gem5  v22.0.0.2
thread_context.hh
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41 
42 #ifndef __CPU_O3_THREAD_CONTEXT_HH__
43 #define __CPU_O3_THREAD_CONTEXT_HH__
44 
45 #include "config/the_isa.hh"
46 #include "cpu/o3/cpu.hh"
47 #include "cpu/thread_context.hh"
48 
49 namespace gem5
50 {
51 
52 namespace o3
53 {
54 
69 {
70  public:
72  CPU *cpu;
73 
74  bool
75  schedule(PCEvent *e) override
76  {
77  return thread->pcEventQueue.schedule(e);
78  }
79  bool
80  remove(PCEvent *e) override
81  {
82  return thread->pcEventQueue.remove(e);
83  }
84 
85  void
87  {
89  }
90  void
92  {
94  }
95  Tick
97  {
99  }
100 
103 
105  BaseMMU *getMMUPtr() override { return cpu->mmu; }
106 
107  CheckerCPU *getCheckerCpuPtr() override { return NULL; }
108 
109  BaseISA *
110  getIsaPtr() const override
111  {
112  return cpu->isa[thread->threadId()];
113  }
114 
115  InstDecoder *
116  getDecoderPtr() override
117  {
118  return cpu->fetch.decoder[thread->threadId()];
119  }
120 
122  BaseCPU *getCpuPtr() override { return cpu; }
123 
125  int cpuId() const override { return cpu->cpuId(); }
126 
128  uint32_t socketId() const override { return cpu->socketId(); }
129 
130  ContextID contextId() const override { return thread->contextId(); }
131 
132  void setContextId(ContextID id) override { thread->setContextId(id); }
133 
135  int threadId() const override { return thread->threadId(); }
136  void setThreadId(int id) override { return thread->setThreadId(id); }
137 
139  System *getSystemPtr() override { return cpu->system; }
140 
142  Process *getProcessPtr() override { return thread->getProcessPtr(); }
143 
144  void setProcessPtr(Process *p) override { thread->setProcessPtr(p); }
145 
147  Status status() const override { return thread->status(); }
148 
150  void
151  setStatus(Status new_status) override
152  {
153  thread->setStatus(new_status);
154  }
155 
157  void activate() override;
158 
160  void suspend() override;
161 
163  void halt() override;
164 
166  void takeOverFrom(gem5::ThreadContext *old_context) override;
167 
169  Tick readLastActivate() override;
171  Tick readLastSuspend() override;
172 
174  void copyArchRegs(gem5::ThreadContext *tc) override;
175 
177  void clearArchRegs() override;
178 
180  const PCStateBase &
181  pcState() const override
182  {
183  return cpu->pcState(thread->threadId());
184  }
185 
187  void pcState(const PCStateBase &val) override;
188 
189  void pcStateNoRecord(const PCStateBase &val) override;
190 
192  RegVal
193  readMiscRegNoEffect(RegIndex misc_reg) const override
194  {
195  return cpu->readMiscRegNoEffect(misc_reg, thread->threadId());
196  }
197 
200  RegVal
201  readMiscReg(RegIndex misc_reg) override
202  {
203  return cpu->readMiscReg(misc_reg, thread->threadId());
204  }
205 
207  void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override;
208 
211  void setMiscReg(RegIndex misc_reg, RegVal val) override;
212 
213  RegId flattenRegId(const RegId& regId) const override;
214 
216  // @todo: Figure out where these store cond failures should go.
217  unsigned
218  readStCondFailures() const override
219  {
220  return thread->storeCondFailures;
221  }
222 
224  void
225  setStCondFailures(unsigned sc_failures) override
226  {
227  thread->storeCondFailures = sc_failures;
228  }
229 
235  void
237  {
240  }
241 
242  RegVal getRegFlat(const RegId &reg) const override;
243  void getRegFlat(const RegId &reg, void *val) const override;
244  void *getWritableRegFlat(const RegId &reg) override;
245 
246  void setRegFlat(const RegId &reg, RegVal val) override;
247  void setRegFlat(const RegId &reg, const void *val) override;
248 
249  // hardware transactional memory
250  void htmAbortTransaction(uint64_t htm_uid,
251  HtmFailureFaultCause cause) override;
253  void setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) override;
254 };
255 
256 } // namespace o3
257 } // namespace gem5
258 
259 #endif
gem5::o3::ThreadContext::remove
bool remove(PCEvent *e) override
Definition: thread_context.hh:80
gem5::o3::ThreadContext::getCpuPtr
BaseCPU * getCpuPtr() override
Returns a pointer to this CPU.
Definition: thread_context.hh:122
gem5::o3::ThreadContext::thread
ThreadState * thread
Pointer to the thread state that this TC corrseponds to.
Definition: thread_context.hh:102
gem5::BaseHTMCheckpointPtr
std::unique_ptr< BaseHTMCheckpoint > BaseHTMCheckpointPtr
Definition: htm.hh:125
gem5::o3::ThreadContext::htmAbortTransaction
void htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) override
Definition: thread_context.cc:224
gem5::o3::ThreadContext::activate
void activate() override
Set the status to Active.
Definition: thread_context.cc:70
gem5::o3::ThreadContext::takeOverFrom
void takeOverFrom(gem5::ThreadContext *old_context) override
Takes over execution of a thread from another CPU.
Definition: thread_context.cc:55
gem5::o3::ThreadContext::socketId
uint32_t socketId() const override
Reads this CPU's Socket ID.
Definition: thread_context.hh:128
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::o3::ThreadContext::getHtmCheckpointPtr
BaseHTMCheckpointPtr & getHtmCheckpointPtr() override
Definition: thread_context.cc:233
gem5::o3::CPU::mmu
BaseMMU * mmu
Definition: cpu.hh:111
gem5::HtmFailureFaultCause
HtmFailureFaultCause
Definition: htm.hh:47
gem5::o3::ThreadContext::getIsaPtr
BaseISA * getIsaPtr() const override
Definition: thread_context.hh:110
gem5::o3::ThreadContext::threadId
int threadId() const override
Returns this thread's ID number.
Definition: thread_context.hh:135
gem5::MipsISA::event
Bitfield< 10, 5 > event
Definition: pra_constants.hh:300
gem5::o3::ThreadContext::setStatus
void setStatus(Status new_status) override
Sets this thread's status.
Definition: thread_context.hh:151
gem5::o3::ThreadState::pcEventQueue
PCEventQueue pcEventQueue
Definition: thread_state.hh:69
gem5::o3::ThreadContext::readMiscRegNoEffect
RegVal readMiscRegNoEffect(RegIndex misc_reg) const override
Reads a miscellaneous register.
Definition: thread_context.hh:193
gem5::ArmISA::e
Bitfield< 9 > e
Definition: misc_types.hh:65
gem5::PCEventQueue::remove
bool remove(PCEvent *event) override
Definition: pc_event.cc:51
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::ThreadContext::Status
Status
Definition: thread_context.hh:105
gem5::PCEventQueue::schedule
bool schedule(PCEvent *event) override
Definition: pc_event.cc:71
gem5::o3::ThreadContext::getProcessPtr
Process * getProcessPtr() override
Returns a pointer to this thread's process.
Definition: thread_context.hh:142
gem5::o3::ThreadContext::getCheckerCpuPtr
CheckerCPU * getCheckerCpuPtr() override
Definition: thread_context.hh:107
gem5::o3::ThreadContext::getSystemPtr
System * getSystemPtr() override
Returns a pointer to the system.
Definition: thread_context.hh:139
gem5::o3::ThreadContext::schedule
bool schedule(PCEvent *e) override
Definition: thread_context.hh:75
gem5::o3::ThreadContext::conditionalSquash
void conditionalSquash()
check if the cpu is currently in state update mode and squash if not.
Definition: thread_context.hh:236
gem5::o3::Fetch::decoder
InstDecoder * decoder[MaxThreads]
The decoder.
Definition: fetch.hh:359
gem5::BaseMMU
Definition: mmu.hh:53
gem5::o3::ThreadContext::getDecoderPtr
InstDecoder * getDecoderPtr() override
Definition: thread_context.hh:116
gem5::o3::ThreadContext
Derived ThreadContext class for use with the O3CPU.
Definition: thread_context.hh:68
gem5::o3::ThreadContext::setRegFlat
void setRegFlat(const RegId &reg, RegVal val) override
Definition: thread_context.cc:171
gem5::o3::ThreadContext::readStCondFailures
unsigned readStCondFailures() const override
Returns the number of consecutive store conditional failures.
Definition: thread_context.hh:218
gem5::System
Definition: system.hh:75
gem5::o3::CPU
O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buff...
Definition: cpu.hh:94
gem5::o3::ThreadContext::suspend
void suspend() override
Set the status to Suspended.
Definition: thread_context.cc:86
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::o3::ThreadContext::flattenRegId
RegId flattenRegId(const RegId &regId) const override
Definition: thread_context.cc:201
gem5::o3::ThreadContext::readMiscReg
RegVal readMiscReg(RegIndex misc_reg) override
Reads a misc.
Definition: thread_context.hh:201
gem5::InstDecoder
Definition: decoder.hh:42
gem5::Event
Definition: eventq.hh:251
gem5::o3::CPU::fetch
Fetch fetch
The fetch stage.
Definition: cpu.hh:403
gem5::X86ISA::count
count
Definition: misc.hh:703
gem5::EventQueue::deschedule
void deschedule(Event *event)
Deschedule the specified event.
Definition: eventq.hh:797
gem5::ThreadState::storeCondFailures
unsigned storeCondFailures
Definition: thread_state.hh:138
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::PCEvent
Definition: pc_event.hh:45
gem5::CheckerCPU
CheckerCPU class.
Definition: cpu.hh:84
gem5::o3::CPU::pcState
void pcState(const PCStateBase &new_pc_state, ThreadID tid)
Sets the commit PC state of a specific thread.
Definition: cpu.cc:1201
gem5::o3::ThreadContext::getMMUPtr
BaseMMU * getMMUPtr() override
Returns a pointer to the MMU.
Definition: thread_context.hh:105
gem5::o3::CPU::squashFromTC
void squashFromTC(ThreadID tid)
Initiates a squash of all in-flight instructions for a given thread.
Definition: cpu.cc:1207
gem5::o3::ThreadContext::setMiscRegNoEffect
void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
Sets a misc.
Definition: thread_context.cc:207
gem5::o3::CPU::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid) const
Register accessors.
Definition: cpu.cc:1014
gem5::o3::ThreadContext::getWritableRegFlat
void * getWritableRegFlat(const RegId &reg) override
Definition: thread_context.cc:159
gem5::o3::ThreadContext::cpuId
int cpuId() const override
Reads this CPU's ID.
Definition: thread_context.hh:125
gem5::ThreadState::setThreadId
void setThreadId(ThreadID id)
Definition: thread_state.hh:67
gem5::o3::ThreadContext::setHtmCheckpointPtr
void setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) override
Definition: thread_context.cc:239
gem5::ThreadState::threadId
ThreadID threadId() const
Definition: thread_state.hh:69
gem5::o3::ThreadState::comInstEventQueue
EventQueue comInstEventQueue
An instruction-based event queue.
Definition: thread_state.hh:74
gem5::o3::ThreadContext::getCurrentInstCount
Tick getCurrentInstCount() override
Definition: thread_context.hh:96
gem5::EventQueue::getCurTick
Tick getCurTick() const
While curTick() is useful for any object assigned to this event queue, if an object that is assigned ...
Definition: eventq.hh:857
gem5::ThreadState::setStatus
void setStatus(Status new_status)
Sets the status of this thread.
Definition: thread_state.hh:83
gem5::ThreadState::contextId
ContextID contextId() const
Definition: thread_state.hh:63
gem5::o3::ThreadContext::setStCondFailures
void setStCondFailures(unsigned sc_failures) override
Sets the number of consecutive store conditional failures.
Definition: thread_context.hh:225
gem5::o3::ThreadContext::getRegFlat
RegVal getRegFlat(const RegId &reg) const override
Flat register interfaces.
Definition: thread_context.cc:153
gem5::ThreadState::setContextId
void setContextId(ContextID id)
Definition: thread_state.hh:65
gem5::o3::ThreadContext::setContextId
void setContextId(ContextID id) override
Definition: thread_context.hh:132
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::Process
Definition: process.hh:68
gem5::o3::CPU::system
System * system
Pointer to the system.
Definition: cpu.hh:528
gem5::o3::ThreadState::noSquashFromTC
bool noSquashFromTC
Definition: thread_state.hh:84
gem5::o3::ThreadContext::status
Status status() const override
Returns this thread's status.
Definition: thread_context.hh:147
gem5::o3::ThreadState
Class that has various thread state, such as the status, the current instruction being processed,...
Definition: thread_state.hh:66
gem5::o3::ThreadContext::halt
void halt() override
Set the status to Halted.
Definition: thread_context.cc:107
gem5::o3::ThreadContext::clearArchRegs
void clearArchRegs() override
Resets all architectural registers to 0.
Definition: thread_context.cc:147
gem5::ThreadState::setProcessPtr
void setProcessPtr(Process *p)
Definition: thread_state.hh:77
gem5::o3::ThreadContext::scheduleInstCountEvent
void scheduleInstCountEvent(Event *event, Tick count) override
Definition: thread_context.hh:86
gem5::o3::ThreadContext::copyArchRegs
void copyArchRegs(gem5::ThreadContext *tc) override
Copies the architectural registers from another TC into this TC.
Definition: thread_context.cc:138
gem5::o3::ThreadContext::readLastSuspend
Tick readLastSuspend() override
Reads the last tick that this thread was suspended on.
Definition: thread_context.cc:132
gem5::o3::ThreadContext::setProcessPtr
void setProcessPtr(Process *p) override
Definition: thread_context.hh:144
gem5::ThreadState::status
Status status() const
Returns the status of this thread.
Definition: thread_state.hh:80
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:239
gem5::o3::CPU::readMiscReg
RegVal readMiscReg(int misc_reg, ThreadID tid)
Reads a misc.
Definition: cpu.cc:1020
gem5::EventQueue::schedule
void schedule(Event *event, Tick when, bool global=false)
Schedule the given event on this queue.
Definition: eventq.hh:764
gem5::o3::ThreadContext::pcState
const PCStateBase & pcState() const override
Reads this thread's PC state.
Definition: thread_context.hh:181
gem5::o3::ThreadContext::descheduleInstCountEvent
void descheduleInstCountEvent(Event *event) override
Definition: thread_context.hh:91
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::o3::ThreadContext::cpu
CPU * cpu
Pointer to the CPU.
Definition: thread_context.hh:72
gem5::BaseISA
Definition: isa.hh:57
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
cpu.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::o3::ThreadContext::pcStateNoRecord
void pcStateNoRecord(const PCStateBase &val) override
Definition: thread_context.cc:193
gem5::o3::ThreadContext::readLastActivate
Tick readLastActivate() override
Reads the last tick that this thread was activated on.
Definition: thread_context.cc:126
gem5::o3::ThreadContext::setThreadId
void setThreadId(int id) override
Definition: thread_context.hh:136
gem5::o3::ThreadState::trapPending
bool trapPending
Whether or not the thread is currently waiting on a trap, and thus able to be externally updated with...
Definition: thread_state.hh:89
gem5::o3::ThreadContext::setMiscReg
void setMiscReg(RegIndex misc_reg, RegVal val) override
Sets a misc.
Definition: thread_context.cc:215
thread_context.hh
gem5::o3::CPU::isa
std::vector< TheISA::ISA * > isa
Definition: cpu.hh:445
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:126
gem5::o3::ThreadContext::contextId
ContextID contextId() const override
Definition: thread_context.hh:130
gem5::ThreadState::getProcessPtr
Process * getProcessPtr()
Definition: thread_state.hh:75

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