gem5  v21.1.0.2
thread_context.hh
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41 
42 #ifndef __CPU_O3_THREAD_CONTEXT_HH__
43 #define __CPU_O3_THREAD_CONTEXT_HH__
44 
45 #include "config/the_isa.hh"
46 #include "cpu/o3/cpu.hh"
47 #include "cpu/thread_context.hh"
48 
49 namespace gem5
50 {
51 
52 namespace o3
53 {
54 
69 {
70  public:
72  CPU *cpu;
73 
74  bool
75  schedule(PCEvent *e) override
76  {
77  return thread->pcEventQueue.schedule(e);
78  }
79  bool
80  remove(PCEvent *e) override
81  {
82  return thread->pcEventQueue.remove(e);
83  }
84 
85  void
87  {
89  }
90  void
92  {
94  }
95  Tick
97  {
99  }
100 
103 
105  BaseMMU *getMMUPtr() override { return cpu->mmu; }
106 
107  CheckerCPU *getCheckerCpuPtr() override { return NULL; }
108 
109  BaseISA *
110  getIsaPtr() override
111  {
112  return cpu->isa[thread->threadId()];
113  }
114 
115  TheISA::Decoder *
116  getDecoderPtr() override
117  {
118  return cpu->fetch.decoder[thread->threadId()];
119  }
120 
122  BaseCPU *getCpuPtr() override { return cpu; }
123 
125  int cpuId() const override { return cpu->cpuId(); }
126 
128  uint32_t socketId() const override { return cpu->socketId(); }
129 
130  ContextID contextId() const override { return thread->contextId(); }
131 
132  void setContextId(ContextID id) override { thread->setContextId(id); }
133 
135  int threadId() const override { return thread->threadId(); }
136  void setThreadId(int id) override { return thread->setThreadId(id); }
137 
139  System *getSystemPtr() override { return cpu->system; }
140 
142  Process *getProcessPtr() override { return thread->getProcessPtr(); }
143 
144  void setProcessPtr(Process *p) override { thread->setProcessPtr(p); }
145 
146  PortProxy &getVirtProxy() override;
147 
148  void
150  {
151  thread->initMemProxies(tc);
152  }
153 
155  Status status() const override { return thread->status(); }
156 
158  void
159  setStatus(Status new_status) override
160  {
161  thread->setStatus(new_status);
162  }
163 
165  void activate() override;
166 
168  void suspend() override;
169 
171  void halt() override;
172 
174  void takeOverFrom(gem5::ThreadContext *old_context) override;
175 
177  Tick readLastActivate() override;
179  Tick readLastSuspend() override;
180 
182  void copyArchRegs(gem5::ThreadContext *tc) override;
183 
185  void clearArchRegs() override;
186 
188  RegVal
189  readReg(RegIndex reg_idx)
190  {
192  reg_idx)).index());
193  }
194  RegVal
195  readIntReg(RegIndex reg_idx) const override
196  {
198  reg_idx)).index());
199  }
200 
201  RegVal
202  readFloatReg(RegIndex reg_idx) const override
203  {
205  reg_idx)).index());
206  }
207 
209  readVecReg(const RegId& id) const override
210  {
211  return readVecRegFlat(flattenRegId(id).index());
212  }
213 
218  getWritableVecReg(const RegId& id) override
219  {
221  }
222 
223  const TheISA::VecElem &
224  readVecElem(const RegId& reg) const override
225  {
226  return readVecElemFlat(flattenRegId(reg).index(), reg.elemIndex());
227  }
228 
230  readVecPredReg(const RegId& id) const override
231  {
232  return readVecPredRegFlat(flattenRegId(id).index());
233  }
234 
236  getWritableVecPredReg(const RegId& id) override
237  {
239  }
240 
241  RegVal
242  readCCReg(RegIndex reg_idx) const override
243  {
245  reg_idx)).index());
246  }
247 
249  void
250  setIntReg(RegIndex reg_idx, RegVal val) override
251  {
253  }
254 
255  void
256  setFloatReg(RegIndex reg_idx, RegVal val) override
257  {
259  reg_idx)).index(), val);
260  }
261 
262  void
263  setVecReg(const RegId& reg, const TheISA::VecRegContainer& val) override
264  {
266  }
267 
268  void
269  setVecElem(const RegId& reg, const TheISA::VecElem& val) override
270  {
271  setVecElemFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
272  }
273 
274  void
276  const TheISA::VecPredRegContainer& val) override
277  {
279  }
280 
281  void
282  setCCReg(RegIndex reg_idx, RegVal val) override
283  {
285  }
286 
289  pcState() const override
290  {
291  return cpu->pcState(thread->threadId());
292  }
293 
295  void pcState(const TheISA::PCState &val) override;
296 
297  void pcStateNoRecord(const TheISA::PCState &val) override;
298 
300  Addr
301  instAddr() const override
302  {
303  return cpu->instAddr(thread->threadId());
304  }
305 
307  Addr
308  nextInstAddr() const override
309  {
310  return cpu->nextInstAddr(thread->threadId());
311  }
312 
314  MicroPC
315  microPC() const override
316  {
317  return cpu->microPC(thread->threadId());
318  }
319 
321  RegVal
322  readMiscRegNoEffect(RegIndex misc_reg) const override
323  {
324  return cpu->readMiscRegNoEffect(misc_reg, thread->threadId());
325  }
326 
329  RegVal
330  readMiscReg(RegIndex misc_reg) override
331  {
332  return cpu->readMiscReg(misc_reg, thread->threadId());
333  }
334 
336  void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override;
337 
340  void setMiscReg(RegIndex misc_reg, RegVal val) override;
341 
342  RegId flattenRegId(const RegId& regId) const override;
343 
345  // @todo: Figure out where these store cond failures should go.
346  unsigned
347  readStCondFailures() const override
348  {
349  return thread->storeCondFailures;
350  }
351 
353  void
354  setStCondFailures(unsigned sc_failures) override
355  {
356  thread->storeCondFailures = sc_failures;
357  }
358 
364  void
366  {
369  }
370 
371  RegVal readIntRegFlat(RegIndex idx) const override;
372  void setIntRegFlat(RegIndex idx, RegVal val) override;
373 
374  RegVal readFloatRegFlat(RegIndex idx) const override;
375  void setFloatRegFlat(RegIndex idx, RegVal val) override;
376 
377  const TheISA::VecRegContainer& readVecRegFlat(RegIndex idx) const override;
380  void setVecRegFlat(RegIndex idx,
381  const TheISA::VecRegContainer& val) override;
382 
384  const ElemIndex& elemIndex) const override;
385  void setVecElemFlat(RegIndex idx, const ElemIndex& elemIdx,
386  const TheISA::VecElem& val) override;
387 
389  readVecPredRegFlat(RegIndex idx) const override;
391  getWritableVecPredRegFlat(RegIndex idx) override;
392  void setVecPredRegFlat(RegIndex idx,
393  const TheISA::VecPredRegContainer& val) override;
394 
395  RegVal readCCRegFlat(RegIndex idx) const override;
396  void setCCRegFlat(RegIndex idx, RegVal val) override;
397 
398  // hardware transactional memory
399  void htmAbortTransaction(uint64_t htm_uid,
400  HtmFailureFaultCause cause) override;
402  void setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) override;
403 };
404 
405 } // namespace o3
406 } // namespace gem5
407 
408 #endif
gem5::o3::ThreadContext::getDecoderPtr
TheISA::Decoder * getDecoderPtr() override
Definition: thread_context.hh:116
gem5::o3::ThreadContext::remove
bool remove(PCEvent *e) override
Definition: thread_context.hh:80
gem5::o3::ThreadContext::readVecElemFlat
const TheISA::VecElem & readVecElemFlat(RegIndex idx, const ElemIndex &elemIndex) const override
Definition: thread_context.cc:186
gem5::o3::ThreadContext::getCpuPtr
BaseCPU * getCpuPtr() override
Returns a pointer to this CPU.
Definition: thread_context.hh:122
gem5::ThreadState::initMemProxies
void initMemProxies(ThreadContext *tc)
Initialise the physical and virtual port proxies and tie them to the data port of the CPU.
Definition: thread_state.cc:72
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:64
gem5::o3::ThreadContext::thread
ThreadState * thread
Pointer to the thread state that this TC corrseponds to.
Definition: thread_context.hh:102
gem5::o3::ThreadContext::getVirtProxy
PortProxy & getVirtProxy() override
Definition: thread_context.cc:55
gem5::BaseHTMCheckpointPtr
std::unique_ptr< BaseHTMCheckpoint > BaseHTMCheckpointPtr
Definition: htm.hh:125
gem5::o3::ThreadContext::readCCReg
RegVal readCCReg(RegIndex reg_idx) const override
Definition: thread_context.hh:242
gem5::o3::ThreadContext::htmAbortTransaction
void htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) override
Definition: thread_context.cc:299
gem5::o3::ThreadContext::readVecReg
const TheISA::VecRegContainer & readVecReg(const RegId &id) const override
Definition: thread_context.hh:209
gem5::o3::ThreadContext::setCCReg
void setCCReg(RegIndex reg_idx, RegVal val) override
Definition: thread_context.hh:282
gem5::o3::ThreadContext::readVecElem
const TheISA::VecElem & readVecElem(const RegId &reg) const override
Definition: thread_context.hh:224
gem5::o3::ThreadContext::activate
void activate() override
Set the status to Active.
Definition: thread_context.cc:76
gem5::o3::ThreadContext::takeOverFrom
void takeOverFrom(gem5::ThreadContext *old_context) override
Takes over execution of a thread from another CPU.
Definition: thread_context.cc:61
gem5::o3::ThreadContext::socketId
uint32_t socketId() const override
Reads this CPU's Socket ID.
Definition: thread_context.hh:128
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::o3::ThreadContext::getHtmCheckpointPtr
BaseHTMCheckpointPtr & getHtmCheckpointPtr() override
Definition: thread_context.cc:308
gem5::o3::CPU::mmu
BaseMMU * mmu
Definition: cpu.hh:112
gem5::ArmISA::VecPredRegContainer
VecPredReg::Container VecPredRegContainer
Definition: vec.hh:68
gem5::HtmFailureFaultCause
HtmFailureFaultCause
Definition: htm.hh:47
gem5::MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:47
gem5::o3::ThreadContext::getWritableVecRegFlat
TheISA::VecRegContainer & getWritableVecRegFlat(RegIndex idx) override
Read vector register operand for modification, flat indexing.
Definition: thread_context.cc:180
gem5::o3::ThreadContext::getWritableVecPredReg
TheISA::VecPredRegContainer & getWritableVecPredReg(const RegId &id) override
Definition: thread_context.hh:236
gem5::o3::ThreadContext::threadId
int threadId() const override
Returns this thread's ID number.
Definition: thread_context.hh:135
gem5::o3::ThreadContext::setVecPredReg
void setVecPredReg(const RegId &reg, const TheISA::VecPredRegContainer &val) override
Definition: thread_context.hh:275
gem5::MipsISA::event
Bitfield< 10, 5 > event
Definition: pra_constants.hh:300
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:58
gem5::o3::ThreadContext::setStatus
void setStatus(Status new_status) override
Sets this thread's status.
Definition: thread_context.hh:159
gem5::o3::ThreadState::pcEventQueue
PCEventQueue pcEventQueue
Definition: thread_state.hh:69
gem5::o3::ThreadContext::readMiscRegNoEffect
RegVal readMiscRegNoEffect(RegIndex misc_reg) const override
Reads a miscellaneous register.
Definition: thread_context.hh:322
gem5::ArmISA::e
Bitfield< 9 > e
Definition: misc_types.hh:64
gem5::PCEventQueue::remove
bool remove(PCEvent *event) override
Definition: pc_event.cc:51
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::o3::ThreadContext::setVecElem
void setVecElem(const RegId &reg, const TheISA::VecElem &val) override
Definition: thread_context.hh:269
gem5::ThreadContext::Status
Status
Definition: thread_context.hh:104
gem5::PCEventQueue::schedule
bool schedule(PCEvent *event) override
Definition: pc_event.cc:71
gem5::o3::ThreadContext::setCCRegFlat
void setCCRegFlat(RegIndex idx, RegVal val) override
Definition: thread_context.cc:252
gem5::o3::ThreadContext::initMemProxies
void initMemProxies(gem5::ThreadContext *tc) override
Initialise the physical and virtual port proxies and tie them to the data port of the CPU.
Definition: thread_context.hh:149
gem5::o3::ThreadContext::getProcessPtr
Process * getProcessPtr() override
Returns a pointer to this thread's process.
Definition: thread_context.hh:142
gem5::o3::ThreadContext::getCheckerCpuPtr
CheckerCPU * getCheckerCpuPtr() override
Definition: thread_context.hh:107
gem5::BaseCPU::socketId
uint32_t socketId() const
Reads this CPU's Socket ID.
Definition: base.hh:191
gem5::o3::ThreadContext::getSystemPtr
System * getSystemPtr() override
Returns a pointer to the system.
Definition: thread_context.hh:139
gem5::o3::ThreadContext::schedule
bool schedule(PCEvent *e) override
Definition: thread_context.hh:75
gem5::o3::ThreadContext::readVecPredRegFlat
const TheISA::VecPredRegContainer & readVecPredRegFlat(RegIndex idx) const override
Definition: thread_context.cc:192
gem5::o3::ThreadContext::conditionalSquash
void conditionalSquash()
check if the cpu is currently in state update mode and squash if not.
Definition: thread_context.hh:365
gem5::BaseMMU
Definition: mmu.hh:50
gem5::o3::ThreadContext::setFloatRegFlat
void setFloatRegFlat(RegIndex idx, RegVal val) override
Definition: thread_context.cc:218
gem5::o3::ThreadContext::readFloatRegFlat
RegVal readFloatRegFlat(RegIndex idx) const override
Definition: thread_context.cc:168
gem5::o3::ThreadContext
Derived ThreadContext class for use with the O3CPU.
Definition: thread_context.hh:68
gem5::MicroPC
uint16_t MicroPC
Definition: types.hh:149
gem5::o3::ThreadContext::readStCondFailures
unsigned readStCondFailures() const override
Returns the number of consecutive store conditional failures.
Definition: thread_context.hh:347
gem5::System
Definition: system.hh:77
gem5::o3::ThreadContext::pcStateNoRecord
void pcStateNoRecord(const TheISA::PCState &val) override
Definition: thread_context.cc:268
gem5::o3::CPU
O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buff...
Definition: cpu.hh:95
gem5::o3::ThreadContext::suspend
void suspend() override
Set the status to Suspended.
Definition: thread_context.cc:92
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::o3::ThreadContext::flattenRegId
RegId flattenRegId(const RegId &regId) const override
Definition: thread_context.cc:276
gem5::o3::ThreadContext::readMiscReg
RegVal readMiscReg(RegIndex misc_reg) override
Reads a misc.
Definition: thread_context.hh:330
gem5::Event
Definition: eventq.hh:251
gem5::o3::CPU::fetch
Fetch fetch
The fetch stage.
Definition: cpu.hh:483
gem5::X86ISA::count
count
Definition: misc.hh:709
gem5::EventQueue::deschedule
void deschedule(Event *event)
Deschedule the specified event.
Definition: eventq.hh:797
gem5::ThreadState::storeCondFailures
unsigned storeCondFailures
Definition: thread_state.hh:152
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::o3::ThreadContext::setVecRegFlat
void setVecRegFlat(RegIndex idx, const TheISA::VecRegContainer &val) override
Definition: thread_context.cc:226
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::PCEvent
Definition: pc_event.hh:45
gem5::CheckerCPU
CheckerCPU class.
Definition: cpu.hh:84
gem5::o3::ThreadContext::getWritableVecPredRegFlat
TheISA::VecPredRegContainer & getWritableVecPredRegFlat(RegIndex idx) override
Definition: thread_context.cc:198
gem5::o3::ThreadContext::getMMUPtr
BaseMMU * getMMUPtr() override
Returns a pointer to the MMU.
Definition: thread_context.hh:105
gem5::o3::CPU::squashFromTC
void squashFromTC(ThreadID tid)
Initiates a squash of all in-flight instructions for a given thread.
Definition: cpu.cc:1405
gem5::o3::ThreadContext::readIntReg
RegVal readIntReg(RegIndex reg_idx) const override
Definition: thread_context.hh:195
gem5::o3::ThreadContext::setMiscRegNoEffect
void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
Sets a misc.
Definition: thread_context.cc:282
gem5::o3::CPU::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid) const
Register accessors.
Definition: cpu.cc:1122
gem5::o3::ThreadContext::cpuId
int cpuId() const override
Reads this CPU's ID.
Definition: thread_context.hh:125
gem5::o3::ThreadContext::setVecElemFlat
void setVecElemFlat(RegIndex idx, const ElemIndex &elemIdx, const TheISA::VecElem &val) override
Definition: thread_context.cc:235
gem5::PortProxy
This object is a proxy for a port or other object which implements the functional response protocol,...
Definition: port_proxy.hh:86
gem5::o3::ThreadContext::pcState
TheISA::PCState pcState() const override
Reads this thread's PC state.
Definition: thread_context.hh:289
gem5::ThreadState::setThreadId
void setThreadId(ThreadID id)
Definition: thread_state.hh:67
gem5::o3::ThreadContext::setHtmCheckpointPtr
void setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) override
Definition: thread_context.cc:314
gem5::BaseCPU
Definition: base.hh:107
gem5::ArmISA::VecRegContainer
gem5::VecRegContainer< NumVecElemPerVecReg *sizeof(VecElem)> VecRegContainer
Definition: vec.hh:62
gem5::o3::ThreadContext::setVecReg
void setVecReg(const RegId &reg, const TheISA::VecRegContainer &val) override
Definition: thread_context.hh:263
gem5::ThreadState::threadId
ThreadID threadId() const
Definition: thread_state.hh:69
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::o3::ThreadContext::readVecPredReg
const TheISA::VecPredRegContainer & readVecPredReg(const RegId &id) const override
Definition: thread_context.hh:230
gem5::o3::ThreadState::comInstEventQueue
EventQueue comInstEventQueue
An instruction-based event queue.
Definition: thread_state.hh:74
gem5::ElemIndex
uint16_t ElemIndex
Logical vector register elem index type.
Definition: types.hh:179
gem5::o3::CPU::instAddr
Addr instAddr(ThreadID tid)
Reads the commit PC of a specific thread.
Definition: cpu.cc:1387
gem5::o3::ThreadContext::getCurrentInstCount
Tick getCurrentInstCount() override
Definition: thread_context.hh:96
gem5::EventQueue::getCurTick
Tick getCurTick() const
While curTick() is useful for any object assigned to this event queue, if an object that is assigned ...
Definition: eventq.hh:857
gem5::o3::ThreadContext::readVecRegFlat
const TheISA::VecRegContainer & readVecRegFlat(RegIndex idx) const override
Definition: thread_context.cc:174
gem5::ThreadState::setStatus
void setStatus(Status new_status)
Sets the status of this thread.
Definition: thread_state.hh:93
gem5::ThreadState::contextId
ContextID contextId() const
Definition: thread_state.hh:63
gem5::o3::ThreadContext::setStCondFailures
void setStCondFailures(unsigned sc_failures) override
Sets the number of consecutive store conditional failures.
Definition: thread_context.hh:354
gem5::ThreadState::setContextId
void setContextId(ContextID id)
Definition: thread_state.hh:65
gem5::o3::ThreadContext::setContextId
void setContextId(ContextID id) override
Definition: thread_context.hh:132
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::Process
Definition: process.hh:67
gem5::o3::CPU::system
System * system
Pointer to the system.
Definition: cpu.hh:605
gem5::o3::ThreadState::noSquashFromTC
bool noSquashFromTC
Definition: thread_state.hh:84
gem5::o3::ThreadContext::status
Status status() const override
Returns this thread's status.
Definition: thread_context.hh:155
gem5::o3::ThreadState
Class that has various thread state, such as the status, the current instruction being processed,...
Definition: thread_state.hh:66
gem5::o3::ThreadContext::halt
void halt() override
Set the status to Halted.
Definition: thread_context.cc:113
gem5::o3::ThreadContext::clearArchRegs
void clearArchRegs() override
Resets all architectural registers to 0.
Definition: thread_context.cc:156
gem5::ThreadState::setProcessPtr
void setProcessPtr(Process *p)
Definition: thread_state.hh:87
gem5::o3::ThreadContext::scheduleInstCountEvent
void scheduleInstCountEvent(Event *event, Tick count) override
Definition: thread_context.hh:86
gem5::o3::ThreadContext::readCCRegFlat
RegVal readCCRegFlat(RegIndex idx) const override
Definition: thread_context.cc:204
gem5::o3::ThreadContext::copyArchRegs
void copyArchRegs(gem5::ThreadContext *tc) override
Copies the architectural registers from another TC into this TC.
Definition: thread_context.cc:144
gem5::o3::ThreadContext::getIsaPtr
BaseISA * getIsaPtr() override
Definition: thread_context.hh:110
gem5::o3::ThreadContext::instAddr
Addr instAddr() const override
Reads this thread's PC.
Definition: thread_context.hh:301
gem5::o3::ThreadContext::readFloatReg
RegVal readFloatReg(RegIndex reg_idx) const override
Definition: thread_context.hh:202
gem5::o3::ThreadContext::readLastSuspend
Tick readLastSuspend() override
Reads the last tick that this thread was suspended on.
Definition: thread_context.cc:138
gem5::ArmISA::VecElem
uint32_t VecElem
Definition: vec.hh:60
gem5::BaseCPU::cpuId
int cpuId() const
Reads this CPU's ID.
Definition: base.hh:188
gem5::o3::ThreadContext::nextInstAddr
Addr nextInstAddr() const override
Reads this thread's next PC.
Definition: thread_context.hh:308
gem5::o3::CPU::microPC
MicroPC microPC(ThreadID tid)
Reads the commit micro PC of a specific thread.
Definition: cpu.cc:1399
gem5::o3::ThreadContext::setProcessPtr
void setProcessPtr(Process *p) override
Definition: thread_context.hh:144
gem5::o3::ThreadContext::getWritableVecReg
TheISA::VecRegContainer & getWritableVecReg(const RegId &id) override
Read vector register operand for modification, hierarchical indexing.
Definition: thread_context.hh:218
gem5::ThreadState::status
Status status() const
Returns the status of this thread.
Definition: thread_state.hh:90
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:246
gem5::o3::CPU::readMiscReg
RegVal readMiscReg(int misc_reg, ThreadID tid)
Reads a misc.
Definition: cpu.cc:1128
gem5::EventQueue::schedule
void schedule(Event *event, Tick when, bool global=false)
Schedule the given event on this queue.
Definition: eventq.hh:764
gem5::o3::ThreadContext::descheduleInstCountEvent
void descheduleInstCountEvent(Event *event) override
Definition: thread_context.hh:91
gem5::o3::ThreadContext::microPC
MicroPC microPC() const override
Reads this thread's next PC.
Definition: thread_context.hh:315
gem5::o3::ThreadContext::cpu
CPU * cpu
Pointer to the CPU.
Definition: thread_context.hh:72
gem5::o3::ThreadContext::setIntRegFlat
void setIntRegFlat(RegIndex idx, RegVal val) override
Definition: thread_context.cc:210
gem5::o3::ThreadContext::setIntReg
void setIntReg(RegIndex reg_idx, RegVal val) override
Sets an integer register to a value.
Definition: thread_context.hh:250
gem5::BaseISA
Definition: isa.hh:54
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
cpu.hh
gem5::o3::ThreadContext::setFloatReg
void setFloatReg(RegIndex reg_idx, RegVal val) override
Definition: thread_context.hh:256
gem5::o3::CPU::pcState
void pcState(const TheISA::PCState &newPCState, ThreadID tid)
Sets the commit PC state of a specific thread.
Definition: cpu.cc:1381
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:57
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::o3::ThreadContext::setVecPredRegFlat
void setVecPredRegFlat(RegIndex idx, const TheISA::VecPredRegContainer &val) override
Definition: thread_context.cc:243
gem5::o3::ThreadContext::readReg
RegVal readReg(RegIndex reg_idx)
Reads an integer register.
Definition: thread_context.hh:189
gem5::o3::CPU::nextInstAddr
Addr nextInstAddr(ThreadID tid)
Reads the next PC of a specific thread.
Definition: cpu.cc:1393
gem5::o3::ThreadContext::readLastActivate
Tick readLastActivate() override
Reads the last tick that this thread was activated on.
Definition: thread_context.cc:132
gem5::o3::ThreadContext::setThreadId
void setThreadId(int id) override
Definition: thread_context.hh:136
gem5::o3::ThreadState::trapPending
bool trapPending
Whether or not the thread is currently waiting on a trap, and thus able to be externally updated with...
Definition: thread_state.hh:89
gem5::o3::ThreadContext::setMiscReg
void setMiscReg(RegIndex misc_reg, RegVal val) override
Sets a misc.
Definition: thread_context.cc:290
thread_context.hh
gem5::o3::CPU::isa
std::vector< TheISA::ISA * > isa
Definition: cpu.hh:528
gem5::o3::ThreadContext::readIntRegFlat
RegVal readIntRegFlat(RegIndex idx) const override
Flat register interfaces.
Definition: thread_context.cc:162
gem5::o3::Fetch::decoder
TheISA::Decoder * decoder[MaxThreads]
The decoder.
Definition: fetch.hh:359
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88
gem5::o3::ThreadContext::contextId
ContextID contextId() const override
Definition: thread_context.hh:130
gem5::ThreadState::getProcessPtr
Process * getProcessPtr()
Definition: thread_state.hh:85

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