gem5  v21.2.1.1
hsa_packet_processor.cc
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1 /*
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31 
33 
34 #include <cassert>
35 #include <cstring>
36 
37 #include "base/chunk_generator.hh"
38 #include "base/compiler.hh"
39 #include "base/logging.hh"
40 #include "base/trace.hh"
41 #include "debug/HSAPacketProcessor.hh"
42 #include "dev/dma_device.hh"
43 #include "dev/hsa/hsa_packet.hh"
44 #include "dev/hsa/hw_scheduler.hh"
45 #include "enums/GfxVersion.hh"
47 #include "mem/packet_access.hh"
48 #include "mem/page_table.hh"
49 #include "sim/process.hh"
50 #include "sim/proxy_ptr.hh"
51 #include "sim/system.hh"
52 
53 #define HSAPP_EVENT_DESCRIPTION_GENERATOR(XEVENT) \
54  const char* \
55  HSAPacketProcessor::XEVENT::description() const \
56  { \
57  return #XEVENT; \
58  }
59 
60 #define PKT_TYPE(PKT) ((hsa_packet_type_t)(((PKT->header) >> \
61  HSA_PACKET_HEADER_TYPE) & (HSA_PACKET_HEADER_WIDTH_TYPE - 1)))
62 
63 // checks if the barrier bit is set in the header -- shift the barrier bit
64 // to LSB, then bitwise "and" to mask off all other bits
65 #define IS_BARRIER(PKT) ((hsa_packet_header_t)(((PKT->header) >> \
66  HSA_PACKET_HEADER_BARRIER) & HSA_PACKET_HEADER_WIDTH_BARRIER))
67 
68 namespace gem5
69 {
70 
71 HSAPP_EVENT_DESCRIPTION_GENERATOR(QueueProcessEvent)
72 
74  : DmaVirtDevice(p), numHWQueues(p.numHWQueues), pioAddr(p.pioAddr),
75  pioSize(PAGE_SIZE), pioDelay(10), pktProcessDelay(p.pktProcessDelay)
76 {
77  DPRINTF(HSAPacketProcessor, "%s:\n", __FUNCTION__);
78  hwSchdlr = new HWScheduler(this, p.wakeupDelay);
79  regdQList.resize(numHWQueues);
80  for (int i = 0; i < numHWQueues; i++) {
81  regdQList[i] = new RQLEntry(this, i);
82  }
83 }
84 
86 {
87  for (auto &queue : regdQList) {
88  delete queue;
89  }
90 }
91 
92 void
93 HSAPacketProcessor::unsetDeviceQueueDesc(uint64_t queue_id, int doorbellSize)
94 {
95  hwSchdlr->unregisterQueue(queue_id, doorbellSize);
96 }
97 
98 void
99 HSAPacketProcessor::setDeviceQueueDesc(uint64_t hostReadIndexPointer,
100  uint64_t basePointer,
101  uint64_t queue_id,
102  uint32_t size, int doorbellSize,
103  GfxVersion gfxVersion)
104 {
106  "%s:base = %p, qID = %d, ze = %d\n", __FUNCTION__,
107  (void *)basePointer, queue_id, size);
108  hwSchdlr->registerNewQueue(hostReadIndexPointer,
109  basePointer, queue_id, size, doorbellSize,
110  gfxVersion);
111 }
112 
115 {
116  assert(pioSize != 0);
117 
118  AddrRangeList ranges;
119  ranges.push_back(RangeSize(pioAddr, pioSize));
120 
121  return ranges;
122 }
123 
124 // Basically only processes writes to the queue doorbell register.
125 Tick
127 {
128  assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
129 
130  // TODO: How to get pid??
131  [[maybe_unused]] Addr daddr = pkt->getAddr() - pioAddr;
132 
134  "%s: write of size %d to reg-offset %d (0x%x)\n",
135  __FUNCTION__, pkt->getSize(), daddr, daddr);
136 
137  assert(gpu_device->driver()->doorbellSize() == pkt->getSize());
138 
139  uint64_t doorbell_reg(0);
140  if (pkt->getSize() == 8)
141  doorbell_reg = pkt->getLE<uint64_t>() + 1;
142  else if (pkt->getSize() == 4)
143  doorbell_reg = pkt->getLE<uint32_t>();
144  else
145  fatal("invalid db size");
146 
148  "%s: write data 0x%x to offset %d (0x%x)\n",
149  __FUNCTION__, doorbell_reg, daddr, daddr);
150  hwSchdlr->write(daddr, doorbell_reg);
151  pkt->makeAtomicResponse();
152  return pioDelay;
153 }
154 
155 Tick
157 {
158  pkt->makeAtomicResponse();
159  pkt->setBadAddress();
160  return pioDelay;
161 }
162 
165 {
166  // Grab the process and try to translate the virtual address with it; with
167  // new extensions, it will likely be wrong to just arbitrarily grab context
168  // zero.
169  auto process = sys->threads[0]->getProcessPtr();
170 
171  return process->pTable->translateRange(vaddr, size);
172 }
173 
179 void
181 {
182  DPRINTF(HSAPacketProcessor, "updateReaddispId\n");
183 }
184 
185 void
186 HSAPacketProcessor::updateReadIndex(int pid, uint32_t rl_idx)
187 {
188  AQLRingBuffer* aqlbuf = regdQList[rl_idx]->qCntxt.aqlBuf;
189  HSAQueueDescriptor* qDesc = regdQList[rl_idx]->qCntxt.qDesc;
190  auto cb = new DmaVirtCallback<uint64_t>(
191  [ = ] (const uint32_t &dma_data) { this->updateReadDispIdDma(); }, 0);
192 
194  "%s: read-pointer offset [0x%x]\n", __FUNCTION__, aqlbuf->rdIdx());
195 
196  dmaWriteVirt((Addr)qDesc->hostReadIndexPtr, sizeof(aqlbuf->rdIdx()),
197  cb, aqlbuf->rdIdxPtr());
198 
200  "%s: rd-ptr offset [0x%x], wr-ptr offset [0x%x], space used = %d," \
201  " q size = %d, is_empty = %s, active list ID = %d\n", __FUNCTION__,
202  qDesc->readIndex, qDesc->writeIndex, qDesc->spaceUsed(),
203  qDesc->numElts, qDesc->isEmpty()? "true" : "false", rl_idx);
204  if (qDesc->writeIndex != aqlbuf->wrIdx()) {
205  getCommandsFromHost(pid, rl_idx);
206  }
207 }
208 
209 void
211  bool isRead, uint32_t ix_start, unsigned num_pkts,
212  dma_series_ctx *series_ctx, void *dest_4debug)
213 {
214  uint32_t rl_idx = series_ctx->rl_idx;
215  [[maybe_unused]] AQLRingBuffer *aqlRingBuffer =
216  hsaPP->regdQList[rl_idx]->qCntxt.aqlBuf;
217  HSAQueueDescriptor* qDesc =
218  hsaPP->regdQList[rl_idx]->qCntxt.qDesc;
219  DPRINTF(HSAPacketProcessor, ">%s, ix = %d, npkts = %d," \
220  " pktsRemaining = %d, active list ID = %d\n", __FUNCTION__,
221  ix_start, num_pkts, series_ctx->pkts_2_go,
222  rl_idx);
223  if (isRead) {
224  series_ctx->pkts_2_go -= num_pkts;
225  if (series_ctx->pkts_2_go == 0) {
226  // Mark DMA as completed
227  qDesc->dmaInProgress = false;
229  "%s: schedule Qwakeup next cycle, rdIdx %d, wrIdx %d," \
230  " dispIdx %d, active list ID = %d\n",
231  __FUNCTION__, aqlRingBuffer->rdIdx(),
232  aqlRingBuffer->wrIdx(), aqlRingBuffer->dispIdx(), rl_idx);
233  // schedule queue wakeup
234  hsaPP->schedAQLProcessing(rl_idx);
235  delete series_ctx;
236  }
237  }
238 }
239 
240 void
242 {
243  RQLEntry *queue = regdQList[rl_idx];
244  if (!queue->aqlProcessEvent.scheduled()) {
245  Tick processingTick = curTick() + delay;
246  schedule(queue->aqlProcessEvent, processingTick);
247  DPRINTF(HSAPacketProcessor, "AQL processing scheduled at tick: %d\n",
248  processingTick);
249  } else {
250  DPRINTF(HSAPacketProcessor, "AQL processing already scheduled\n");
251  }
252 }
253 
254 void
256 {
258 }
259 
260 Q_STATE
261 HSAPacketProcessor::processPkt(void* pkt, uint32_t rl_idx, Addr host_pkt_addr)
262 {
263  Q_STATE is_submitted = BLOCKED_BPKT;
264  SignalState *dep_sgnl_rd_st = &(regdQList[rl_idx]->depSignalRdState);
265  // Dependency signals are not read yet. And this can only be a retry.
266  // The retry logic will schedule the packet processor wakeup
267  if (dep_sgnl_rd_st->pendingReads != 0) {
268  return BLOCKED_BPKT;
269  }
270  // `pkt` can be typecasted to any type of AQL packet since they all
271  // have header information at offset zero
272  auto disp_pkt = (_hsa_dispatch_packet_t *)pkt;
273  hsa_packet_type_t pkt_type = PKT_TYPE(disp_pkt);
274  if (IS_BARRIER(disp_pkt) &&
275  regdQList[rl_idx]->compltnPending() > 0) {
276  // If this packet is using the "barrier bit" to enforce ordering with
277  // previous packets, and if there are outstanding packets, set the
278  // barrier bit for this queue and block the queue.
279  DPRINTF(HSAPacketProcessor, "%s: setting barrier bit for active" \
280  " list ID = %d\n", __FUNCTION__, rl_idx);
281  regdQList[rl_idx]->setBarrierBit(true);
282  return BLOCKED_BBIT;
283  }
284  if (pkt_type == HSA_PACKET_TYPE_VENDOR_SPECIFIC) {
285  DPRINTF(HSAPacketProcessor, "%s: submitting vendor specific pkt" \
286  " active list ID = %d\n", __FUNCTION__, rl_idx);
287  // Submit packet to HSA device (dispatcher)
288  gpu_device->submitVendorPkt((void *)disp_pkt, rl_idx, host_pkt_addr);
289  is_submitted = UNBLOCKED;
290  } else if (pkt_type == HSA_PACKET_TYPE_KERNEL_DISPATCH) {
291  DPRINTF(HSAPacketProcessor, "%s: submitting kernel dispatch pkt" \
292  " active list ID = %d\n", __FUNCTION__, rl_idx);
293  // Submit packet to HSA device (dispatcher)
294  gpu_device->submitDispatchPkt((void *)disp_pkt, rl_idx, host_pkt_addr);
295  is_submitted = UNBLOCKED;
296  /*
297  If this packet is using the "barrier bit" to enforce ordering with
298  subsequent kernels, set the bit for this queue now, after
299  dispatching.
300  */
301  if (IS_BARRIER(disp_pkt)) {
302  DPRINTF(HSAPacketProcessor, "%s: setting barrier bit for active" \
303  " list ID = %d\n", __FUNCTION__, rl_idx);
304  regdQList[rl_idx]->setBarrierBit(true);
305  }
306  } else if (pkt_type == HSA_PACKET_TYPE_BARRIER_AND) {
307  DPRINTF(HSAPacketProcessor, "%s: Processing barrier packet" \
308  " active list ID = %d\n", __FUNCTION__, rl_idx);
309  auto bar_and_pkt = (_hsa_barrier_and_packet_t *)pkt;
310  bool isReady = true;
311  // Loop thorugh all the completion signals to see if this barrier
312  // packet is ready.
313  for (int i = 0; i < NumSignalsPerBarrier; i++) {
314  // dep_signal = zero imply no signal connected
315  if (bar_and_pkt->dep_signal[i]) {
316  // The signal value is aligned 8 bytes from
317  // the actual handle in the runtime
318  uint64_t signal_addr =
319  (uint64_t) (((uint64_t *) bar_and_pkt->dep_signal[i]) + 1);
320  hsa_signal_value_t *signal_val =
321  &(dep_sgnl_rd_st->values[i]);
322  DPRINTF(HSAPacketProcessor, "%s: Barrier pkt dep sgnl[%d]" \
323  " , sig addr %x, value %d active list ID = %d\n",
324  __FUNCTION__, i, signal_addr,
325  *signal_val, rl_idx);
326  // The if condition will be executed everytime except the
327  // very first time this barrier packet is encounteresd.
328  if (dep_sgnl_rd_st->allRead) {
329  if (*signal_val != 0) {
330  // This signal is not yet ready, read it again
331  isReady = false;
332 
333  auto cb = new DmaVirtCallback<int64_t>(
334  [ = ] (const uint32_t &dma_data)
335  { dep_sgnl_rd_st->handleReadDMA(); }, 0);
336  dmaReadVirt(signal_addr, sizeof(hsa_signal_value_t),
337  cb, signal_val);
338  dep_sgnl_rd_st->pendingReads++;
339  DPRINTF(HSAPacketProcessor, "%s: Pending reads %d," \
340  " active list %d\n", __FUNCTION__,
341  dep_sgnl_rd_st->pendingReads, rl_idx);
342  }
343  } else {
344  // This signal is not yet ready, read it again
345  isReady = false;
346  auto cb = new DmaVirtCallback<int64_t>(
347  [ = ] (const uint32_t &dma_data)
348  { dep_sgnl_rd_st->handleReadDMA(); }, 0);
349  dmaReadVirt(signal_addr, sizeof(hsa_signal_value_t),
350  cb, signal_val);
351  dep_sgnl_rd_st->pendingReads++;
352  DPRINTF(HSAPacketProcessor, "%s: Pending reads %d," \
353  " active list %d\n", __FUNCTION__,
354  dep_sgnl_rd_st->pendingReads, rl_idx);
355  }
356  }
357  }
358  if (isReady) {
359  assert(dep_sgnl_rd_st->pendingReads == 0);
360  DPRINTF(HSAPacketProcessor, "%s: Barrier packet completed" \
361  " active list ID = %d\n", __FUNCTION__, rl_idx);
362  // TODO: Completion signal of barrier packet to be
363  // atomically decremented here
364  finishPkt((void*)bar_and_pkt, rl_idx);
365  is_submitted = UNBLOCKED;
366  // Reset signal values
367  dep_sgnl_rd_st->resetSigVals();
368  // The completion signal is connected
369  if (bar_and_pkt->completion_signal != 0) {
370  // HACK: The semantics of the HSA signal is to
371  // decrement the current signal value
372  // I'm going to cheat here and read out
373  // the value from main memory using functional
374  // access, and then just DMA the decremented value.
375  uint64_t signal_value = gpu_device->functionalReadHsaSignal(\
376  bar_and_pkt->completion_signal);
377 
378  DPRINTF(HSAPacketProcessor, "Triggering barrier packet" \
379  " completion signal! Addr: %x\n",
380  bar_and_pkt->completion_signal);
381 
382  gpu_device->updateHsaSignal(bar_and_pkt->completion_signal,
383  signal_value - 1);
384  }
385  }
386  if (dep_sgnl_rd_st->pendingReads > 0) {
387  // Atleast one DepSignalsReadDmaEvent is scheduled this cycle
388  dep_sgnl_rd_st->allRead = false;
389  dep_sgnl_rd_st->discardRead = false;
390  }
391  } else if (pkt_type == HSA_PACKET_TYPE_BARRIER_OR) {
392  fatal("Unsupported packet type HSA_PACKET_TYPE_BARRIER_OR");
393  } else if (pkt_type == HSA_PACKET_TYPE_INVALID) {
394  fatal("Unsupported packet type HSA_PACKET_TYPE_INVALID");
395  } else if (pkt_type == HSA_PACKET_TYPE_AGENT_DISPATCH) {
396  DPRINTF(HSAPacketProcessor, "%s: submitting agent dispatch pkt" \
397  " active list ID = %d\n", __FUNCTION__, rl_idx);
398  // Submit packet to HSA device (dispatcher)
400  (void *)disp_pkt, rl_idx, host_pkt_addr);
401  is_submitted = UNBLOCKED;
402  sendAgentDispatchCompletionSignal((void *)disp_pkt,0);
403  } else {
404  fatal("Unsupported packet type %d\n", pkt_type);
405  }
406  return is_submitted;
407 }
408 
409 // Wakes up every fixed time interval (pktProcessDelay) and processes a single
410 // packet from the queue that scheduled this wakeup. If there are more
411 // packets in that queue, the next wakeup is scheduled.
412 void
414 {
415  AQLRingBuffer *aqlRingBuffer = hsaPP->regdQList[rqIdx]->qCntxt.aqlBuf;
417  "%s: Qwakeup , rdIdx %d, wrIdx %d," \
418  " dispIdx %d, active list ID = %d\n",
419  __FUNCTION__, aqlRingBuffer->rdIdx(),
420  aqlRingBuffer->wrIdx(), aqlRingBuffer->dispIdx(), rqIdx);
421  // If barrier bit is set, then this wakeup is a dummy wakeup
422  // just to model the processing time. Do nothing.
423  if (hsaPP->regdQList[rqIdx]->getBarrierBit()) {
425  "Dummy wakeup with barrier bit for rdIdx %d\n", rqIdx);
426  return;
427  }
428  // In the future, we may support batch processing of packets.
429  // Then, we can just remove the break statements and the code
430  // will support batch processing. That is why we are using a
431  // "while loop" here instead on an "if" condition.
432  while (hsaPP->regdQList[rqIdx]->dispPending()) {
433  void *pkt = aqlRingBuffer->ptr(aqlRingBuffer->dispIdx());
434  DPRINTF(HSAPacketProcessor, "%s: Attempting dispatch @ dispIdx[%d]\n",
435  __FUNCTION__, aqlRingBuffer->dispIdx());
436  Addr host_addr = aqlRingBuffer->hostDispAddr();
437  Q_STATE q_state = hsaPP->processPkt(pkt, rqIdx, host_addr);
438  if (q_state == UNBLOCKED) {
439  aqlRingBuffer->incDispIdx(1);
440  DPRINTF(HSAPacketProcessor, "%s: Increment dispIdx[%d]\n",
441  __FUNCTION__, aqlRingBuffer->dispIdx());
442  if (hsaPP->regdQList[rqIdx]->dispPending()) {
444  }
445  break;
446  } else if (q_state == BLOCKED_BPKT) {
447  // This queue is blocked by barrier packet,
448  // schedule a processing event
450  break;
451  } else if (q_state == BLOCKED_BBIT) {
452  // This queue is blocked by barrier bit, and processing event
453  // should be scheduled from finishPkt(). However, to elapse
454  // "pktProcessDelay" processing time, let us schedule a dummy
455  // wakeup once which will just wakeup and will do nothing.
457  break;
458  } else {
459  panic("Unknown queue state\n");
460  }
461  }
462 }
463 
464 void
466 {
467  assert(pendingReads > 0);
468  pendingReads--;
469  if (pendingReads == 0) {
470  allRead = true;
471  if (discardRead) {
472  resetSigVals();
473  }
474  }
475 }
476 
477 void
479 {
480  HSAQueueDescriptor* qDesc = regdQList[rl_idx]->qCntxt.qDesc;
481  AQLRingBuffer *aqlRingBuffer = regdQList[rl_idx]->qCntxt.aqlBuf;
482 
484  "%s: read-pointer offset[0x%x], write-pointer offset[0x%x]"
485  " doorbell(%d)[0x%x] \n",
486  __FUNCTION__, qDesc->readIndex,
487  qDesc->writeIndex, pid, qDesc->doorbellPointer);
488 
489  if (qDesc->dmaInProgress) {
490  // we'll try again when this dma transfer completes in updateReadIndex
491  return;
492  }
493  uint32_t num_umq = qDesc->spaceUsed();
494  if (num_umq == 0)
495  return; // nothing to be gotten
496  uint32_t umq_nxt = qDesc->readIndex;
497  // Total AQL buffer size
498  uint32_t ttl_aql_buf = aqlRingBuffer->numObjs();
499  // Available AQL buffer size. If the available buffer is less than
500  // demanded, number of available buffer is returned
501  uint32_t got_aql_buf = aqlRingBuffer->allocEntry(num_umq);
502  qDesc->readIndex += got_aql_buf;
503  uint32_t dma_start_ix = (aqlRingBuffer->wrIdx() - got_aql_buf) %
504  ttl_aql_buf;
505  dma_series_ctx *series_ctx = NULL;
506 
507  DPRINTF(HSAPacketProcessor, "%s: umq_nxt = %d, ttl_aql_buf = %d, "
508  "dma_start_ix = %d, num_umq = %d\n", __FUNCTION__, umq_nxt,
509  ttl_aql_buf, dma_start_ix, num_umq);
510 
511  if (got_aql_buf == 0) {
512  // we'll try again when some dma bufs are freed in freeEntry
513  qDesc->stalledOnDmaBufAvailability = true;
514  return;
515  } else {
516  qDesc->stalledOnDmaBufAvailability = false;
517  }
518 
519  uint32_t dma_b4_wrap = ttl_aql_buf - dma_start_ix;
520  while (got_aql_buf != 0 && num_umq != 0) {
521  uint32_t umq_b4_wrap = qDesc->numObjs() -
522  (umq_nxt % qDesc->objSize());
523  uint32_t num_2_xfer
524  = std::min({umq_b4_wrap, dma_b4_wrap, num_umq, got_aql_buf});
525  if (!series_ctx) {
526  qDesc->dmaInProgress = true;
527  series_ctx = new dma_series_ctx(got_aql_buf, got_aql_buf,
528  dma_start_ix, rl_idx);
529  }
530 
531  void *aql_buf = aqlRingBuffer->ptr(dma_start_ix);
532  auto cb = new DmaVirtCallback<uint64_t>(
533  [ = ] (const uint32_t &dma_data)
534  { this->cmdQueueCmdDma(this, pid, true, dma_start_ix,
535  num_2_xfer, series_ctx, aql_buf); }, 0);
536  dmaReadVirt(qDesc->ptr(umq_nxt), num_2_xfer * qDesc->objSize(),
537  cb, aql_buf);
538 
539  aqlRingBuffer->saveHostDispAddr(qDesc->ptr(umq_nxt), num_2_xfer,
540  dma_start_ix);
541 
543  "%s: aql_buf = %p, umq_nxt = %d, dma_ix = %d, num2xfer = %d\n",
544  __FUNCTION__, aql_buf, umq_nxt, dma_start_ix, num_2_xfer);
545 
546  num_umq -= num_2_xfer;
547  got_aql_buf -= num_2_xfer;
548  dma_start_ix = (dma_start_ix + num_2_xfer) % ttl_aql_buf;
549  umq_nxt = (umq_nxt + num_2_xfer) % qDesc->numObjs();
550  if (got_aql_buf == 0 && num_umq != 0) {
551  // There are more packets in the queue but
552  // not enough DMA buffers. Set the stalledOnDmaBufAvailability,
553  // we will try again in freeEntry
554  qDesc->stalledOnDmaBufAvailability = true;
555  }
556  }
557 }
558 
559 void
561 {
562  [[maybe_unused]] HSAQueueDescriptor* qDesc =
563  regdQList[rl_idx]->qCntxt.qDesc;
565  "%s: pid[%d], basePointer[0x%lx], dBPointer[0x%lx], "
566  "writeIndex[0x%x], readIndex[0x%x], size(bytes)[0x%x]\n",
567  __FUNCTION__, pid, qDesc->basePointer,
568  qDesc->doorbellPointer, qDesc->writeIndex,
569  qDesc->readIndex, qDesc->numElts);
570 }
571 
573  const std::string name)
574  : _name(name), _wrIdx(0), _rdIdx(0), _dispIdx(0)
575 {
576  _aqlBuf.resize(size);
577  _aqlComplete.resize(size);
578  _hostDispAddresses.resize(size);
579  // Mark all packets as invalid and incomplete
580  for (auto& it : _aqlBuf)
581  it.header = HSA_PACKET_TYPE_INVALID;
582  std::fill(_aqlComplete.begin(), _aqlComplete.end(), false);
583 }
584 
585 bool
587 {
588  _aqlComplete[(hsa_kernel_dispatch_packet_t *) pkt - _aqlBuf.data()] = true;
589  DPRINTF(HSAPacketProcessor, "%s: pkt_ix = %d; "\
590  " # free entries = %d, wrIdx = %d, rdIdx = %d\n", __FUNCTION__,
591  (hsa_kernel_dispatch_packet_t *) pkt - _aqlBuf.data(),
592  nFree(), wrIdx(), rdIdx());
593  // Packets can complete out-of-order. This code "retires" packets in-order
594  // by updating the read pointer in the MQD when a contiguous chunk of
595  // packets have finished.
596  uint32_t old_rdIdx = rdIdx();
597  while (_aqlComplete[rdIdx() % numObjs()]) {
598  _aqlComplete[rdIdx() % numObjs()] = false;
600  incRdIdx(1);
601  }
602  return (old_rdIdx != rdIdx());
603 }
604 
605 void
607 {
608  this->gpu_device = dev;
609 }
610 
611 int
612 AQLRingBuffer::allocEntry(uint32_t nBufReq)
613 {
614  DPRINTF(HSAPacketProcessor, "%s: nReq = %d\n", __FUNCTION__, nBufReq);
615  if (nFree() == 0) {
616  DPRINTF(HSAPacketProcessor, "%s: return = %d\n", __FUNCTION__, 0);
617  return 0;
618  }
619 
620  if (nBufReq > nFree())
621  nBufReq = nFree();
622 
623  DPRINTF(HSAPacketProcessor, "%s: ix1stFree = %d\n", __FUNCTION__, wrIdx());
624  incWrIdx(nBufReq);
625  DPRINTF(HSAPacketProcessor, "%s: return = %d, wrIdx = %d\n",
626  __FUNCTION__, nBufReq, wrIdx());
627  return nBufReq;
628 }
629 
630 void
631 HSAPacketProcessor::finishPkt(void *pvPkt, uint32_t rl_idx)
632 {
633  HSAQueueDescriptor* qDesc = regdQList[rl_idx]->qCntxt.qDesc;
634 
635  // if barrier bit was set and this is the last
636  // outstanding packet from that queue,
637  // unset it here
638  if (regdQList[rl_idx]->getBarrierBit() &&
639  regdQList[rl_idx]->isLastOutstandingPkt()) {
641  "Unset barrier bit for active list ID %d\n", rl_idx);
642  regdQList[rl_idx]->setBarrierBit(false);
643  // if pending kernels in the queue after this kernel, reschedule
644  if (regdQList[rl_idx]->dispPending()) {
646  "Rescheduling active list ID %d after unsetting barrier "
647  "bit\n", rl_idx);
648  schedAQLProcessing(rl_idx);
649  }
650  }
651 
652  // If set, then blocked schedule, so need to reschedule
653  if (regdQList[rl_idx]->qCntxt.aqlBuf->freeEntry(pvPkt))
654  updateReadIndex(0, rl_idx);
656  "%s: rd-ptr offset [0x%x], wr-ptr offset [0x%x], space used = %d," \
657  " q size = %d, stalled = %s, empty = %s, active list ID = %d\n",
658  __FUNCTION__, qDesc->readIndex, qDesc->writeIndex,
659  qDesc->spaceUsed(), qDesc->numElts,
660  qDesc->stalledOnDmaBufAvailability? "true" : "false",
661  qDesc->isEmpty()? "true" : "false", rl_idx);
662  // DMA buffer is freed, check the queue to see if there are DMA
663  // accesses blocked becasue of non-availability of DMA buffer
664  if (qDesc->stalledOnDmaBufAvailability) {
665  assert(!qDesc->isEmpty());
666  getCommandsFromHost(0, rl_idx); // TODO:assign correct pid
667  // when implementing
668  // multi-process support
669  }
670 }
671 
672 void
674  void *pkt, hsa_signal_value_t signal)
675 {
676  auto agent_pkt = (_hsa_agent_dispatch_packet_t *)pkt;
677  uint64_t signal_addr =
678  (uint64_t) (((uint64_t *)agent_pkt->completion_signal) + 1);
679  DPRINTF(HSAPacketProcessor, "Triggering Agent Dispatch packet" \
680  " completion signal: %x!\n", signal_addr);
690  VPtr<uint64_t> prev_signal(signal_addr, sys->threads[0]);
691 
692  DPRINTF(HSAPacketProcessor,"HSADriver: Sending signal to %lu\n",
693  (uint64_t)sys->threads[0]->cpuId());
694 
695 
696  hsa_signal_value_t *new_signal = new hsa_signal_value_t;
697  *new_signal = (hsa_signal_value_t) *prev_signal - 1;
698 
699  dmaWriteVirt(signal_addr, sizeof(hsa_signal_value_t), nullptr, new_signal, 0);
700 }
701 
702 void
704 {
705  uint64_t signal_addr = (uint64_t) (((uint64_t *)signal) + 1);
706  DPRINTF(HSAPacketProcessor, "Triggering completion signal: %x!\n",
707  signal_addr);
717  VPtr<uint64_t> prev_signal(signal_addr, sys->threads[0]);
718 
719  hsa_signal_value_t *new_signal = new hsa_signal_value_t;
720  *new_signal = (hsa_signal_value_t) *prev_signal - 1;
721 
722  dmaWriteVirt(signal_addr, sizeof(hsa_signal_value_t), nullptr, new_signal, 0);
723 }
724 
725 } // namespace gem5
gem5::_hsa_agent_dispatch_packet_t
Definition: hsa_packet.hh:72
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
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Wraps a std::function object in a DmaCallback.
Definition: dma_virt_device.hh:51
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Initiate a DMA read from virtual address host_addr.
Definition: dma_virt_device.cc:38
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Definition: addr_range.hh:815
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Definition: hsa.h:1322
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Definition: packet.hh:773
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the kernel may try to read from the dispatch packet, so we need to keep the host address that corresp...
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Definition: hsa_packet_processor.hh:53
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Definition: packet.hh:1043
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Definition: hsa_packet_processor.hh:61
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Definition: hsa_packet_processor.cc:99
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Definition: hsa_packet_processor.hh:380
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submitDispatchPkt() is the entry point into the CP from the HSAPP and is only meant to be used with A...
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Definition: hsa_packet_processor.hh:269
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Definition: gpu_command_processor.cc:186
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Definition: hsa_packet_processor.hh:99
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Definition: hsa_packet_processor.hh:254
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Definition: hsa_packet_processor.cc:156
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HSA_PACKET_TYPE_KERNEL_DISPATCH
@ HSA_PACKET_TYPE_KERNEL_DISPATCH
Packet used by agents for dispatching jobs to kernel agents.
Definition: hsa.h:2761
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Definition: gpu_command_processor.hh:69
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Definition: named.hh:47
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Definition: hsa_packet_processor.hh:249
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Definition: trace.hh:186
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A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
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Definition: base.cc:60
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Definition: hsa_packet_processor.hh:157
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@ BLOCKED_BBIT
Definition: hsa_packet_processor.hh:64
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Definition: pra_constants.hh:326
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Definition: hsa_packet_processor.hh:255
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submitAgentDispatchPkt() is for accepting agent dispatch packets.
Definition: gpu_command_processor.cc:268
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Definition: hsa_packet_processor.hh:85
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Definition: hsa_packet_processor.hh:76
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Definition: proxy_ptr.hh:238
PKT_TYPE
#define PKT_TYPE(PKT)
Definition: hsa_packet_processor.cc:60
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DmaDeviceParams Params
Definition: dma_device.hh:209
gem5::BLOCKED_BPKT
@ BLOCKED_BPKT
Definition: hsa_packet_processor.hh:67
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void sendCompletionSignal(hsa_signal_value_t signal)
Definition: hsa_packet_processor.cc:703
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Definition: hw_scheduler.cc:336
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gem5::_hsa_dispatch_packet_t
Definition: hsa_packet.hh:53
HSA_PACKET_TYPE_BARRIER_OR
@ HSA_PACKET_TYPE_BARRIER_OR
Packet used by agents to delay processing of subsequent packets, and to express complex dependencies ...
Definition: hsa.h:2778
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void displayQueueDescriptor(int pid, uint32_t rl_idx)
Definition: hsa_packet_processor.cc:560
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Definition: hsa_packet_processor.hh:80
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Initiate a DMA write from virtual address host_addr.
Definition: dma_virt_device.cc:45
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Definition: hsa_packet_processor.cc:186
HSA_PACKET_TYPE_VENDOR_SPECIFIC
@ HSA_PACKET_TYPE_VENDOR_SPECIFIC
Vendor-specific packet.
Definition: hsa.h:2750
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uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
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Definition: hw_scheduler.hh:50
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Definition: hsa_packet_processor.hh:233
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Definition: gpu_compute_driver.hh:86
HSA_PACKET_TYPE_INVALID
@ HSA_PACKET_TYPE_INVALID
The packet has been processed in the past, but has not been reassigned to the packet processor.
Definition: hsa.h:2756
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hsa_packet_type_t
Packet type.
Definition: hsa.h:2745
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Definition: hw_scheduler.cc:85
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void handleReadDMA()
Definition: hsa_packet_processor.cc:465
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Definition: hsa_packet_processor.hh:260
HSA_PACKET_TYPE_AGENT_DISPATCH
@ HSA_PACKET_TYPE_AGENT_DISPATCH
Packet used by agents for dispatching jobs to agents.
Definition: hsa.h:2772
gem5::HSAPacketProcessor::sendAgentDispatchCompletionSignal
void sendAgentDispatchCompletionSignal(void *pkt, hsa_signal_value_t signal)
Definition: hsa_packet_processor.cc:673
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Definition: hsa_packet_processor.hh:228
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std::vector< Addr > _hostDispAddresses
Definition: hsa_packet_processor.hh:159
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std::vector< class RQLEntry * > regdQList
Definition: hsa_packet_processor.hh:316
IS_BARRIER
#define IS_BARRIER(PKT)
Definition: hsa_packet_processor.cc:65
gem5::HSAPacketProcessor::pktProcessDelay
const Tick pktProcessDelay
Definition: hsa_packet_processor.hh:344
gem5::HSAPacketProcessor::setDevice
void setDevice(GPUCommandProcessor *dev)
Definition: hsa_packet_processor.cc:606
gem5::AQLRingBuffer::incRdIdx
void incRdIdx(uint64_t value)
Definition: hsa_packet_processor.hh:231
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Threads threads
Definition: system.hh:314
gem5::HSAQueueDescriptor::numElts
uint32_t numElts
Definition: hsa_packet_processor.hh:83
gem5::AQLRingBuffer
Internal ring buffer which is used to prefetch/store copies of the in-memory HSA ring buffer.
Definition: hsa_packet_processor.hh:154
gem5::GPUCommandProcessor::submitVendorPkt
void submitVendorPkt(void *raw_pkt, uint32_t queue_id, Addr host_pkt_addr)
submitVendorPkt() is for accepting vendor-specific packets from the HSAPP.
Definition: gpu_command_processor.cc:254
gem5::GPUCommandProcessor::functionalReadHsaSignal
uint64_t functionalReadHsaSignal(Addr signal_handle)
Definition: gpu_command_processor.cc:177
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bool allRead
Definition: hsa_packet_processor.hh:270
logging.hh
gem5::Packet::getLE
T getLE() const
Get the data in the packet byte swapped from little endian to host endian.
Definition: packet_access.hh:78
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uint64_t * rdIdxPtr()
Definition: hsa_packet_processor.hh:230
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uint32_t objSize()
Definition: hsa_packet_processor.hh:100
gem5::HSAPacketProcessor::getAddrRanges
virtual AddrRangeList getAddrRanges() const override
Every PIO device is obliged to provide an implementation that returns the address ranges the device r...
Definition: hsa_packet_processor.cc:114
HSA_PACKET_TYPE_BARRIER_AND
@ HSA_PACKET_TYPE_BARRIER_AND
Packet used by agents to delay processing of subsequent packets, and to express complex dependencies ...
Definition: hsa.h:2767
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~HSAPacketProcessor()
Definition: hsa_packet_processor.cc:85
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std::vector< hsa_signal_value_t > values
Definition: hsa_packet_processor.hh:275
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Definition: hsa_packet_processor.hh:298
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Definition: hw_scheduler.cc:319
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uint32_t nFree() const
Definition: hsa_packet_processor.hh:223
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std::vector< bool > _aqlComplete
Definition: hsa_packet_processor.hh:160
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Definition: dma_virt_device.hh:41
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vaddr
Definition: pra_constants.hh:278
std::list< AddrRange >
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:781
gem5::HSAPacketProcessor::updateReadDispIdDma
void updateReadDispIdDma()
this event is used to update the read_disp_id field (the read pointer) of the MQD,...
Definition: hsa_packet_processor.cc:180
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gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
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Definition: hsa_packet.hh:83
gem5::HSAPacketProcessor::QueueProcessEvent::process
virtual void process()
Definition: hsa_packet_processor.cc:413
gem5::UNBLOCKED
@ UNBLOCKED
Definition: hsa_packet_processor.hh:63
gem5::HSAPacketProcessor::write
virtual Tick write(Packet *) override
Definition: hsa_packet_processor.cc:126
gem5::Packet::getSize
unsigned getSize() const
Definition: packet.hh:791
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const std::string _name
Definition: named.hh:41
gem5::HSAPacketProcessor::dma_series_ctx::rl_idx
uint32_t rl_idx
Definition: hsa_packet_processor.hh:382
gem5::TranslationGenPtr
std::unique_ptr< TranslationGen > TranslationGenPtr
Definition: translation_gen.hh:128
gem5::HSAQueueDescriptor::writeIndex
uint64_t writeIndex
Definition: hsa_packet_processor.hh:81
gem5::Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:465
gem5::AQLRingBuffer::dispIdx
uint64_t dispIdx() const
Definition: hsa_packet_processor.hh:227
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::GPUCommandProcessor::driver
GPUComputeDriver * driver()
Definition: gpu_command_processor.cc:231
gem5::HSAPacketProcessor::RQLEntry::aqlProcessEvent
QueueProcessEvent aqlProcessEvent
Definition: hsa_packet_processor.hh:307

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