gem5  v21.2.1.1
dyn_inst.cc
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40 
41 #include "cpu/o3/dyn_inst.hh"
42 
43 #include <algorithm>
44 
45 #include "base/intmath.hh"
46 #include "debug/DynInst.hh"
47 #include "debug/IQ.hh"
48 #include "debug/O3PipeView.hh"
49 
50 namespace gem5
51 {
52 
53 namespace o3
54 {
55 
56 DynInst::DynInst(const Arrays &arrays, const StaticInstPtr &static_inst,
57  const StaticInstPtr &_macroop, InstSeqNum seq_num, CPU *_cpu)
58  : seqNum(seq_num), staticInst(static_inst), cpu(_cpu),
59  _numSrcs(arrays.numSrcs), _numDests(arrays.numDests),
60  _flatDestIdx(arrays.flatDestIdx), _destIdx(arrays.destIdx),
61  _prevDestIdx(arrays.prevDestIdx), _srcIdx(arrays.srcIdx),
62  _readySrcIdx(arrays.readySrcIdx), macroop(_macroop)
63 {
64  std::fill(_readySrcIdx, _readySrcIdx + (numSrcs() + 7) / 8, 0);
65 
66  status.reset();
67 
68  instFlags.reset();
69  instFlags[RecordResult] = true;
70  instFlags[Predicate] = true;
71  instFlags[MemAccPredicate] = true;
72 
73 #ifndef NDEBUG
74  ++cpu->instcount;
75 
76  if (cpu->instcount > 1500) {
77 #ifdef DEBUG
78  cpu->dumpInsts();
79  dumpSNList();
80 #endif
81  assert(cpu->instcount <= 1500);
82  }
83 
85  "DynInst: [sn:%lli] Instruction created. Instcount for %s = %i\n",
86  seqNum, cpu->name(), cpu->instcount);
87 #endif
88 
89 #ifdef DEBUG
90  cpu->snList.insert(seqNum);
91 #endif
92 
93 }
94 
95 DynInst::DynInst(const Arrays &arrays, const StaticInstPtr &static_inst,
96  const StaticInstPtr &_macroop, const PCStateBase &_pc,
97  const PCStateBase &pred_pc, InstSeqNum seq_num, CPU *_cpu)
98  : DynInst(arrays, static_inst, _macroop, seq_num, _cpu)
99 {
100  set(pc, _pc);
101  set(predPC, pred_pc);
102 }
103 
104 DynInst::DynInst(const Arrays &arrays, const StaticInstPtr &_staticInst,
105  const StaticInstPtr &_macroop)
106  : DynInst(arrays, _staticInst, _macroop, 0, nullptr)
107 {}
108 
109 /*
110  * This custom "new" operator uses the default "new" operator to allocate space
111  * for a DynInst, but also pads out the number of bytes to make room for some
112  * extra structures the DynInst needs. We save time and improve performance by
113  * only going to the heap once to get space for all these structures.
114  *
115  * When a DynInst is allocated with new, the compiler will call this "new"
116  * operator with "count" set to the number of bytes it needs to store the
117  * DynInst. We ultimately call into the default new operator to get those
118  * bytes, but before we do, we pad out "count" so that there will be extra
119  * space for some structures the DynInst needs. We take into account both the
120  * absolute size of these structures, and also what alignment they need.
121  *
122  * Once we've gotten a buffer large enough to hold the DynInst itself and these
123  * extra structures, we construct the extra bits using placement new. This
124  * constructs the structures in place in the space we created for them.
125  *
126  * Next, we return the buffer as the result of our operator. The compiler takes
127  * that buffer and constructs the DynInst in the beginning of it using the
128  * DynInst constructor.
129  *
130  * To avoid having to calculate where these extra structures are twice, once
131  * when making room for them and initializing them, and then once again in the
132  * DynInst constructor, we also pass in a structure called "arrays" which holds
133  * pointers to them. The fields of "arrays" are initialized in this operator,
134  * and are then consumed in the DynInst constructor.
135  */
136 void *
137 DynInst::operator new(size_t count, Arrays &arrays)
138 {
139  // Convenience variables for brevity.
140  const auto num_dests = arrays.numDests;
141  const auto num_srcs = arrays.numSrcs;
142 
143  // Figure out where everything will go.
144  uintptr_t inst = 0;
145  size_t inst_size = count;
146 
147  uintptr_t flat_dest_idx = roundUp(inst + inst_size, alignof(RegId));
148  size_t flat_dest_idx_size = sizeof(*arrays.flatDestIdx) * num_dests;
149 
150  uintptr_t dest_idx =
151  roundUp(flat_dest_idx + flat_dest_idx_size, alignof(PhysRegIdPtr));
152  size_t dest_idx_size = sizeof(*arrays.destIdx) * num_dests;
153 
154  uintptr_t prev_dest_idx =
155  roundUp(dest_idx + dest_idx_size, alignof(PhysRegIdPtr));
156  size_t prev_dest_idx_size = sizeof(*arrays.prevDestIdx) * num_dests;
157 
158  uintptr_t src_idx =
159  roundUp(prev_dest_idx + prev_dest_idx_size, alignof(PhysRegIdPtr));
160  size_t src_idx_size = sizeof(*arrays.srcIdx) * num_srcs;
161 
162  uintptr_t ready_src_idx =
163  roundUp(src_idx + src_idx_size, alignof(uint8_t));
164  size_t ready_src_idx_size =
165  sizeof(*arrays.readySrcIdx) * ((num_srcs + 7) / 8);
166 
167  // Figure out how much space we need in total.
168  size_t total_size = ready_src_idx + ready_src_idx_size;
169 
170  // Actually allocate it.
171  uint8_t *buf = (uint8_t *)::operator new(total_size);
172 
173  // Fill in "arrays" with pointers to all the arrays.
174  arrays.flatDestIdx = (RegId *)(buf + flat_dest_idx);
175  arrays.destIdx = (PhysRegIdPtr *)(buf + dest_idx);
176  arrays.prevDestIdx = (PhysRegIdPtr *)(buf + prev_dest_idx);
177  arrays.srcIdx = (PhysRegIdPtr *)(buf + src_idx);
178  arrays.readySrcIdx = (uint8_t *)(buf + ready_src_idx);
179 
180  // Initialize all the extra components.
181  new (arrays.flatDestIdx) RegId[num_dests];
182  new (arrays.destIdx) PhysRegIdPtr[num_dests];
183  new (arrays.prevDestIdx) PhysRegIdPtr[num_dests];
184  new (arrays.srcIdx) PhysRegIdPtr[num_srcs];
185  new (arrays.readySrcIdx) uint8_t[num_srcs];
186 
187  return buf;
188 }
189 
191 {
192  /*
193  * The buffer this DynInst occupies also holds some of the structures it
194  * points to. We need to call their destructors manually to make sure that
195  * they're cleaned up appropriately, but we don't need to free their memory
196  * explicitly since that's part of the DynInst's buffer and is already
197  * going to be freed as part of deleting the DynInst.
198  */
199  for (int i = 0; i < _numDests; i++) {
200  _flatDestIdx[i].~RegId();
201  _destIdx[i].~PhysRegIdPtr();
202  _prevDestIdx[i].~PhysRegIdPtr();
203  }
204 
205  for (int i = 0; i < _numSrcs; i++)
206  _srcIdx[i].~PhysRegIdPtr();
207 
208  for (int i = 0; i < ((_numSrcs + 7) / 8); i++)
209  _readySrcIdx[i].~uint8_t();
210 
211 #if TRACING_ON
212  if (debug::O3PipeView) {
213  Tick fetch = fetchTick;
214  // fetchTick can be -1 if the instruction fetched outside the trace
215  // window.
216  if (fetch != -1) {
217  Tick val;
218  // Print info needed by the pipeline activity viewer.
219  DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n",
220  fetch,
221  pcState().instAddr(),
222  pcState().microPC(),
223  seqNum,
224  staticInst->disassemble(pcState().instAddr()));
225 
226  val = (decodeTick == -1) ? 0 : fetch + decodeTick;
227  DPRINTFR(O3PipeView, "O3PipeView:decode:%llu\n", val);
228  val = (renameTick == -1) ? 0 : fetch + renameTick;
229  DPRINTFR(O3PipeView, "O3PipeView:rename:%llu\n", val);
230  val = (dispatchTick == -1) ? 0 : fetch + dispatchTick;
231  DPRINTFR(O3PipeView, "O3PipeView:dispatch:%llu\n", val);
232  val = (issueTick == -1) ? 0 : fetch + issueTick;
233  DPRINTFR(O3PipeView, "O3PipeView:issue:%llu\n", val);
234  val = (completeTick == -1) ? 0 : fetch + completeTick;
235  DPRINTFR(O3PipeView, "O3PipeView:complete:%llu\n", val);
236  val = (commitTick == -1) ? 0 : fetch + commitTick;
237 
238  Tick valS = (storeTick == -1) ? 0 : fetch + storeTick;
239  DPRINTFR(O3PipeView, "O3PipeView:retire:%llu:store:%llu\n",
240  val, valS);
241  }
242  }
243 #endif
244 
245  delete [] memData;
246  delete traceData;
247  fault = NoFault;
248 
249 #ifndef NDEBUG
250  --cpu->instcount;
251 
253  "DynInst: [sn:%lli] Instruction destroyed. Instcount for %s = %i\n",
254  seqNum, cpu->name(), cpu->instcount);
255 #endif
256 #ifdef DEBUG
257  cpu->snList.erase(seqNum);
258 #endif
259 };
260 
261 
262 #ifdef DEBUG
263 void
264 DynInst::dumpSNList()
265 {
266  std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
267 
268  int count = 0;
269  while (sn_it != cpu->snList.end()) {
270  cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
271  count++;
272  sn_it++;
273  }
274 }
275 #endif
276 
277 void
279 {
280  cprintf("T%d : %#08d `", threadNumber, pc->instAddr());
281  std::cout << staticInst->disassemble(pc->instAddr());
282  cprintf("'\n");
283 }
284 
285 void
286 DynInst::dump(std::string &outstring)
287 {
288  std::ostringstream s;
289  s << "T" << threadNumber << " : 0x" << pc->instAddr() << " "
290  << staticInst->disassemble(pc->instAddr());
291 
292  outstring = s.str();
293 }
294 
295 void
297 {
298  DPRINTF(IQ, "[sn:%lli] has %d ready out of %d sources. RTI %d)\n",
300  if (++readyRegs == numSrcRegs()) {
301  setCanIssue();
302  }
303 }
304 
305 void
307 {
308  readySrcIdx(src_idx, true);
309  markSrcRegReady();
310 }
311 
312 
313 void
315 {
316  status.set(Squashed);
317 
319  return;
320 
321  // This inst has been renamed already so it may go through rename
322  // again (e.g. if the squash is due to memory access order violation).
323  // Reset the write counters for all pinned destination register to ensure
324  // that they are in a consistent state for a possible re-rename. This also
325  // ensures that dest regs will be pinned to the same phys register if
326  // re-rename happens.
327  for (int idx = 0; idx < numDestRegs(); idx++) {
328  PhysRegIdPtr phys_dest_reg = renamedDestIdx(idx);
329  if (phys_dest_reg->isPinned()) {
330  phys_dest_reg->incrNumPinnedWrites();
331  if (isPinnedRegsWritten())
332  phys_dest_reg->incrNumPinnedWritesToComplete();
333  }
334  }
336 }
337 
338 Fault
340 {
341  // @todo: Pretty convoluted way to avoid squashing from happening
342  // when using the TC during an instruction's execution
343  // (specifically for instructions that have side-effects that use
344  // the TC). Fix this.
345  bool no_squash_from_TC = thread->noSquashFromTC;
346  thread->noSquashFromTC = true;
347 
348  fault = staticInst->execute(this, traceData);
349 
350  thread->noSquashFromTC = no_squash_from_TC;
351 
352  return fault;
353 }
354 
355 Fault
357 {
358  // @todo: Pretty convoluted way to avoid squashing from happening
359  // when using the TC during an instruction's execution
360  // (specifically for instructions that have side-effects that use
361  // the TC). Fix this.
362  bool no_squash_from_TC = thread->noSquashFromTC;
363  thread->noSquashFromTC = true;
364 
366 
367  thread->noSquashFromTC = no_squash_from_TC;
368 
369  return fault;
370 }
371 
372 Fault
374 {
375  // @todo: Pretty convoluted way to avoid squashing from happening
376  // when using the TC during an instruction's execution
377  // (specifically for instructions that have side-effects that use
378  // the TC). Fix this.
379  bool no_squash_from_TC = thread->noSquashFromTC;
380  thread->noSquashFromTC = true;
381 
382  if (cpu->checker) {
383  if (isStoreConditional()) {
384  reqToVerify->setExtraData(pkt->req->getExtraData());
385  }
386  }
387 
388  fault = staticInst->completeAcc(pkt, this, traceData);
389 
390  thread->noSquashFromTC = no_squash_from_TC;
391 
392  return fault;
393 }
394 
395 void
396 DynInst::trap(const Fault &fault)
397 {
399 }
400 
401 Fault
403  const std::vector<bool> &byte_enable)
404 {
405  assert(byte_enable.size() == size);
406  return cpu->pushRequest(
407  dynamic_cast<DynInstPtr::PtrType>(this),
408  /* ld */ true, nullptr, size, addr, flags, nullptr, nullptr,
409  byte_enable);
410 }
411 
412 Fault
414 {
415  const unsigned int size = 8;
416  return cpu->pushRequest(
417  dynamic_cast<DynInstPtr::PtrType>(this),
418  /* ld */ true, nullptr, size, 0x0ul, flags, nullptr, nullptr,
419  std::vector<bool>(size, true));
420 }
421 
422 Fault
423 DynInst::writeMem(uint8_t *data, unsigned size, Addr addr,
424  Request::Flags flags, uint64_t *res,
425  const std::vector<bool> &byte_enable)
426 {
427  assert(byte_enable.size() == size);
428  return cpu->pushRequest(
429  dynamic_cast<DynInstPtr::PtrType>(this),
430  /* st */ false, data, size, addr, flags, res, nullptr,
431  byte_enable);
432 }
433 
434 Fault
436  AtomicOpFunctorPtr amo_op)
437 {
438  // atomic memory instructions do not have data to be written to memory yet
439  // since the atomic operations will be executed directly in cache/memory.
440  // Therefore, its `data` field is nullptr.
441  // Atomic memory requests need to carry their `amo_op` fields to cache/
442  // memory
443  return cpu->pushRequest(
444  dynamic_cast<DynInstPtr::PtrType>(this),
445  /* atomic */ false, nullptr, size, addr, flags, nullptr,
446  std::move(amo_op), std::vector<bool>(size, true));
447 }
448 
449 } // namespace o3
450 } // namespace gem5
gem5::MipsISA::fill
fill
Definition: pra_constants.hh:57
gem5::o3::CPU::dumpInsts
void dumpInsts()
Debug function to print all instructions on the list.
Definition: cpu.cc:1486
gem5::o3::CPU::pushRequest
Fault pushRequest(const DynInstPtr &inst, bool isLoad, uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, AtomicOpFunctorPtr amo_op=nullptr, const std::vector< bool > &byte_enable=std::vector< bool >())
CPU pushRequest function, forwards request to LSQ.
Definition: cpu.hh:603
gem5::o3::DynInst::Arrays
Definition: dyn_inst.hh:86
gem5::PhysRegId::isPinned
bool isPinned() const
Definition: reg_class.hh:316
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::o3::DynInst::predPC
std::unique_ptr< PCStateBase > predPC
Predicted PC state after this instruction.
Definition: dyn_inst.hh:324
gem5::o3::DynInst::Squashed
@ Squashed
Instruction has committed.
Definition: dyn_inst.hh:157
gem5::o3::DynInst::initiateAcc
Fault initiateAcc()
Initiates the access.
Definition: dyn_inst.cc:356
gem5::cprintf
void cprintf(const char *format, const Args &...args)
Definition: cprintf.hh:155
gem5::o3::DynInst::readySrcIdx
bool readySrcIdx(int idx) const
Definition: dyn_inst.hh:303
gem5::o3::DynInst::threadNumber
ThreadID threadNumber
The thread this instruction is from.
Definition: dyn_inst.hh:317
DPRINTFR
#define DPRINTFR(x,...)
Definition: trace.hh:200
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::o3::DynInst::RecordResult
@ RecordResult
Definition: dyn_inst.hh:182
gem5::o3::DynInst::numSrcRegs
size_t numSrcRegs() const
Returns the number of source registers.
Definition: dyn_inst.hh:678
gem5::o3::DynInst::setCanIssue
void setCanIssue()
Sets this instruction as ready to issue.
Definition: dyn_inst.hh:754
gem5::Packet::req
RequestPtr req
A pointer to the original request.
Definition: packet.hh:366
gem5::o3::DynInst::pc
std::unique_ptr< PCStateBase > pc
PC state for this instruction.
Definition: dyn_inst.hh:207
gem5::o3::DynInst::isStoreConditional
bool isStoreConditional() const
Definition: dyn_inst.hh:544
gem5::o3::DynInst::_readySrcIdx
uint8_t * _readySrcIdx
Definition: dyn_inst.hh:237
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::o3::DynInst::status
std::bitset< NumStatus > status
The status of this BaseDynInst.
Definition: dyn_inst.hh:198
gem5::o3::DynInst::_numDests
size_t _numDests
Definition: dyn_inst.hh:219
gem5::o3::DynInst::instFlags
std::bitset< MaxFlags > instFlags
Definition: dyn_inst.hh:195
gem5::o3::DynInst::isPinnedRegsRenamed
bool isPinnedRegsRenamed() const
Returns whether pinned registers are renamed.
Definition: dyn_inst.hh:856
gem5::o3::DynInst::seqNum
InstSeqNum seqNum
The sequence number of the instruction.
Definition: dyn_inst.hh:124
std::vector< bool >
dyn_inst.hh
gem5::o3::DynInst::numDestRegs
size_t numDestRegs() const
Returns the number of destination registers.
Definition: dyn_inst.hh:681
gem5::o3::DynInst::pcState
const PCStateBase & pcState() const override
Read the PC state of this instruction.
Definition: dyn_inst.hh:896
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::o3::DynInst::_prevDestIdx
PhysRegIdPtr * _prevDestIdx
Definition: dyn_inst.hh:231
gem5::o3::DynInst::Predicate
@ Predicate
Definition: dyn_inst.hh:183
gem5::RefCountingPtr< DynInst >::PtrType
DynInst * PtrType
Definition: refcnt.hh:129
gem5::o3::DynInst::thread
ThreadState * thread
Pointer to the thread state.
Definition: dyn_inst.hh:135
gem5::o3::DynInst::MemAccPredicate
@ MemAccPredicate
Definition: dyn_inst.hh:184
gem5::StaticInst::execute
virtual Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const =0
gem5::RefCountingPtr< StaticInst >
gem5::o3::DynInst::~DynInst
~DynInst()
Definition: dyn_inst.cc:190
gem5::o3::DynInst::dump
void dump()
Dumps out contents of this BaseDynInst.
Definition: dyn_inst.cc:278
gem5::o3::CPU::checker
gem5::Checker< DynInstPtr > * checker
Pointer to the checker, which can dynamically verify instruction results at run time.
Definition: cpu.hh:578
gem5::o3::DynInst::cpu
CPU * cpu
Pointer to the Impl's CPU object.
Definition: dyn_inst.hh:130
gem5::o3::DynInst::readyToIssue
bool readyToIssue() const
Returns whether or not this instruction is ready to issue.
Definition: dyn_inst.hh:757
gem5::PhysRegIdPtr
PhysRegId * PhysRegIdPtr
Definition: reg_class.hh:334
gem5::o3::DynInst::markSrcRegReady
void markSrcRegReady()
Records that one of the source registers is ready.
Definition: dyn_inst.cc:296
gem5::o3::DynInst::numSrcs
size_t numSrcs() const
Definition: dyn_inst.hh:240
gem5::Flags< FlagsType >
gem5::o3::CPU
O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buff...
Definition: cpu.hh:94
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::o3::DynInst::trap
void trap(const Fault &fault)
Traps to handle specified fault.
Definition: dyn_inst.cc:396
gem5::PhysRegId::incrNumPinnedWritesToComplete
void incrNumPinnedWritesToComplete()
Definition: reg_class.hh:331
gem5::o3::DynInst::setPinnedRegsSquashDone
void setPinnedRegsSquashDone()
Sets dest registers' status updated after squash.
Definition: dyn_inst.hh:888
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::X86ISA::count
count
Definition: misc.hh:709
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::o3::DynInst::execute
Fault execute()
Executes the instruction.
Definition: dyn_inst.cc:339
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::ArmISA::s
Bitfield< 4 > s
Definition: misc_types.hh:562
gem5::RefCounted::count
int count
Definition: refcnt.hh:67
gem5::o3::DynInst::staticInst
const StaticInstPtr staticInst
The StaticInst used by this BaseDynInst.
Definition: dyn_inst.hh:127
gem5::o3::DynInst::readyRegs
uint8_t readyRegs
How many source registers are ready.
Definition: dyn_inst.hh:330
gem5::o3::DynInst::writeMem
Fault writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable) override
Definition: dyn_inst.cc:423
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::o3::DynInst::DynInst
DynInst(const StaticInstPtr &staticInst, const StaticInstPtr &macroop, InstSeqNum seq_num, CPU *cpu)
gem5::o3::DynInst::completeAcc
Fault completeAcc(PacketPtr pkt)
Completes the access.
Definition: dyn_inst.cc:373
gem5::o3::DynInst::setSquashed
void setSquashed()
Sets this instruction as squashed.
Definition: dyn_inst.cc:314
gem5::o3::DynInst::_srcIdx
PhysRegIdPtr * _srcIdx
Definition: dyn_inst.hh:234
gem5::o3::ThreadState::noSquashFromTC
bool noSquashFromTC
Definition: thread_state.hh:84
gem5::o3::DynInst::isPinnedRegsSquashDone
bool isPinnedRegsSquashDone() const
Return whether dest registers' pinning status updated after squash.
Definition: dyn_inst.hh:881
gem5::o3::CPU::instcount
int instcount
Count of total number of dynamic instructions in flight.
Definition: cpu.hh:431
gem5::o3::DynInst::initiateMemAMO
Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override
Definition: dyn_inst.cc:435
gem5::StaticInst::completeAcc
virtual Fault completeAcc(Packet *pkt, ExecContext *xc, Trace::InstRecord *trace_data) const
Definition: static_inst.hh:316
gem5::StaticInst::disassemble
virtual const std::string & disassemble(Addr pc, const loader::SymbolTable *symtab=nullptr) const
Return string representation of disassembled instruction.
Definition: static_inst.cc:60
gem5::StaticInst::initiateAcc
virtual Fault initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const
Definition: static_inst.hh:310
gem5::PhysRegId::incrNumPinnedWrites
void incrNumPinnedWrites()
Definition: reg_class.hh:314
gem5::o3::CPU::trap
void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst)
Traps to handle given fault.
Definition: cpu.cc:844
gem5::o3::DynInst::traceData
Trace::InstRecord * traceData
InstRecord that tracks this instructions.
Definition: dyn_inst.hh:141
gem5::roundUp
static constexpr T roundUp(const T &val, const U &align)
This function is used to align addresses in memory.
Definition: intmath.hh:260
gem5::o3::DynInst::initiateMemRead
Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable) override
Definition: dyn_inst.cc:402
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::PhysRegId
Physical register ID.
Definition: reg_class.hh:224
gem5::o3::DynInst::initiateHtmCmd
Fault initiateHtmCmd(Request::Flags flags) override
Initiate an HTM command, e.g.
Definition: dyn_inst.cc:413
gem5::o3::DynInst::isPinnedRegsWritten
bool isPinnedRegsWritten() const
Returns whether destination registers are written.
Definition: dyn_inst.hh:868
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::o3::DynInst::renamedDestIdx
PhysRegIdPtr renamedDestIdx(int idx) const
Definition: dyn_inst.hh:262
intmath.hh
gem5::AtomicOpFunctorPtr
std::unique_ptr< AtomicOpFunctor > AtomicOpFunctorPtr
Definition: amo.hh:242
gem5::o3::DynInst::fault
Fault fault
The kind of fault this instruction has generated.
Definition: dyn_inst.hh:138
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::o3::DynInst::_numSrcs
size_t _numSrcs
Definition: dyn_inst.hh:218
gem5::o3::DynInst::_flatDestIdx
RegId * _flatDestIdx
Definition: dyn_inst.hh:223
gem5::o3::DynInst::_destIdx
PhysRegIdPtr * _destIdx
Definition: dyn_inst.hh:227
gem5::o3::DynInst::numDests
size_t numDests() const
Definition: dyn_inst.hh:241
gem5::o3::DynInst::reqToVerify
RequestPtr reqToVerify
Definition: dyn_inst.hh:367
gem5::o3::DynInst
Definition: dyn_inst.hh:76
gem5::o3::DynInst::memData
uint8_t * memData
Pointer to the data for the memory access.
Definition: dyn_inst.hh:347
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:113
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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