gem5  v21.1.0.2
dyn_inst.cc
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40 
41 #include "cpu/o3/dyn_inst.hh"
42 
43 #include <algorithm>
44 
45 #include "debug/DynInst.hh"
46 #include "debug/IQ.hh"
47 #include "debug/O3PipeView.hh"
48 
49 namespace gem5
50 {
51 
52 namespace o3
53 {
54 
55 DynInst::DynInst(const StaticInstPtr &static_inst,
56  const StaticInstPtr &_macroop, TheISA::PCState _pc,
57  TheISA::PCState pred_pc, InstSeqNum seq_num, CPU *_cpu)
58  : seqNum(seq_num), staticInst(static_inst), cpu(_cpu), pc(_pc),
59  regs(staticInst->numSrcRegs(), staticInst->numDestRegs()),
60  predPC(pred_pc), macroop(_macroop)
61 {
62  this->regs.init();
63 
64  status.reset();
65 
66  instFlags.reset();
67  instFlags[RecordResult] = true;
68  instFlags[Predicate] = true;
69  instFlags[MemAccPredicate] = true;
70 
71 #ifndef NDEBUG
72  ++cpu->instcount;
73 
74  if (cpu->instcount > 1500) {
75 #ifdef DEBUG
76  cpu->dumpInsts();
77  dumpSNList();
78 #endif
79  assert(cpu->instcount <= 1500);
80  }
81 
83  "DynInst: [sn:%lli] Instruction created. Instcount for %s = %i\n",
84  seqNum, cpu->name(), cpu->instcount);
85 #endif
86 
87 #ifdef DEBUG
88  cpu->snList.insert(seqNum);
89 #endif
90 
91 }
92 
93 DynInst::DynInst(const StaticInstPtr &_staticInst,
94  const StaticInstPtr &_macroop)
95  : DynInst(_staticInst, _macroop, {}, {}, 0, nullptr)
96 {}
97 
99 {
100 #if TRACING_ON
101  if (debug::O3PipeView) {
102  Tick fetch = this->fetchTick;
103  // fetchTick can be -1 if the instruction fetched outside the trace
104  // window.
105  if (fetch != -1) {
106  Tick val;
107  // Print info needed by the pipeline activity viewer.
108  DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n",
109  fetch,
110  this->instAddr(),
111  this->microPC(),
112  this->seqNum,
113  this->staticInst->disassemble(this->instAddr()));
114 
115  val = (this->decodeTick == -1) ? 0 : fetch + this->decodeTick;
116  DPRINTFR(O3PipeView, "O3PipeView:decode:%llu\n", val);
117  val = (this->renameTick == -1) ? 0 : fetch + this->renameTick;
118  DPRINTFR(O3PipeView, "O3PipeView:rename:%llu\n", val);
119  val = (this->dispatchTick == -1) ? 0 : fetch + this->dispatchTick;
120  DPRINTFR(O3PipeView, "O3PipeView:dispatch:%llu\n", val);
121  val = (this->issueTick == -1) ? 0 : fetch + this->issueTick;
122  DPRINTFR(O3PipeView, "O3PipeView:issue:%llu\n", val);
123  val = (this->completeTick == -1) ? 0 : fetch + this->completeTick;
124  DPRINTFR(O3PipeView, "O3PipeView:complete:%llu\n", val);
125  val = (this->commitTick == -1) ? 0 : fetch + this->commitTick;
126 
127  Tick valS = (this->storeTick == -1) ? 0 : fetch + this->storeTick;
128  DPRINTFR(O3PipeView, "O3PipeView:retire:%llu:store:%llu\n",
129  val, valS);
130  }
131  }
132 #endif
133 
134  delete [] memData;
135  delete traceData;
136  fault = NoFault;
137 
138 #ifndef NDEBUG
139  --cpu->instcount;
140 
142  "DynInst: [sn:%lli] Instruction destroyed. Instcount for %s = %i\n",
143  seqNum, cpu->name(), cpu->instcount);
144 #endif
145 #ifdef DEBUG
146  cpu->snList.erase(seqNum);
147 #endif
148 };
149 
150 
151 #ifdef DEBUG
152 void
153 DynInst::dumpSNList()
154 {
155  std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
156 
157  int count = 0;
158  while (sn_it != cpu->snList.end()) {
159  cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
160  count++;
161  sn_it++;
162  }
163 }
164 #endif
165 
166 void
168 {
169  cprintf("T%d : %#08d `", threadNumber, pc.instAddr());
170  std::cout << staticInst->disassemble(pc.instAddr());
171  cprintf("'\n");
172 }
173 
174 void
175 DynInst::dump(std::string &outstring)
176 {
177  std::ostringstream s;
178  s << "T" << threadNumber << " : 0x" << pc.instAddr() << " "
179  << staticInst->disassemble(pc.instAddr());
180 
181  outstring = s.str();
182 }
183 
184 void
186 {
187  DPRINTF(IQ, "[sn:%lli] has %d ready out of %d sources. RTI %d)\n",
189  if (++readyRegs == numSrcRegs()) {
190  setCanIssue();
191  }
192 }
193 
194 void
196 {
197  regs.readySrcIdx(src_idx, true);
198  markSrcRegReady();
199 }
200 
201 
202 void
204 {
205  status.set(Squashed);
206 
208  return;
209 
210  // This inst has been renamed already so it may go through rename
211  // again (e.g. if the squash is due to memory access order violation).
212  // Reset the write counters for all pinned destination register to ensure
213  // that they are in a consistent state for a possible re-rename. This also
214  // ensures that dest regs will be pinned to the same phys register if
215  // re-rename happens.
216  for (int idx = 0; idx < numDestRegs(); idx++) {
217  PhysRegIdPtr phys_dest_reg = regs.renamedDestIdx(idx);
218  if (phys_dest_reg->isPinned()) {
219  phys_dest_reg->incrNumPinnedWrites();
220  if (isPinnedRegsWritten())
221  phys_dest_reg->incrNumPinnedWritesToComplete();
222  }
223  }
225 }
226 
227 Fault
229 {
230  // @todo: Pretty convoluted way to avoid squashing from happening
231  // when using the TC during an instruction's execution
232  // (specifically for instructions that have side-effects that use
233  // the TC). Fix this.
234  bool no_squash_from_TC = this->thread->noSquashFromTC;
235  this->thread->noSquashFromTC = true;
236 
237  this->fault = this->staticInst->execute(this, this->traceData);
238 
239  this->thread->noSquashFromTC = no_squash_from_TC;
240 
241  return this->fault;
242 }
243 
244 Fault
246 {
247  // @todo: Pretty convoluted way to avoid squashing from happening
248  // when using the TC during an instruction's execution
249  // (specifically for instructions that have side-effects that use
250  // the TC). Fix this.
251  bool no_squash_from_TC = this->thread->noSquashFromTC;
252  this->thread->noSquashFromTC = true;
253 
254  this->fault = this->staticInst->initiateAcc(this, this->traceData);
255 
256  this->thread->noSquashFromTC = no_squash_from_TC;
257 
258  return this->fault;
259 }
260 
261 Fault
263 {
264  // @todo: Pretty convoluted way to avoid squashing from happening
265  // when using the TC during an instruction's execution
266  // (specifically for instructions that have side-effects that use
267  // the TC). Fix this.
268  bool no_squash_from_TC = this->thread->noSquashFromTC;
269  this->thread->noSquashFromTC = true;
270 
271  if (this->cpu->checker) {
272  if (this->isStoreConditional()) {
273  this->reqToVerify->setExtraData(pkt->req->getExtraData());
274  }
275  }
276 
277  this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
278 
279  this->thread->noSquashFromTC = no_squash_from_TC;
280 
281  return this->fault;
282 }
283 
284 void
285 DynInst::trap(const Fault &fault)
286 {
287  this->cpu->trap(fault, this->threadNumber, this->staticInst);
288 }
289 
290 Fault
292  const std::vector<bool> &byte_enable)
293 {
294  assert(byte_enable.size() == size);
295  return cpu->pushRequest(
296  dynamic_cast<DynInstPtr::PtrType>(this),
297  /* ld */ true, nullptr, size, addr, flags, nullptr, nullptr,
298  byte_enable);
299 }
300 
301 Fault
303 {
304  return cpu->pushRequest(
305  dynamic_cast<DynInstPtr::PtrType>(this),
306  /* ld */ true, nullptr, 8, 0x0ul, flags, nullptr, nullptr);
307 }
308 
309 Fault
310 DynInst::writeMem(uint8_t *data, unsigned size, Addr addr,
311  Request::Flags flags, uint64_t *res,
312  const std::vector<bool> &byte_enable)
313 {
314  assert(byte_enable.size() == size);
315  return cpu->pushRequest(
316  dynamic_cast<DynInstPtr::PtrType>(this),
317  /* st */ false, data, size, addr, flags, res, nullptr,
318  byte_enable);
319 }
320 
321 Fault
323  AtomicOpFunctorPtr amo_op)
324 {
325  // atomic memory instructions do not have data to be written to memory yet
326  // since the atomic operations will be executed directly in cache/memory.
327  // Therefore, its `data` field is nullptr.
328  // Atomic memory requests need to carry their `amo_op` fields to cache/
329  // memory
330  return cpu->pushRequest(
331  dynamic_cast<DynInstPtr::PtrType>(this),
332  /* atomic */ false, nullptr, size, addr, flags, nullptr,
333  std::move(amo_op), std::vector<bool>(size, true));
334 }
335 
336 } // namespace o3
337 } // namespace gem5
gem5::o3::CPU::dumpInsts
void dumpInsts()
Debug function to print all instructions on the list.
Definition: cpu.cc:1568
gem5::o3::CPU::pushRequest
Fault pushRequest(const DynInstPtr &inst, bool isLoad, uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, AtomicOpFunctorPtr amo_op=nullptr, const std::vector< bool > &byte_enable=std::vector< bool >())
CPU pushRequest function, forwards request to LSQ.
Definition: cpu.hh:626
gem5::PhysRegId::isPinned
bool isPinned() const
Definition: reg_class.hh:290
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::o3::DynInst::Squashed
@ Squashed
Instruction has committed.
Definition: dyn_inst.hh:135
gem5::o3::DynInst::microPC
Addr microPC() const
Read the micro PC of this instruction.
Definition: dyn_inst.hh:991
gem5::o3::DynInst::initiateAcc
Fault initiateAcc()
Initiates the access.
Definition: dyn_inst.cc:245
gem5::cprintf
void cprintf(const char *format, const Args &...args)
Definition: cprintf.hh:155
gem5::o3::DynInst::threadNumber
ThreadID threadNumber
The thread this instruction is from.
Definition: dyn_inst.hh:357
DPRINTFR
#define DPRINTFR(x,...)
Definition: trace.hh:200
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::o3::DynInst::RecordResult
@ RecordResult
Definition: dyn_inst.hh:160
gem5::o3::DynInst::numSrcRegs
size_t numSrcRegs() const
Returns the number of source registers.
Definition: dyn_inst.hh:727
gem5::o3::DynInst::pc
TheISA::PCState pc
PC state for this instruction.
Definition: dyn_inst.hh:185
gem5::o3::DynInst::setCanIssue
void setCanIssue()
Sets this instruction as ready to issue.
Definition: dyn_inst.hh:838
gem5::Packet::req
RequestPtr req
A pointer to the original request.
Definition: packet.hh:366
gem5::o3::DynInst::regs
Regs regs
Definition: dyn_inst.hh:354
gem5::o3::DynInst::isStoreConditional
bool isStoreConditional() const
Definition: dyn_inst.hh:593
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::o3::DynInst::status
std::bitset< NumStatus > status
The status of this BaseDynInst.
Definition: dyn_inst.hh:176
gem5::o3::DynInst::instFlags
std::bitset< MaxFlags > instFlags
Definition: dyn_inst.hh:173
gem5::o3::DynInst::isPinnedRegsRenamed
bool isPinnedRegsRenamed() const
Returns whether pinned registers are renamed.
Definition: dyn_inst.hh:940
gem5::o3::DynInst::seqNum
InstSeqNum seqNum
The sequence number of the instruction.
Definition: dyn_inst.hh:102
std::vector< bool >
dyn_inst.hh
gem5::o3::DynInst::numDestRegs
size_t numDestRegs() const
Returns the number of destination registers.
Definition: dyn_inst.hh:730
gem5::o3::DynInst::Predicate
@ Predicate
Definition: dyn_inst.hh:161
gem5::o3::DynInst::Regs::init
void init()
Definition: dyn_inst.hh:261
gem5::RefCountingPtr< DynInst >::PtrType
DynInst * PtrType
Definition: refcnt.hh:129
gem5::o3::DynInst::thread
ThreadState * thread
Pointer to the thread state.
Definition: dyn_inst.hh:113
gem5::o3::DynInst::MemAccPredicate
@ MemAccPredicate
Definition: dyn_inst.hh:162
gem5::StaticInst::execute
virtual Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const =0
gem5::RefCountingPtr< StaticInst >
gem5::o3::DynInst::~DynInst
~DynInst()
Definition: dyn_inst.cc:98
gem5::o3::DynInst::dump
void dump()
Dumps out contents of this BaseDynInst.
Definition: dyn_inst.cc:167
gem5::o3::CPU::checker
gem5::Checker< DynInstPtr > * checker
Pointer to the checker, which can dynamically verify instruction results at run time.
Definition: cpu.hh:602
gem5::o3::DynInst::cpu
CPU * cpu
Pointer to the Impl's CPU object.
Definition: dyn_inst.hh:108
gem5::o3::DynInst::readyToIssue
bool readyToIssue() const
Returns whether or not this instruction is ready to issue.
Definition: dyn_inst.hh:841
gem5::o3::DynInst::markSrcRegReady
void markSrcRegReady()
Records that one of the source registers is ready.
Definition: dyn_inst.cc:185
gem5::Flags< FlagsType >
gem5::o3::CPU
O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buff...
Definition: cpu.hh:95
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::o3::DynInst::trap
void trap(const Fault &fault)
Traps to handle specified fault.
Definition: dyn_inst.cc:285
gem5::PhysRegId::incrNumPinnedWritesToComplete
void incrNumPinnedWritesToComplete()
Definition: reg_class.hh:305
gem5::o3::DynInst::setPinnedRegsSquashDone
void setPinnedRegsSquashDone()
Sets dest registers' status updated after squash.
Definition: dyn_inst.hh:972
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::o3::DynInst::execute
Fault execute()
Executes the instruction.
Definition: dyn_inst.cc:228
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::ArmISA::s
Bitfield< 4 > s
Definition: misc_types.hh:561
gem5::RefCounted::count
int count
Definition: refcnt.hh:67
gem5::o3::DynInst::staticInst
const StaticInstPtr staticInst
The StaticInst used by this BaseDynInst.
Definition: dyn_inst.hh:105
gem5::o3::DynInst::readyRegs
uint8_t readyRegs
How many source registers are ready.
Definition: dyn_inst.hh:370
gem5::o3::DynInst::writeMem
Fault writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable) override
Definition: dyn_inst.cc:310
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::o3::DynInst::Regs::readySrcIdx
bool readySrcIdx(int idx) const
Definition: dyn_inst.hh:339
gem5::o3::DynInst::completeAcc
Fault completeAcc(PacketPtr pkt)
Completes the access.
Definition: dyn_inst.cc:262
gem5::o3::DynInst::setSquashed
void setSquashed()
Sets this instruction as squashed.
Definition: dyn_inst.cc:203
gem5::o3::DynInst::Regs::renamedDestIdx
PhysRegIdPtr renamedDestIdx(int idx) const
Definition: dyn_inst.hh:298
gem5::o3::ThreadState::noSquashFromTC
bool noSquashFromTC
Definition: thread_state.hh:84
gem5::o3::DynInst::isPinnedRegsSquashDone
bool isPinnedRegsSquashDone() const
Return whether dest registers' pinning status updated after squash.
Definition: dyn_inst.hh:965
gem5::o3::CPU::instcount
int instcount
Count of total number of dynamic instructions in flight.
Definition: cpu.hh:458
gem5::o3::DynInst::initiateMemAMO
Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override
Definition: dyn_inst.cc:322
gem5::StaticInst::completeAcc
virtual Fault completeAcc(Packet *pkt, ExecContext *xc, Trace::InstRecord *trace_data) const
Definition: static_inst.hh:317
gem5::StaticInst::disassemble
virtual const std::string & disassemble(Addr pc, const loader::SymbolTable *symtab=nullptr) const
Return string representation of disassembled instruction.
Definition: static_inst.cc:75
gem5::StaticInst::initiateAcc
virtual Fault initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const
Definition: static_inst.hh:311
gem5::PhysRegId::incrNumPinnedWrites
void incrNumPinnedWrites()
Definition: reg_class.hh:288
gem5::o3::CPU::trap
void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst)
Traps to handle given fault.
Definition: cpu.cc:902
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::o3::DynInst::traceData
Trace::InstRecord * traceData
InstRecord that tracks this instructions.
Definition: dyn_inst.hh:119
gem5::o3::DynInst::initiateMemRead
Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable) override
Definition: dyn_inst.cc:291
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::PhysRegId
Physical register ID.
Definition: reg_class.hh:198
gem5::o3::DynInst::DynInst
DynInst(const StaticInstPtr &staticInst, const StaticInstPtr &macroop, TheISA::PCState pc, TheISA::PCState predPC, InstSeqNum seq_num, CPU *cpu)
BaseDynInst constructor given a binary instruction.
Definition: dyn_inst.cc:55
gem5::o3::DynInst::initiateHtmCmd
Fault initiateHtmCmd(Request::Flags flags) override
Initiate an HTM command, e.g.
Definition: dyn_inst.cc:302
gem5::o3::DynInst::isPinnedRegsWritten
bool isPinnedRegsWritten() const
Returns whether destination registers are written.
Definition: dyn_inst.hh:952
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::AtomicOpFunctorPtr
std::unique_ptr< AtomicOpFunctor > AtomicOpFunctorPtr
Definition: amo.hh:242
gem5::o3::DynInst::fault
Fault fault
The kind of fault this instruction has generated.
Definition: dyn_inst.hh:116
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::o3::DynInst::instAddr
Addr instAddr() const
Read the PC of this instruction.
Definition: dyn_inst.hh:985
gem5::o3::DynInst::reqToVerify
RequestPtr reqToVerify
Definition: dyn_inst.hh:407
gem5::o3::DynInst
Definition: dyn_inst.hh:76
gem5::o3::DynInst::memData
uint8_t * memData
Pointer to the data for the memory access.
Definition: dyn_inst.hh:387
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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