gem5  v22.1.0.0
dyn_inst.hh
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41 
42 #ifndef __CPU_O3_DYN_INST_HH__
43 #define __CPU_O3_DYN_INST_HH__
44 
45 #include <algorithm>
46 #include <array>
47 #include <deque>
48 #include <list>
49 #include <string>
50 
51 #include "base/refcnt.hh"
52 #include "base/trace.hh"
53 #include "cpu/checker/cpu.hh"
54 #include "cpu/exec_context.hh"
55 #include "cpu/exetrace.hh"
56 #include "cpu/inst_res.hh"
57 #include "cpu/inst_seq.hh"
58 #include "cpu/o3/cpu.hh"
59 #include "cpu/o3/dyn_inst_ptr.hh"
60 #include "cpu/o3/lsq_unit.hh"
61 #include "cpu/op_class.hh"
62 #include "cpu/reg_class.hh"
63 #include "cpu/static_inst.hh"
64 #include "cpu/translation.hh"
65 #include "debug/HtmCpu.hh"
66 
67 namespace gem5
68 {
69 
70 class Packet;
71 
72 namespace o3
73 {
74 
75 class DynInst : public ExecContext, public RefCounted
76 {
77  private:
79  InstSeqNum seq_num, CPU *cpu);
80 
81  public:
82  // The list of instructions iterator type.
84 
85  struct Arrays
86  {
87  size_t numSrcs;
88  size_t numDests;
89 
94  uint8_t *readySrcIdx;
95  };
96 
97  static void *operator new(size_t count, Arrays &arrays);
98 
100  DynInst(const Arrays &arrays, const StaticInstPtr &staticInst,
101  const StaticInstPtr &macroop, InstSeqNum seq_num, CPU *cpu);
102 
103  DynInst(const Arrays &arrays, const StaticInstPtr &staticInst,
104  const StaticInstPtr &macroop, const PCStateBase &pc,
105  const PCStateBase &pred_pc, InstSeqNum seq_num, CPU *cpu);
106 
108  DynInst(const Arrays &arrays, const StaticInstPtr &_staticInst,
109  const StaticInstPtr &_macroop);
110 
111  ~DynInst();
112 
114  Fault execute();
115 
117  Fault initiateAcc();
118 
121 
124 
127 
129  CPU *cpu = nullptr;
130 
131  BaseCPU *getCpuPtr() { return cpu; }
132 
134  ThreadState *thread = nullptr;
135 
138 
141 
142  protected:
143  enum Status
144  {
170  NumStatus
171  };
172 
173  enum Flags
174  {
189  MaxFlags
190  };
191 
192  private:
193  /* An amalgamation of a lot of boolean values into one */
194  std::bitset<MaxFlags> instFlags;
195 
197  std::bitset<NumStatus> status;
198 
199  protected:
203  std::queue<InstResult> instResult;
204 
206  std::unique_ptr<PCStateBase> pc;
207 
210 
216 
217  size_t _numSrcs;
218  size_t _numDests;
219 
220  // Flattened register index of the destination registers of this
221  // instruction.
223 
224  // Physical register index of the destination registers of this
225  // instruction.
227 
228  // Physical register index of the previous producers of the
229  // architected destinations.
231 
232  // Physical register index of the source registers of this instruction.
234 
235  // Whether or not the source register is ready, one bit per register.
236  uint8_t *_readySrcIdx;
237 
238  public:
239  size_t numSrcs() const { return _numSrcs; }
240  size_t numDests() const { return _numDests; }
241 
242  // Returns the flattened register index of the idx'th destination
243  // register.
244  const RegId &
245  flattenedDestIdx(int idx) const
246  {
247  return _flatDestIdx[idx];
248  }
249 
250  // Flattens a destination architectural register index into a logical
251  // index.
252  void
253  flattenedDestIdx(int idx, const RegId &reg_id)
254  {
255  _flatDestIdx[idx] = reg_id;
256  }
257 
258  // Returns the physical register index of the idx'th destination
259  // register.
261  renamedDestIdx(int idx) const
262  {
263  return _destIdx[idx];
264  }
265 
266  // Set the renamed dest register id.
267  void
268  renamedDestIdx(int idx, PhysRegIdPtr phys_reg_id)
269  {
270  _destIdx[idx] = phys_reg_id;
271  }
272 
273  // Returns the physical register index of the previous physical
274  // register that remapped to the same logical register index.
276  prevDestIdx(int idx) const
277  {
278  return _prevDestIdx[idx];
279  }
280 
281  // Set the previous renamed dest register id.
282  void
283  prevDestIdx(int idx, PhysRegIdPtr phys_reg_id)
284  {
285  _prevDestIdx[idx] = phys_reg_id;
286  }
287 
288  // Returns the physical register index of the i'th source register.
290  renamedSrcIdx(int idx) const
291  {
292  return _srcIdx[idx];
293  }
294 
295  void
296  renamedSrcIdx(int idx, PhysRegIdPtr phys_reg_id)
297  {
298  _srcIdx[idx] = phys_reg_id;
299  }
300 
301  bool
302  readySrcIdx(int idx) const
303  {
304  uint8_t &byte = _readySrcIdx[idx / 8];
305  return bits(byte, idx % 8);
306  }
307 
308  void
309  readySrcIdx(int idx, bool ready)
310  {
311  uint8_t &byte = _readySrcIdx[idx / 8];
312  replaceBits(byte, idx % 8, ready ? 1 : 0);
313  }
314 
317 
320 
322 
323  std::unique_ptr<PCStateBase> predPC;
324 
327 
329  uint8_t readyRegs = 0;
330 
331  public:
333 
335 
338 
340  unsigned memReqFlags = 0;
341 
343  unsigned effSize;
344 
346  uint8_t *memData = nullptr;
347 
349  ssize_t lqIdx = -1;
351 
353  ssize_t sqIdx = -1;
355 
356 
358 
363 
365  // Need a copy of main request pointer to verify on writes.
367 
368  public:
370  void recordResult(bool f) { instFlags[RecordResult] = f; }
371 
373  bool effAddrValid() const { return instFlags[EffAddrValid]; }
374  void effAddrValid(bool b) { instFlags[EffAddrValid] = b; }
375 
377  bool memOpDone() const { return instFlags[MemOpDone]; }
378  void memOpDone(bool f) { instFlags[MemOpDone] = f; }
379 
380  bool notAnInst() const { return instFlags[NotAnInst]; }
381  void setNotAnInst() { instFlags[NotAnInst] = true; }
382 
383 
385  //
386  // INSTRUCTION EXECUTION
387  //
389 
390  void
391  demapPage(Addr vaddr, uint64_t asn) override
392  {
393  cpu->demapPage(vaddr, asn);
394  }
395 
397  const std::vector<bool> &byte_enable) override;
398 
400 
401  Fault writeMem(uint8_t *data, unsigned size, Addr addr,
402  Request::Flags flags, uint64_t *res,
403  const std::vector<bool> &byte_enable) override;
404 
406  AtomicOpFunctorPtr amo_op) override;
407 
411 
413  bool
415  {
417  }
419 
425  bool
427  {
429  }
430  void
432  {
434  }
435 
440  bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; }
442 
447  bool
449  {
450  return (translationStarted() && !translationCompleted());
451  }
452 
453  public:
454 #ifdef DEBUG
455  void dumpSNList();
456 #endif
457 
461  void
462  renameDestReg(int idx, PhysRegIdPtr renamed_dest,
463  PhysRegIdPtr previous_rename)
464  {
465  renamedDestIdx(idx, renamed_dest);
466  prevDestIdx(idx, previous_rename);
467  if (renamed_dest->isPinned())
469  }
470 
475  void
476  renameSrcReg(int idx, PhysRegIdPtr renamed_src)
477  {
478  renamedSrcIdx(idx, renamed_src);
479  }
480 
482  void dump();
483 
485  void dump(std::string &outstring);
486 
488  int cpuId() const { return cpu->cpuId(); }
489 
491  uint32_t socketId() const { return cpu->socketId(); }
492 
495 
497  ContextID contextId() const { return thread->contextId(); }
498 
500  Fault getFault() const { return fault; }
503  Fault& getFault() { return fault; }
504 
510  bool doneTargCalc() { return false; }
511 
513  void setPredTarg(const PCStateBase &pred_pc) { set(predPC, pred_pc); }
514 
515  const PCStateBase &readPredTarg() { return *predPC; }
516 
518  bool readPredTaken() { return instFlags[PredTaken]; }
519 
520  void
521  setPredTaken(bool predicted_taken)
522  {
523  instFlags[PredTaken] = predicted_taken;
524  }
525 
527  bool
529  {
530  std::unique_ptr<PCStateBase> next_pc(pc->clone());
531  staticInst->advancePC(*next_pc);
532  return *next_pc != *predPC;
533  }
534 
535  //
536  // Instruction types. Forward checks to StaticInst object.
537  //
538  bool isNop() const { return staticInst->isNop(); }
539  bool isMemRef() const { return staticInst->isMemRef(); }
540  bool isLoad() const { return staticInst->isLoad(); }
541  bool isStore() const { return staticInst->isStore(); }
542  bool isAtomic() const { return staticInst->isAtomic(); }
543  bool isStoreConditional() const
544  { return staticInst->isStoreConditional(); }
545  bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
546  bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
547  bool isInteger() const { return staticInst->isInteger(); }
548  bool isFloating() const { return staticInst->isFloating(); }
549  bool isVector() const { return staticInst->isVector(); }
550  bool isControl() const { return staticInst->isControl(); }
551  bool isCall() const { return staticInst->isCall(); }
552  bool isReturn() const { return staticInst->isReturn(); }
553  bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
554  bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
555  bool isCondCtrl() const { return staticInst->isCondCtrl(); }
556  bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
557  bool isSerializing() const { return staticInst->isSerializing(); }
558  bool
560  {
562  }
563  bool
565  {
567  }
568  bool isSquashAfter() const { return staticInst->isSquashAfter(); }
569  bool isFullMemBarrier() const { return staticInst->isFullMemBarrier(); }
570  bool isReadBarrier() const { return staticInst->isReadBarrier(); }
571  bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
572  bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
573  bool isQuiesce() const { return staticInst->isQuiesce(); }
574  bool isUnverifiable() const { return staticInst->isUnverifiable(); }
575  bool isSyscall() const { return staticInst->isSyscall(); }
576  bool isMacroop() const { return staticInst->isMacroop(); }
577  bool isMicroop() const { return staticInst->isMicroop(); }
578  bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
579  bool isLastMicroop() const { return staticInst->isLastMicroop(); }
580  bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
581  // hardware transactional memory
582  bool isHtmStart() const { return staticInst->isHtmStart(); }
583  bool isHtmStop() const { return staticInst->isHtmStop(); }
584  bool isHtmCancel() const { return staticInst->isHtmCancel(); }
585  bool isHtmCmd() const { return staticInst->isHtmCmd(); }
586 
587  uint64_t
588  getHtmTransactionUid() const override
589  {
590  assert(instFlags[HtmFromTransaction]);
591  return htmUid;
592  }
593 
594  uint64_t
595  newHtmTransactionUid() const override
596  {
597  panic("Not yet implemented\n");
598  return 0;
599  }
600 
601  bool
602  inHtmTransactionalState() const override
603  {
605  }
606 
607  uint64_t
608  getHtmTransactionalDepth() const override
609  {
611  return htmDepth;
612  else
613  return 0;
614  }
615 
616  void
617  setHtmTransactionalState(uint64_t htm_uid, uint64_t htm_depth)
618  {
620  htmUid = htm_uid;
621  htmDepth = htm_depth;
622  }
623 
624  void
626  {
627  if (inHtmTransactionalState()) {
628  DPRINTF(HtmCpu,
629  "clearing instuction's transactional state htmUid=%u\n",
631 
633  htmUid = -1;
634  htmDepth = 0;
635  }
636  }
637 
640 
643 
646 
649 
652 
655 
658 
665 
667  OpClass opClass() const { return staticInst->opClass(); }
668 
670  std::unique_ptr<PCStateBase>
671  branchTarget() const
672  {
673  return staticInst->branchTarget(*pc);
674  }
675 
677  size_t numSrcRegs() const { return numSrcs(); }
678 
680  size_t numDestRegs() const { return numDests(); }
681 
682  size_t
684  {
685  return staticInst->numDestRegs(type);
686  }
687 
689  const RegId& destRegIdx(int i) const { return staticInst->destRegIdx(i); }
690 
692  const RegId& srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
693 
695  uint8_t resultSize() { return instResult.size(); }
696 
700  InstResult
702  {
703  if (!instResult.empty()) {
704  InstResult t = instResult.front();
705  instResult.pop();
706  return t;
707  }
708  return dflt;
709  }
710 
713  template<typename T>
714  void
715  setResult(const RegClass &reg_class, T &&t)
716  {
717  if (instFlags[RecordResult]) {
718  instResult.emplace(reg_class, std::forward<T>(t));
719  }
720  }
724  void markSrcRegReady();
725 
727  void markSrcRegReady(RegIndex src_idx);
728 
730  void setCompleted() { status.set(Completed); }
731 
733  bool isCompleted() const { return status[Completed]; }
734 
737 
739  bool isResultReady() const { return status[ResultReady]; }
740 
742  void setCanIssue() { status.set(CanIssue); }
743 
745  bool readyToIssue() const { return status[CanIssue]; }
746 
748  void clearCanIssue() { status.reset(CanIssue); }
749 
751  void setIssued() { status.set(Issued); }
752 
754  bool isIssued() const { return status[Issued]; }
755 
757  void clearIssued() { status.reset(Issued); }
758 
760  void setExecuted() { status.set(Executed); }
761 
763  bool isExecuted() const { return status[Executed]; }
764 
766  void setCanCommit() { status.set(CanCommit); }
767 
769  void clearCanCommit() { status.reset(CanCommit); }
770 
772  bool readyToCommit() const { return status[CanCommit]; }
773 
774  void setAtCommit() { status.set(AtCommit); }
775 
776  bool isAtCommit() { return status[AtCommit]; }
777 
779  void setCommitted() { status.set(Committed); }
780 
782  bool isCommitted() const { return status[Committed]; }
783 
785  void setSquashed();
786 
788  bool isSquashed() const { return status[Squashed]; }
789 
790  //Instruction Queue Entry
791  //-----------------------
793  void setInIQ() { status.set(IqEntry); }
794 
796  void clearInIQ() { status.reset(IqEntry); }
797 
799  bool isInIQ() const { return status[IqEntry]; }
800 
803 
805  bool isSquashedInIQ() const { return status[SquashedInIQ]; }
806 
807 
808  //Load / Store Queue Functions
809  //-----------------------
811  void setInLSQ() { status.set(LsqEntry); }
812 
814  void removeInLSQ() { status.reset(LsqEntry); }
815 
817  bool isInLSQ() const { return status[LsqEntry]; }
818 
821 
823  bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
824 
825 
826  //Reorder Buffer Functions
827  //-----------------------
829  void setInROB() { status.set(RobEntry); }
830 
832  void clearInROB() { status.reset(RobEntry); }
833 
835  bool isInROB() const { return status[RobEntry]; }
836 
839 
841  bool isSquashedInROB() const { return status[SquashedInROB]; }
842 
844  bool isPinnedRegsRenamed() const { return status[PinnedRegsRenamed]; }
845 
847  void
849  {
850  assert(!status[PinnedRegsSquashDone]);
851  assert(!status[PinnedRegsWritten]);
853  }
854 
856  bool isPinnedRegsWritten() const { return status[PinnedRegsWritten]; }
857 
859  void
861  {
862  assert(!status[PinnedRegsSquashDone]);
863  assert(status[PinnedRegsRenamed]);
865  }
866 
868  bool
870  {
872  }
873 
875  void
877  {
878  assert(!status[PinnedRegsSquashDone]);
880  }
881 
883  const PCStateBase &
884  pcState() const override
885  {
886  return *pc;
887  }
888 
890  void pcState(const PCStateBase &val) override { set(pc, val); }
891 
892  bool readPredicate() const override { return instFlags[Predicate]; }
893 
894  void
895  setPredicate(bool val) override
896  {
898 
899  if (traceData) {
901  }
902  }
903 
904  bool
905  readMemAccPredicate() const override
906  {
907  return instFlags[MemAccPredicate];
908  }
909 
910  void
911  setMemAccPredicate(bool val) override
912  {
914  }
915 
917  void setTid(ThreadID tid) { threadNumber = tid; }
918 
921 
923  gem5::ThreadContext *tcBase() const override { return thread->getTC(); }
924 
925  public:
927  bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; }
929 
931  bool hasRequest() const { return instFlags[ReqMade]; }
933  void setRequest() { instFlags[ReqMade] = true; }
934 
937 
939  void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
940 
941  public:
943  unsigned int
944  readStCondFailures() const override
945  {
946  return thread->storeCondFailures;
947  }
948 
950  void
951  setStCondFailures(unsigned int sc_failures) override
952  {
953  thread->storeCondFailures = sc_failures;
954  }
955 
956  public:
957  // monitor/mwait funtions
958  void
959  armMonitor(Addr address) override
960  {
961  cpu->armMonitor(threadNumber, address);
962  }
963  bool
964  mwait(PacketPtr pkt) override
965  {
966  return cpu->mwait(threadNumber, pkt);
967  }
968  void
970  {
971  return cpu->mwaitAtomic(threadNumber, tc, cpu->mmu);
972  }
974  getAddrMonitor() override
975  {
977  }
978 
979  private:
980  // hardware transactional memory
981  uint64_t htmUid = -1;
982  uint64_t htmDepth = 0;
983 
984  public:
985 #if TRACING_ON
986  // Value -1 indicates that particular phase
987  // hasn't happened (yet).
989  Tick fetchTick = -1; // instruction fetch is completed.
990  int32_t decodeTick = -1; // instruction enters decode phase
991  int32_t renameTick = -1; // instruction enters rename phase
992  int32_t dispatchTick = -1;
993  int32_t issueTick = -1;
994  int32_t completeTick = -1;
995  int32_t commitTick = -1;
996  int32_t storeTick = -1;
997 #endif
998 
999  /* Values used by LoadToUse stat */
1002 
1006  RegVal
1007  readMiscReg(int misc_reg) override
1008  {
1009  return cpu->readMiscReg(misc_reg, threadNumber);
1010  }
1011 
1015  void
1016  setMiscReg(int misc_reg, RegVal val) override
1017  {
1024  for (auto &idx: _destMiscRegIdx) {
1025  if (idx == misc_reg)
1026  return;
1027  }
1028 
1029  _destMiscRegIdx.push_back(misc_reg);
1030  _destMiscRegVal.push_back(val);
1031  }
1032 
1036  RegVal
1037  readMiscRegOperand(const StaticInst *si, int idx) override
1038  {
1039  const RegId& reg = si->srcRegIdx(idx);
1040  assert(reg.is(MiscRegClass));
1041  return cpu->readMiscReg(reg.index(), threadNumber);
1042  }
1043 
1047  void
1048  setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
1049  {
1050  const RegId& reg = si->destRegIdx(idx);
1051  assert(reg.is(MiscRegClass));
1052  setMiscReg(reg.index(), val);
1053  }
1054 
1056  void
1058  {
1059  // @todo: Pretty convoluted way to avoid squashing from happening when
1060  // using the TC during an instruction's execution (specifically for
1061  // instructions that have side-effects that use the TC). Fix this.
1062  // See cpu/o3/dyn_inst_impl.hh.
1063  bool no_squash_from_TC = thread->noSquashFromTC;
1064  thread->noSquashFromTC = true;
1065 
1066  for (int i = 0; i < _destMiscRegIdx.size(); i++)
1067  cpu->setMiscReg(
1069 
1070  thread->noSquashFromTC = no_squash_from_TC;
1071  }
1072 
1073  void
1075  {
1076 
1077  for (int idx = 0; idx < numDestRegs(); idx++) {
1078  PhysRegIdPtr prev_phys_reg = prevDestIdx(idx);
1079  const RegId& original_dest_reg = staticInst->destRegIdx(idx);
1080  const auto bytes = original_dest_reg.regClass().regBytes();
1081 
1082  // Registers which aren't renamed don't need to be forwarded.
1083  if (!original_dest_reg.isRenameable())
1084  continue;
1085 
1086  if (bytes == sizeof(RegVal)) {
1087  setRegOperand(staticInst.get(), idx,
1088  cpu->getReg(prev_phys_reg));
1089  } else {
1090  uint8_t val[original_dest_reg.regClass().regBytes()];
1091  cpu->getReg(prev_phys_reg, val);
1092  setRegOperand(staticInst.get(), idx, val);
1093  }
1094  }
1095  }
1097  void trap(const Fault &fault);
1098 
1099  public:
1100 
1101  // The register accessor methods provide the index of the
1102  // instruction's operand (e.g., 0 or 1), not the architectural
1103  // register index, to simplify the implementation of register
1104  // renaming. We find the architectural register index by indexing
1105  // into the instruction's own operand index table. Note that a
1106  // raw pointer to the StaticInst is provided instead of a
1107  // ref-counted StaticInstPtr to redice overhead. This is fine as
1108  // long as these methods don't copy the pointer into any long-term
1109  // storage (which is pretty hard to imagine they would have reason
1110  // to do).
1111 
1112  RegVal
1113  getRegOperand(const StaticInst *si, int idx) override
1114  {
1115  const PhysRegIdPtr reg = renamedSrcIdx(idx);
1116  if (reg->is(InvalidRegClass))
1117  return 0;
1118  return cpu->getReg(reg);
1119  }
1120 
1121  void
1122  getRegOperand(const StaticInst *si, int idx, void *val) override
1123  {
1124  const PhysRegIdPtr reg = renamedSrcIdx(idx);
1125  if (reg->is(InvalidRegClass))
1126  return;
1127  cpu->getReg(reg, val);
1128  }
1129 
1130  void *
1131  getWritableRegOperand(const StaticInst *si, int idx) override
1132  {
1133  return cpu->getWritableReg(renamedDestIdx(idx));
1134  }
1135 
1139  void
1140  setRegOperand(const StaticInst *si, int idx, RegVal val) override
1141  {
1142  const PhysRegIdPtr reg = renamedDestIdx(idx);
1143  if (reg->is(InvalidRegClass))
1144  return;
1145  cpu->setReg(reg, val);
1146  setResult(reg->regClass(), val);
1147  }
1148 
1149  void
1150  setRegOperand(const StaticInst *si, int idx, const void *val) override
1151  {
1152  const PhysRegIdPtr reg = renamedDestIdx(idx);
1153  if (reg->is(InvalidRegClass))
1154  return;
1155  cpu->setReg(reg, val);
1156  setResult(reg->regClass(), val);
1157  }
1158 };
1159 
1160 } // namespace o3
1161 } // namespace gem5
1162 
1163 #endif // __CPU_O3_DYN_INST_HH__
#define DPRINTF(x,...)
Definition: trace.hh:186
const char data[]
RequestorID dataRequestorId() const
Reads this CPU's unique data requestor ID.
Definition: base.hh:189
uint32_t socketId() const
Reads this CPU's Socket ID.
Definition: base.hh:186
AddressMonitor * getCpuAddrMonitor(ThreadID tid)
Definition: base.hh:633
void mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseMMU *mmu)
Definition: base.cc:240
bool mwait(ThreadID tid, PacketPtr pkt)
Definition: base.cc:217
int cpuId() const
Reads this CPU's ID.
Definition: base.hh:183
void armMonitor(ThreadID tid, Addr address)
Definition: base.cc:205
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:72
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:294
Physical register ID.
Definition: reg_class.hh:392
bool isPinned() const
Definition: reg_class.hh:469
Derive from RefCounted if you want to enable reference counting of this class.
Definition: refcnt.hh:61
T * get() const
Directly access the pointer itself without taking a reference.
Definition: refcnt.hh:227
constexpr size_t regBytes() const
Definition: reg_class.hh:236
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:91
constexpr bool isRenameable() const
Return true if this register can be renamed.
Definition: reg_class.hh:138
constexpr const RegClass & regClass() const
Class accessor.
Definition: reg_class.hh:151
Base, ISA-independent static instruction class.
Definition: static_inst.hh:89
bool isInteger() const
Definition: static_inst.hh:156
bool isQuiesce() const
Definition: static_inst.hh:182
bool isHtmStop() const
Definition: static_inst.hh:194
bool isUnverifiable() const
Definition: static_inst.hh:183
OpClass opClass() const
Operation class. Used to select appropriate function unit in issue.
Definition: static_inst.hh:210
const RegId & srcRegIdx(int i) const
Return logical index (architectural reg num) of i'th source reg.
Definition: static_inst.hh:225
bool isSyscall() const
Definition: static_inst.hh:184
bool isStoreConditional() const
Definition: static_inst.hh:150
bool isFirstMicroop() const
Definition: static_inst.hh:189
bool isDirectCtrl() const
Definition: static_inst.hh:163
bool isHtmCmd() const
Definition: static_inst.hh:198
bool isUncondCtrl() const
Definition: static_inst.hh:166
bool isSerializeBefore() const
Definition: static_inst.hh:171
bool isLoad() const
Definition: static_inst.hh:147
virtual std::unique_ptr< PCStateBase > branchTarget(const PCStateBase &pc) const
Return the target address for a PC-relative branch.
Definition: static_inst.cc:46
bool isSquashAfter() const
Definition: static_inst.hh:173
uint8_t numDestRegs() const
Number of destination registers.
Definition: static_inst.hh:125
virtual void advancePC(PCStateBase &pc_state) const =0
bool isHtmCancel() const
Definition: static_inst.hh:195
bool isFloating() const
Definition: static_inst.hh:157
bool isWriteBarrier() const
Definition: static_inst.hh:180
bool isNop() const
Definition: static_inst.hh:140
bool isMacroop() const
Definition: static_inst.hh:185
bool isReturn() const
Definition: static_inst.hh:162
bool isMemRef() const
Definition: static_inst.hh:143
bool isReadBarrier() const
Definition: static_inst.hh:179
bool isNonSpeculative() const
Definition: static_inst.hh:181
bool isDataPrefetch() const
Definition: static_inst.hh:152
bool isIndirectCtrl() const
Definition: static_inst.hh:164
bool isVector() const
Definition: static_inst.hh:158
bool isHtmStart() const
Definition: static_inst.hh:193
bool isLastMicroop() const
Definition: static_inst.hh:188
bool isFullMemBarrier() const
Definition: static_inst.hh:175
bool isStore() const
Definition: static_inst.hh:148
bool isInstPrefetch() const
Definition: static_inst.hh:151
bool isSerializing() const
Definition: static_inst.hh:168
const RegId & destRegIdx(int i) const
Return logical index (architectural reg num) of i'th destination reg.
Definition: static_inst.hh:215
bool isAtomic() const
Definition: static_inst.hh:149
bool isMicroop() const
Definition: static_inst.hh:186
bool isCall() const
Definition: static_inst.hh:161
bool isCondCtrl() const
Definition: static_inst.hh:165
bool isDelayedCommit() const
Definition: static_inst.hh:187
bool isControl() const
Definition: static_inst.hh:160
bool isSerializeAfter() const
Definition: static_inst.hh:172
ThreadContext is the external interface to all thread state for anything outside of the CPU.
O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buff...
Definition: cpu.hh:94
RegVal getReg(PhysRegIdPtr phys_reg)
Definition: cpu.cc:1037
void * getWritableReg(PhysRegIdPtr phys_reg)
Definition: cpu.cc:1089
void setMiscReg(int misc_reg, RegVal val, ThreadID tid)
Sets a misc.
Definition: cpu.cc:1030
void setReg(PhysRegIdPtr phys_reg, RegVal val)
Definition: cpu.cc:1105
void demapPage(Addr vaddr, uint64_t asn)
Definition: cpu.hh:180
BaseMMU * mmu
Definition: cpu.hh:110
RegVal readMiscReg(int misc_reg, ThreadID tid)
Reads a misc.
Definition: cpu.cc:1017
bool hasRequest() const
Has this instruction generated a memory request.
Definition: dyn_inst.hh:931
std::list< DynInstPtr >::iterator ListIt
Definition: dyn_inst.hh:83
const PCStateBase & pcState() const override
Read the PC state of this instruction.
Definition: dyn_inst.hh:884
bool isCompleted() const
Returns whether or not this instruction is completed.
Definition: dyn_inst.hh:733
uint8_t readyRegs
How many source registers are ready.
Definition: dyn_inst.hh:329
uint8_t * memData
Pointer to the data for the memory access.
Definition: dyn_inst.hh:346
gem5::ThreadContext * tcBase() const override
Returns the thread context.
Definition: dyn_inst.hh:923
RequestorID requestorId() const
Read this CPU's data requestor ID.
Definition: dyn_inst.hh:494
bool isStoreConditional() const
Definition: dyn_inst.hh:543
unsigned memReqFlags
The memory request flags (from translation).
Definition: dyn_inst.hh:340
bool isDirectCtrl() const
Definition: dyn_inst.hh:553
bool isMicroop() const
Definition: dyn_inst.hh:577
size_t numDestRegs(RegClassType type) const
Definition: dyn_inst.hh:683
RequestPtr reqToVerify
Definition: dyn_inst.hh:366
bool isHtmStart() const
Definition: dyn_inst.hh:582
RegVal readMiscRegOperand(const StaticInst *si, int idx) override
Reads a misc.
Definition: dyn_inst.hh:1037
bool isCondCtrl() const
Definition: dyn_inst.hh:555
void memOpDone(bool f)
Definition: dyn_inst.hh:378
bool isSquashAfter() const
Definition: dyn_inst.hh:568
bool doneTargCalc()
Checks whether or not this instruction has had its branch target calculated yet.
Definition: dyn_inst.hh:510
void setIssued()
Sets this instruction as issued from the IQ.
Definition: dyn_inst.hh:751
void forwardOldRegs()
Definition: dyn_inst.hh:1074
ThreadState * thread
Pointer to the thread state.
Definition: dyn_inst.hh:134
bool isIndirectCtrl() const
Definition: dyn_inst.hh:554
void clearCanIssue()
Clears this instruction being able to issue.
Definition: dyn_inst.hh:748
Fault & getFault()
TODO: This I added for the LSQRequest side to be able to modify the fault.
Definition: dyn_inst.hh:503
void clearSerializeAfter()
Clears the serializeAfter part of this instruction.
Definition: dyn_inst.hh:651
void setAtCommit()
Definition: dyn_inst.hh:774
PhysRegIdPtr * _prevDestIdx
Definition: dyn_inst.hh:230
std::unique_ptr< PCStateBase > predPC
Predicted PC state after this instruction.
Definition: dyn_inst.hh:323
bool isUncondCtrl() const
Definition: dyn_inst.hh:556
unsigned effSize
The size of the request.
Definition: dyn_inst.hh:343
const RegId & srcRegIdx(int i) const
Returns the logical register index of the i'th source register.
Definition: dyn_inst.hh:692
RegId * _flatDestIdx
Definition: dyn_inst.hh:222
Fault writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable) override
Definition: dyn_inst.cc:423
uint8_t * _readySrcIdx
Definition: dyn_inst.hh:236
void clearInIQ()
Sets this instruction as a entry the IQ.
Definition: dyn_inst.hh:796
void setSerializeBefore()
Temporarily sets this instruction as a serialize before instruction.
Definition: dyn_inst.hh:639
void clearHtmTransactionalState()
Definition: dyn_inst.hh:625
void setTid(ThreadID tid)
Sets the thread id.
Definition: dyn_inst.hh:917
bool readyToIssue() const
Returns whether or not this instruction is ready to issue.
Definition: dyn_inst.hh:745
void translationCompleted(bool f)
Definition: dyn_inst.hh:418
bool isLoad() const
Definition: dyn_inst.hh:540
uint64_t htmDepth
Definition: dyn_inst.hh:982
@ LsqEntry
Instruction is in the ROB.
Definition: dyn_inst.hh:147
@ ThreadsyncWait
Is a blocking instruction.
Definition: dyn_inst.hh:165
@ Committed
Instruction has reached commit.
Definition: dyn_inst.hh:155
@ Completed
Instruction is in the LSQ.
Definition: dyn_inst.hh:148
@ SerializeHandled
Needs to serialize instructions behind it.
Definition: dyn_inst.hh:169
@ PinnedRegsRenamed
Instruction is squashed in the ROB.
Definition: dyn_inst.hh:160
@ NumStatus
Serialization has been handled.
Definition: dyn_inst.hh:170
@ Squashed
Instruction has committed.
Definition: dyn_inst.hh:156
@ PinnedRegsWritten
Pinned registers are renamed.
Definition: dyn_inst.hh:161
@ Executed
Instruction has issued.
Definition: dyn_inst.hh:152
@ SerializeBefore
Is a thread synchronization instruction.
Definition: dyn_inst.hh:166
@ SerializeAfter
Needs to serialize on instructions ahead of it.
Definition: dyn_inst.hh:168
@ PinnedRegsSquashDone
Pinned registers are written back.
Definition: dyn_inst.hh:162
@ CanCommit
Instruction has executed.
Definition: dyn_inst.hh:153
@ Issued
Instruction can issue and execute.
Definition: dyn_inst.hh:151
@ BlockingInst
Is a recover instruction.
Definition: dyn_inst.hh:164
@ SquashedInLSQ
Instruction is squashed in the IQ.
Definition: dyn_inst.hh:158
@ AtCommit
Instruction can commit.
Definition: dyn_inst.hh:154
@ SquashedInIQ
Instruction is squashed.
Definition: dyn_inst.hh:157
@ CanIssue
Instruction has its result.
Definition: dyn_inst.hh:150
@ SquashedInROB
Instruction is squashed in the LSQ.
Definition: dyn_inst.hh:159
@ RecoverInst
Regs pinning status updated after squash.
Definition: dyn_inst.hh:163
@ RobEntry
Instruction is in the IQ.
Definition: dyn_inst.hh:146
@ ResultReady
Instruction has completed.
Definition: dyn_inst.hh:149
void renamedSrcIdx(int idx, PhysRegIdPtr phys_reg_id)
Definition: dyn_inst.hh:296
Fault completeAcc(PacketPtr pkt)
Completes the access.
Definition: dyn_inst.cc:373
Fault fault
The kind of fault this instruction has generated.
Definition: dyn_inst.hh:137
std::vector< short > _destMiscRegIdx
Indexes of the destination misc.
Definition: dyn_inst.hh:215
void setResult(const RegClass &reg_class, T &&t)
Pushes a result onto the instResult queue.
Definition: dyn_inst.hh:715
bool isMemRef() const
Definition: dyn_inst.hh:539
ssize_t lqIdx
Load queue index.
Definition: dyn_inst.hh:349
bool strictlyOrdered() const
Is this instruction's memory access strictly ordered?
Definition: dyn_inst.hh:927
bool readPredicate() const override
Definition: dyn_inst.hh:892
void getRegOperand(const StaticInst *si, int idx, void *val) override
Definition: dyn_inst.hh:1122
bool isFirstMicroop() const
Definition: dyn_inst.hh:580
bool isInstPrefetch() const
Definition: dyn_inst.hh:545
std::unique_ptr< PCStateBase > pc
PC state for this instruction.
Definition: dyn_inst.hh:206
ThreadID threadNumber
The thread this instruction is from.
Definition: dyn_inst.hh:316
std::bitset< MaxFlags > instFlags
Definition: dyn_inst.hh:194
void setThreadState(ThreadState *state)
Sets the pointer to the thread state.
Definition: dyn_inst.hh:920
bool readySrcIdx(int idx) const
Definition: dyn_inst.hh:302
LSQ::LSQRequest * savedRequest
Saved memory request (needed when the DTB address translation is delayed due to a hw page table walk)...
Definition: dyn_inst.hh:362
void setRegOperand(const StaticInst *si, int idx, const void *val) override
Definition: dyn_inst.hh:1150
bool isDataPrefetch() const
Definition: dyn_inst.hh:546
bool isSquashedInROB() const
Returns whether or not this instruction is squashed in the ROB.
Definition: dyn_inst.hh:841
RegVal readMiscReg(int misc_reg) override
Reads a misc.
Definition: dyn_inst.hh:1007
void updateMiscRegs()
Called at the commit stage to update the misc.
Definition: dyn_inst.hh:1057
bool isPinnedRegsRenamed() const
Returns whether pinned registers are renamed.
Definition: dyn_inst.hh:844
void setStCondFailures(unsigned int sc_failures) override
Sets the number of consecutive store conditional failures.
Definition: dyn_inst.hh:951
bool isReadBarrier() const
Definition: dyn_inst.hh:570
void strictlyOrdered(bool so)
Definition: dyn_inst.hh:928
std::unique_ptr< PCStateBase > branchTarget() const
Returns the branch target address.
Definition: dyn_inst.hh:671
bool isLastMicroop() const
Definition: dyn_inst.hh:579
Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override
Definition: dyn_inst.cc:435
RegVal getRegOperand(const StaticInst *si, int idx) override
Definition: dyn_inst.hh:1113
ContextID contextId() const
Read this context's system-wide ID.
Definition: dyn_inst.hh:497
PhysRegIdPtr renamedSrcIdx(int idx) const
Definition: dyn_inst.hh:290
void mwaitAtomic(gem5::ThreadContext *tc) override
Definition: dyn_inst.hh:969
size_t numDestRegs() const
Returns the number of destination registers.
Definition: dyn_inst.hh:680
std::queue< InstResult > instResult
The result of the instruction; assumes an instruction can have many destination registers.
Definition: dyn_inst.hh:203
void setSerializeHandled()
Sets the serialization part of this instruction as handled.
Definition: dyn_inst.hh:657
void setExecuted()
Sets this instruction as executed.
Definition: dyn_inst.hh:760
bool isUnverifiable() const
Definition: dyn_inst.hh:574
uint64_t newHtmTransactionUid() const override
Definition: dyn_inst.hh:595
void renameDestReg(int idx, PhysRegIdPtr renamed_dest, PhysRegIdPtr previous_rename)
Renames a destination register to a physical register.
Definition: dyn_inst.hh:462
bool isFullMemBarrier() const
Definition: dyn_inst.hh:569
bool isCall() const
Definition: dyn_inst.hh:551
bool possibleLoadViolation() const
True if this address was found to match a previous load and they issued out of order.
Definition: dyn_inst.hh:426
uint8_t resultSize()
Return the size of the instResult queue.
Definition: dyn_inst.hh:695
void dump()
Dumps out contents of this BaseDynInst.
Definition: dyn_inst.cc:278
bool isHtmStop() const
Definition: dyn_inst.hh:583
void setInROB()
Sets this instruction as a entry the ROB.
Definition: dyn_inst.hh:829
bool isSquashedInIQ() const
Returns whether or not this instruction is squashed in the IQ.
Definition: dyn_inst.hh:805
BaseCPU * getCpuPtr()
Definition: dyn_inst.hh:131
void setResultReady()
Marks the result as ready.
Definition: dyn_inst.hh:736
const StaticInstPtr staticInst
The StaticInst used by this BaseDynInst.
Definition: dyn_inst.hh:126
bool isTranslationDelayed() const
Returns true if the DTB address translation is being delayed due to a hw page table walk.
Definition: dyn_inst.hh:448
void setSerializeAfter()
Temporarily sets this instruction as a serialize after instruction.
Definition: dyn_inst.hh:648
void setSquashedInROB()
Sets this instruction as squashed in the ROB.
Definition: dyn_inst.hh:838
void setNotAnInst()
Definition: dyn_inst.hh:381
void setPinnedRegsWritten()
Sets destination registers as written.
Definition: dyn_inst.hh:860
bool effAddrValid() const
Is the effective virtual address valid.
Definition: dyn_inst.hh:373
bool isSerializing() const
Definition: dyn_inst.hh:557
void setRegOperand(const StaticInst *si, int idx, RegVal val) override
Definition: dyn_inst.hh:1140
bool isNop() const
Definition: dyn_inst.hh:538
void setSquashed()
Sets this instruction as squashed.
Definition: dyn_inst.cc:314
bool isSerializeAfter() const
Definition: dyn_inst.hh:564
uint64_t getHtmTransactionalDepth() const override
Definition: dyn_inst.hh:608
Fault getFault() const
Returns the fault type.
Definition: dyn_inst.hh:500
LSQUnit::SQIterator sqIt
Definition: dyn_inst.hh:354
void translationStarted(bool f)
Definition: dyn_inst.hh:410
bool isTempSerializeBefore()
Checks if this serializeBefore is only temporarily set.
Definition: dyn_inst.hh:645
bool isSerializeHandled()
Checks if the serialization part of this instruction has been handled.
Definition: dyn_inst.hh:664
bool isInROB() const
Returns whether or not this instruction is in the ROB.
Definition: dyn_inst.hh:835
bool isWriteBarrier() const
Definition: dyn_inst.hh:571
bool isInIQ() const
Returns whether or not this instruction has issued.
Definition: dyn_inst.hh:799
bool hitExternalSnoop() const
True if the address hit a external snoop while sitting in the LSQ.
Definition: dyn_inst.hh:440
const RegId & flattenedDestIdx(int idx) const
Definition: dyn_inst.hh:245
void recordResult(bool f)
Records changes to result?
Definition: dyn_inst.hh:370
bool isStore() const
Definition: dyn_inst.hh:541
void effAddrValid(bool b)
Definition: dyn_inst.hh:374
void setPredicate(bool val) override
Definition: dyn_inst.hh:895
void setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
Sets a misc.
Definition: dyn_inst.hh:1048
void setSquashedInIQ()
Sets this instruction as squashed in the IQ.
Definition: dyn_inst.hh:802
void pcState(const PCStateBase &val) override
Set the PC state of this instruction.
Definition: dyn_inst.hh:890
Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable) override
Definition: dyn_inst.cc:402
bool isResultReady() const
Returns whether or not the result is ready.
Definition: dyn_inst.hh:739
void armMonitor(Addr address) override
Definition: dyn_inst.hh:959
ListIt & getInstListIt()
Returns iterator to this instruction in the list of all insts.
Definition: dyn_inst.hh:936
CPU * cpu
Pointer to the Impl's CPU object.
Definition: dyn_inst.hh:129
void trap(const Fault &fault)
Traps to handle specified fault.
Definition: dyn_inst.cc:396
void hitExternalSnoop(bool f)
Definition: dyn_inst.hh:441
bool isInLSQ() const
Returns whether or not this instruction is in the LSQ.
Definition: dyn_inst.hh:817
Addr physEffAddr
The effective physical address.
Definition: dyn_inst.hh:337
AddressMonitor * getAddrMonitor() override
Definition: dyn_inst.hh:974
int cpuId() const
Read this CPU's ID.
Definition: dyn_inst.hh:488
void demapPage(Addr vaddr, uint64_t asn) override
Invalidate a page in the DTLB and ITLB.
Definition: dyn_inst.hh:391
void possibleLoadViolation(bool f)
Definition: dyn_inst.hh:431
bool isIssued() const
Returns whether or not this instruction has issued.
Definition: dyn_inst.hh:754
trace::InstRecord * traceData
InstRecord that tracks this instructions.
Definition: dyn_inst.hh:140
bool isSquashedInLSQ() const
Returns whether or not this instruction is squashed in the LSQ.
Definition: dyn_inst.hh:823
void setCompleted()
Sets this instruction as completed.
Definition: dyn_inst.hh:730
Fault execute()
Executes the instruction.
Definition: dyn_inst.cc:339
ListIt instListIt
Iterator pointing to this BaseDynInst in the list of all insts.
Definition: dyn_inst.hh:319
bool isPinnedRegsSquashDone() const
Return whether dest registers' pinning status updated after squash.
Definition: dyn_inst.hh:869
bool isHtmCmd() const
Definition: dyn_inst.hh:585
PhysRegIdPtr renamedDestIdx(int idx) const
Definition: dyn_inst.hh:261
void setCanCommit()
Sets this instruction as ready to commit.
Definition: dyn_inst.hh:766
unsigned int readStCondFailures() const override
Returns the number of consecutive store conditional failures.
Definition: dyn_inst.hh:944
bool isTempSerializeAfter()
Checks if this serializeAfter is only temporarily set.
Definition: dyn_inst.hh:654
void clearIssued()
Clears this instruction as being issued.
Definition: dyn_inst.hh:757
bool isSerializeBefore() const
Definition: dyn_inst.hh:559
uint64_t getHtmTransactionUid() const override
Definition: dyn_inst.hh:588
uint64_t htmUid
Definition: dyn_inst.hh:981
bool isControl() const
Definition: dyn_inst.hh:550
bool readyToCommit() const
Returns whether or not this instruction is ready to commit.
Definition: dyn_inst.hh:772
std::bitset< NumStatus > status
The status of this BaseDynInst.
Definition: dyn_inst.hh:197
void setPredTaken(bool predicted_taken)
Definition: dyn_inst.hh:521
void setPinnedRegsRenamed()
Sets the destination registers as renamed.
Definition: dyn_inst.hh:848
void setInstListIt(ListIt _instListIt)
Sets iterator for this instruction in the list of all insts.
Definition: dyn_inst.hh:939
bool isInteger() const
Definition: dyn_inst.hh:547
void prevDestIdx(int idx, PhysRegIdPtr phys_reg_id)
Definition: dyn_inst.hh:283
bool isDelayedCommit() const
Definition: dyn_inst.hh:578
LSQUnit::LQIterator lqIt
Definition: dyn_inst.hh:350
bool isMacroop() const
Definition: dyn_inst.hh:576
void setPinnedRegsSquashDone()
Sets dest registers' status updated after squash.
Definition: dyn_inst.hh:876
DynInst(const StaticInstPtr &staticInst, const StaticInstPtr &macroop, InstSeqNum seq_num, CPU *cpu)
bool isCommitted() const
Returns whether or not this instruction is committed.
Definition: dyn_inst.hh:782
bool isSquashed() const
Returns whether or not this instruction is squashed.
Definition: dyn_inst.hh:788
bool isExecuted() const
Returns whether or not this instruction has executed.
Definition: dyn_inst.hh:763
bool mispredicted()
Returns whether the instruction mispredicted.
Definition: dyn_inst.hh:528
Fault initiateMemMgmtCmd(Request::Flags flags) override
Initiate a memory management command with no valid address.
Definition: dyn_inst.cc:413
bool isPinnedRegsWritten() const
Returns whether destination registers are written.
Definition: dyn_inst.hh:856
const RegId & destRegIdx(int i) const
Returns the logical register index of the i'th destination register.
Definition: dyn_inst.hh:689
void clearCanCommit()
Clears this instruction as being ready to commit.
Definition: dyn_inst.hh:769
bool memOpDone() const
Whether or not the memory operation is done.
Definition: dyn_inst.hh:377
void setRequest()
Assert this instruction has generated a memory request.
Definition: dyn_inst.hh:933
void setSquashedInLSQ()
Sets this instruction as squashed in the LSQ.
Definition: dyn_inst.hh:820
bool isNonSpeculative() const
Definition: dyn_inst.hh:572
PhysRegIdPtr prevDestIdx(int idx) const
Definition: dyn_inst.hh:276
void setPredTarg(const PCStateBase &pred_pc)
Set the predicted target of this current instruction.
Definition: dyn_inst.hh:513
InstSeqNum seqNum
The sequence number of the instruction.
Definition: dyn_inst.hh:123
bool isHtmCancel() const
Definition: dyn_inst.hh:584
void clearInROB()
Sets this instruction as a entry the ROB.
Definition: dyn_inst.hh:832
void markSrcRegReady()
Records that one of the source registers is ready.
Definition: dyn_inst.cc:296
bool isSyscall() const
Definition: dyn_inst.hh:575
size_t numSrcRegs() const
Returns the number of source registers.
Definition: dyn_inst.hh:677
void removeInLSQ()
Sets this instruction as a entry the LSQ.
Definition: dyn_inst.hh:814
void flattenedDestIdx(int idx, const RegId &reg_id)
Definition: dyn_inst.hh:253
ssize_t sqIdx
Store queue index.
Definition: dyn_inst.hh:353
void renameSrcReg(int idx, PhysRegIdPtr renamed_src)
Renames a source logical register to the physical register which has/will produce that logical regist...
Definition: dyn_inst.hh:476
const StaticInstPtr macroop
The Macroop if one exists.
Definition: dyn_inst.hh:326
bool translationStarted() const
True if the DTB address translation has started.
Definition: dyn_inst.hh:409
bool isReturn() const
Definition: dyn_inst.hh:552
void setMiscReg(int misc_reg, RegVal val) override
Sets a misc.
Definition: dyn_inst.hh:1016
bool isFloating() const
Definition: dyn_inst.hh:548
void setInLSQ()
Sets this instruction as a entry the LSQ.
Definition: dyn_inst.hh:811
bool readPredTaken()
Returns whether the instruction was predicted taken or not.
Definition: dyn_inst.hh:518
PhysRegIdPtr * _destIdx
Definition: dyn_inst.hh:226
bool mwait(PacketPtr pkt) override
Definition: dyn_inst.hh:964
void renamedDestIdx(int idx, PhysRegIdPtr phys_reg_id)
Definition: dyn_inst.hh:268
size_t numSrcs() const
Definition: dyn_inst.hh:239
void readySrcIdx(int idx, bool ready)
Definition: dyn_inst.hh:309
void setMemAccPredicate(bool val) override
Definition: dyn_inst.hh:911
Fault initiateAcc()
Initiates the access.
Definition: dyn_inst.cc:356
bool readMemAccPredicate() const override
Definition: dyn_inst.hh:905
bool isAtomic() const
Definition: dyn_inst.hh:542
void clearSerializeBefore()
Clears the serializeBefore part of this instruction.
Definition: dyn_inst.hh:642
void * getWritableRegOperand(const StaticInst *si, int idx) override
Definition: dyn_inst.hh:1131
void setInIQ()
Sets this instruction as a entry the IQ.
Definition: dyn_inst.hh:793
bool isVector() const
Definition: dyn_inst.hh:549
bool inHtmTransactionalState() const override
Definition: dyn_inst.hh:602
bool translationCompleted() const
True if the DTB address translation has completed.
Definition: dyn_inst.hh:414
void setCanIssue()
Sets this instruction as ready to issue.
Definition: dyn_inst.hh:742
size_t numDests() const
Definition: dyn_inst.hh:240
const PCStateBase & readPredTarg()
Definition: dyn_inst.hh:515
void setHtmTransactionalState(uint64_t htm_uid, uint64_t htm_depth)
Definition: dyn_inst.hh:617
void setCommitted()
Sets this instruction as committed.
Definition: dyn_inst.hh:779
PhysRegIdPtr * _srcIdx
Definition: dyn_inst.hh:233
bool isQuiesce() const
Definition: dyn_inst.hh:573
bool notAnInst() const
Definition: dyn_inst.hh:380
std::vector< RegVal > _destMiscRegVal
Values to be written to the destination misc.
Definition: dyn_inst.hh:209
OpClass opClass() const
Returns the opclass of this instruction.
Definition: dyn_inst.hh:667
Addr effAddr
The effective virtual address (lds & stores only).
Definition: dyn_inst.hh:334
InstResult popResult(InstResult dflt=InstResult())
Pops a result off the instResult queue.
Definition: dyn_inst.hh:701
uint32_t socketId() const
Read this CPU's Socket ID.
Definition: dyn_inst.hh:491
CircularQueue< LQEntry >::iterator LQIterator
Definition: lsq_unit.hh:564
CircularQueue< SQEntry >::iterator SQIterator
Definition: lsq_unit.hh:565
Memory operation metadata.
Definition: lsq.hh:190
Class that has various thread state, such as the status, the current instruction being processed,...
Definition: thread_state.hh:67
gem5::ThreadContext * getTC()
Returns a pointer to the TC of this thread.
void setPredicate(bool val)
Definition: insttracer.hh:258
STL list class.
Definition: stl.hh:51
std::unique_ptr< AtomicOpFunctor > AtomicOpFunctorPtr
Definition: amo.hh:242
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
constexpr void replaceBits(T &val, unsigned first, unsigned last, B bit_val)
A convenience function to replace bits first to last of val with bit_val in place.
Definition: bitfield.hh:197
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
atomic_var_t state
Definition: helpers.cc:188
uint8_t flags
Definition: helpers.cc:66
Bitfield< 7 > b
Definition: misc_types.hh:388
Bitfield< 7 > i
Definition: misc_types.hh:67
Bitfield< 6 > si
Definition: misc_types.hh:831
Bitfield< 12, 11 > set
Definition: misc_types.hh:709
Bitfield< 28 > so
Definition: misc.hh:59
Bitfield< 51 > t
Definition: pagetable.hh:56
Bitfield< 56 > f
Definition: pagetable.hh:53
Bitfield< 5, 3 > reg
Definition: types.hh:92
Bitfield< 63 > val
Definition: misc.hh:776
Bitfield< 3 > addr
Definition: types.hh:84
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:109
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:235
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
uint16_t RegIndex
Definition: types.hh:176
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
uint64_t Tick
Tick count type.
Definition: types.hh:58
uint16_t RequestorID
Definition: request.hh:95
int ContextID
Globally unique thread context ID.
Definition: types.hh:239
uint64_t RegVal
Definition: types.hh:173
constexpr decltype(nullptr) NoFault
Definition: types.hh:253
uint64_t InstSeqNum
Definition: inst_seq.hh:40
RegClassType
Enumerate the classes of registers.
Definition: reg_class.hh:59
@ InvalidRegClass
Definition: reg_class.hh:69
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:68
Classes for managing reference counted objects.
unsigned storeCondFailures
ContextID contextId() const
Definition: thread_state.hh:63
PhysRegIdPtr * prevDestIdx
Definition: dyn_inst.hh:92
PhysRegIdPtr * srcIdx
Definition: dyn_inst.hh:93
PhysRegIdPtr * destIdx
Definition: dyn_inst.hh:91

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