gem5  v21.1.0.2
dyn_inst.hh
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41 
42 #ifndef __CPU_O3_DYN_INST_HH__
43 #define __CPU_O3_DYN_INST_HH__
44 
45 #include <algorithm>
46 #include <array>
47 #include <deque>
48 #include <list>
49 #include <string>
50 
51 #include "base/refcnt.hh"
52 #include "base/trace.hh"
53 #include "config/the_isa.hh"
54 #include "cpu/checker/cpu.hh"
55 #include "cpu/exec_context.hh"
56 #include "cpu/exetrace.hh"
57 #include "cpu/inst_res.hh"
58 #include "cpu/inst_seq.hh"
59 #include "cpu/o3/cpu.hh"
60 #include "cpu/o3/dyn_inst_ptr.hh"
61 #include "cpu/o3/lsq_unit.hh"
62 #include "cpu/op_class.hh"
63 #include "cpu/reg_class.hh"
64 #include "cpu/static_inst.hh"
65 #include "cpu/translation.hh"
66 #include "debug/HtmCpu.hh"
67 
68 namespace gem5
69 {
70 
71 class Packet;
72 
73 namespace o3
74 {
75 
76 class DynInst : public ExecContext, public RefCounted
77 {
78  public:
79  // The list of instructions iterator type.
81 
85  InstSeqNum seq_num, CPU *cpu);
86 
88  DynInst(const StaticInstPtr &_staticInst, const StaticInstPtr &_macroop);
89 
90  ~DynInst();
91 
93  Fault execute();
94 
97 
100 
103 
106 
108  CPU *cpu = nullptr;
109 
110  BaseCPU *getCpuPtr() { return cpu; }
111 
113  ThreadState *thread = nullptr;
114 
117 
120 
121  protected:
122  enum Status
123  {
150  };
151 
152  enum Flags
153  {
169  };
170 
171  private:
172  /* An amalgamation of a lot of boolean values into one */
173  std::bitset<MaxFlags> instFlags;
174 
176  std::bitset<NumStatus> status;
177 
178  protected:
182  std::queue<InstResult> instResult;
183 
186 
189 
195 
203  struct Regs
204  {
205  private:
206  size_t _numSrcs;
207  size_t _numDests;
208 
209  using BackingStorePtr = std::unique_ptr<uint8_t[]>;
210  using BufCursor = BackingStorePtr::pointer;
211 
213 
214  // Members should be ordered based on required alignment so that they
215  // can be allocated contiguously.
216 
217  // Flattened register index of the destination registers of this
218  // instruction.
220 
221  // Physical register index of the destination registers of this
222  // instruction.
224 
225  // Physical register index of the previous producers of the
226  // architected destinations.
228 
229  static inline size_t
230  bytesForDests(size_t num)
231  {
232  return (sizeof(RegId) + 2 * sizeof(PhysRegIdPtr)) * num;
233  }
234 
235  // Physical register index of the source registers of this instruction.
237 
238  // Whether or not the source register is ready, one bit per register.
239  uint8_t *_readySrcIdx;
240 
241  static inline size_t
242  bytesForSources(size_t num)
243  {
244  return sizeof(PhysRegIdPtr) * num +
245  sizeof(uint8_t) * ((num + 7) / 8);
246  }
247 
248  template <class T>
249  static inline void
250  allocate(T *&ptr, BufCursor &cur, size_t count)
251  {
252  ptr = new (cur) T[count];
253  cur += sizeof(T) * count;
254  }
255 
256  public:
257  size_t numSrcs() const { return _numSrcs; }
258  size_t numDests() const { return _numDests; }
259 
260  void
262  {
263  std::fill(_readySrcIdx, _readySrcIdx + (numSrcs() + 7) / 8, 0);
264  }
265 
266  Regs(size_t srcs, size_t dests) : _numSrcs(srcs), _numDests(dests),
267  buf(new uint8_t[bytesForSources(srcs) + bytesForDests(dests)])
268  {
269  BufCursor cur = buf.get();
270  allocate(_flatDestIdx, cur, dests);
271  allocate(_destIdx, cur, dests);
272  allocate(_prevDestIdx, cur, dests);
273  allocate(_srcIdx, cur, srcs);
274  allocate(_readySrcIdx, cur, (srcs + 7) / 8);
275 
276  init();
277  }
278 
279  // Returns the flattened register index of the idx'th destination
280  // register.
281  const RegId &
282  flattenedDestIdx(int idx) const
283  {
284  return _flatDestIdx[idx];
285  }
286 
287  // Flattens a destination architectural register index into a logical
288  // index.
289  void
290  flattenedDestIdx(int idx, const RegId &reg_id)
291  {
292  _flatDestIdx[idx] = reg_id;
293  }
294 
295  // Returns the physical register index of the idx'th destination
296  // register.
298  renamedDestIdx(int idx) const
299  {
300  return _destIdx[idx];
301  }
302 
303  // Set the renamed dest register id.
304  void
305  renamedDestIdx(int idx, PhysRegIdPtr phys_reg_id)
306  {
307  _destIdx[idx] = phys_reg_id;
308  }
309 
310  // Returns the physical register index of the previous physical
311  // register that remapped to the same logical register index.
313  prevDestIdx(int idx) const
314  {
315  return _prevDestIdx[idx];
316  }
317 
318  // Set the previous renamed dest register id.
319  void
320  prevDestIdx(int idx, PhysRegIdPtr phys_reg_id)
321  {
322  _prevDestIdx[idx] = phys_reg_id;
323  }
324 
325  // Returns the physical register index of the i'th source register.
327  renamedSrcIdx(int idx) const
328  {
329  return _srcIdx[idx];
330  }
331 
332  void
333  renamedSrcIdx(int idx, PhysRegIdPtr phys_reg_id)
334  {
335  _srcIdx[idx] = phys_reg_id;
336  }
337 
338  bool
339  readySrcIdx(int idx) const
340  {
341  uint8_t &byte = _readySrcIdx[idx / 8];
342  return bits(byte, idx % 8);
343  }
344 
345  void
346  readySrcIdx(int idx, bool ready)
347  {
348  uint8_t &byte = _readySrcIdx[idx / 8];
349  replaceBits(byte, idx % 8, ready ? 1 : 0);
350  }
351  };
352 
353  public:
355 
358 
361 
363 
365 
368 
370  uint8_t readyRegs = 0;
371 
372  public:
374 
376 
379 
381  unsigned memReqFlags = 0;
382 
384  unsigned effSize;
385 
387  uint8_t *memData = nullptr;
388 
390  ssize_t lqIdx = -1;
392 
394  ssize_t sqIdx = -1;
396 
397 
399 
404 
406  // Need a copy of main request pointer to verify on writes.
408 
409  public:
411  void recordResult(bool f) { instFlags[RecordResult] = f; }
412 
414  bool effAddrValid() const { return instFlags[EffAddrValid]; }
415  void effAddrValid(bool b) { instFlags[EffAddrValid] = b; }
416 
418  bool memOpDone() const { return instFlags[MemOpDone]; }
419  void memOpDone(bool f) { instFlags[MemOpDone] = f; }
420 
421  bool notAnInst() const { return instFlags[NotAnInst]; }
422  void setNotAnInst() { instFlags[NotAnInst] = true; }
423 
424 
426  //
427  // INSTRUCTION EXECUTION
428  //
430 
431  void
432  demapPage(Addr vaddr, uint64_t asn) override
433  {
434  cpu->demapPage(vaddr, asn);
435  }
436 
437  Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags,
438  const std::vector<bool> &byte_enable) override;
439 
440  Fault initiateHtmCmd(Request::Flags flags) override;
441 
442  Fault writeMem(uint8_t *data, unsigned size, Addr addr,
443  Request::Flags flags, uint64_t *res,
444  const std::vector<bool> &byte_enable) override;
445 
446  Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags,
447  AtomicOpFunctorPtr amo_op) override;
448 
452 
454  bool
456  {
458  }
460 
466  bool
468  {
470  }
471  void
473  {
475  }
476 
481  bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; }
483 
488  bool
490  {
491  return (translationStarted() && !translationCompleted());
492  }
493 
494  public:
495 #ifdef DEBUG
496  void dumpSNList();
497 #endif
498 
502  void
503  renameDestReg(int idx, PhysRegIdPtr renamed_dest,
504  PhysRegIdPtr previous_rename)
505  {
506  regs.renamedDestIdx(idx, renamed_dest);
507  regs.prevDestIdx(idx, previous_rename);
508  if (renamed_dest->isPinned())
510  }
511 
516  void
517  renameSrcReg(int idx, PhysRegIdPtr renamed_src)
518  {
519  regs.renamedSrcIdx(idx, renamed_src);
520  }
521 
523  void dump();
524 
526  void dump(std::string &outstring);
527 
529  int cpuId() const { return cpu->cpuId(); }
530 
532  uint32_t socketId() const { return cpu->socketId(); }
533 
536 
538  ContextID contextId() const { return thread->contextId(); }
539 
541  Fault getFault() const { return fault; }
544  Fault& getFault() { return fault; }
545 
551  bool doneTargCalc() { return false; }
552 
554  void setPredTarg(const TheISA::PCState &_predPC) { predPC = _predPC; }
555 
556  const TheISA::PCState &readPredTarg() { return predPC; }
557 
559  Addr predInstAddr() { return predPC.instAddr(); }
560 
562  Addr predNextInstAddr() { return predPC.nextInstAddr(); }
563 
565  Addr predMicroPC() { return predPC.microPC(); }
566 
568  bool readPredTaken() { return instFlags[PredTaken]; }
569 
570  void
571  setPredTaken(bool predicted_taken)
572  {
573  instFlags[PredTaken] = predicted_taken;
574  }
575 
577  bool
579  {
580  TheISA::PCState tempPC = pc;
581  staticInst->advancePC(tempPC);
582  return !(tempPC == predPC);
583  }
584 
585  //
586  // Instruction types. Forward checks to StaticInst object.
587  //
588  bool isNop() const { return staticInst->isNop(); }
589  bool isMemRef() const { return staticInst->isMemRef(); }
590  bool isLoad() const { return staticInst->isLoad(); }
591  bool isStore() const { return staticInst->isStore(); }
592  bool isAtomic() const { return staticInst->isAtomic(); }
593  bool isStoreConditional() const
594  { return staticInst->isStoreConditional(); }
595  bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
596  bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
597  bool isInteger() const { return staticInst->isInteger(); }
598  bool isFloating() const { return staticInst->isFloating(); }
599  bool isVector() const { return staticInst->isVector(); }
600  bool isControl() const { return staticInst->isControl(); }
601  bool isCall() const { return staticInst->isCall(); }
602  bool isReturn() const { return staticInst->isReturn(); }
603  bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
604  bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
605  bool isCondCtrl() const { return staticInst->isCondCtrl(); }
606  bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
607  bool isSerializing() const { return staticInst->isSerializing(); }
608  bool
610  {
612  }
613  bool
615  {
617  }
618  bool isSquashAfter() const { return staticInst->isSquashAfter(); }
619  bool isFullMemBarrier() const { return staticInst->isFullMemBarrier(); }
620  bool isReadBarrier() const { return staticInst->isReadBarrier(); }
621  bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
622  bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
623  bool isQuiesce() const { return staticInst->isQuiesce(); }
624  bool isUnverifiable() const { return staticInst->isUnverifiable(); }
625  bool isSyscall() const { return staticInst->isSyscall(); }
626  bool isMacroop() const { return staticInst->isMacroop(); }
627  bool isMicroop() const { return staticInst->isMicroop(); }
628  bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
629  bool isLastMicroop() const { return staticInst->isLastMicroop(); }
630  bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
631  // hardware transactional memory
632  bool isHtmStart() const { return staticInst->isHtmStart(); }
633  bool isHtmStop() const { return staticInst->isHtmStop(); }
634  bool isHtmCancel() const { return staticInst->isHtmCancel(); }
635  bool isHtmCmd() const { return staticInst->isHtmCmd(); }
636 
637  uint64_t
638  getHtmTransactionUid() const override
639  {
640  assert(instFlags[HtmFromTransaction]);
641  return this->htmUid;
642  }
643 
644  uint64_t
645  newHtmTransactionUid() const override
646  {
647  panic("Not yet implemented\n");
648  return 0;
649  }
650 
651  bool
652  inHtmTransactionalState() const override
653  {
655  }
656 
657  uint64_t
658  getHtmTransactionalDepth() const override
659  {
661  return this->htmDepth;
662  else
663  return 0;
664  }
665 
666  void
667  setHtmTransactionalState(uint64_t htm_uid, uint64_t htm_depth)
668  {
670  htmUid = htm_uid;
671  htmDepth = htm_depth;
672  }
673 
674  void
676  {
677  if (inHtmTransactionalState()) {
678  DPRINTF(HtmCpu,
679  "clearing instuction's transactional state htmUid=%u\n",
681 
683  htmUid = -1;
684  htmDepth = 0;
685  }
686  }
687 
690 
693 
696 
699 
702 
705 
708 
715 
717  OpClass opClass() const { return staticInst->opClass(); }
718 
721  branchTarget() const
722  {
723  return staticInst->branchTarget(pc);
724  }
725 
727  size_t numSrcRegs() const { return regs.numSrcs(); }
728 
730  size_t numDestRegs() const { return regs.numDests(); }
731 
732  // the following are used to track physical register usage
733  // for machines with separate int & FP reg files
734  int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
735  int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
736  int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); }
737  int8_t numVecDestRegs() const { return staticInst->numVecDestRegs(); }
738  int8_t
740  {
741  return staticInst->numVecElemDestRegs();
742  }
743  int8_t
745  {
746  return staticInst->numVecPredDestRegs();
747  }
748 
750  const RegId& destRegIdx(int i) const { return staticInst->destRegIdx(i); }
751 
753  const RegId& srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
754 
756  uint8_t resultSize() { return instResult.size(); }
757 
761  InstResult
763  {
764  if (!instResult.empty()) {
765  InstResult t = instResult.front();
766  instResult.pop();
767  return t;
768  }
769  return dflt;
770  }
771 
775  template<typename T>
776  void
778  {
779  if (instFlags[RecordResult]) {
780  instResult.push(InstResult(std::forward<T>(t),
782  }
783  }
784 
786  template<typename T>
787  void
789  {
790  if (instFlags[RecordResult]) {
791  instResult.push(InstResult(std::forward<T>(t),
793  }
794  }
795 
797  template<typename T>
798  void
800  {
801  if (instFlags[RecordResult]) {
802  instResult.push(InstResult(std::forward<T>(t),
804  }
805  }
806 
808  template<typename T>
809  void
811  {
812  if (instFlags[RecordResult]) {
813  instResult.push(InstResult(std::forward<T>(t),
815  }
816  }
820  void markSrcRegReady();
821 
823  void markSrcRegReady(RegIndex src_idx);
824 
826  void setCompleted() { status.set(Completed); }
827 
829  bool isCompleted() const { return status[Completed]; }
830 
833 
835  bool isResultReady() const { return status[ResultReady]; }
836 
838  void setCanIssue() { status.set(CanIssue); }
839 
841  bool readyToIssue() const { return status[CanIssue]; }
842 
844  void clearCanIssue() { status.reset(CanIssue); }
845 
847  void setIssued() { status.set(Issued); }
848 
850  bool isIssued() const { return status[Issued]; }
851 
853  void clearIssued() { status.reset(Issued); }
854 
856  void setExecuted() { status.set(Executed); }
857 
859  bool isExecuted() const { return status[Executed]; }
860 
862  void setCanCommit() { status.set(CanCommit); }
863 
865  void clearCanCommit() { status.reset(CanCommit); }
866 
868  bool readyToCommit() const { return status[CanCommit]; }
869 
870  void setAtCommit() { status.set(AtCommit); }
871 
872  bool isAtCommit() { return status[AtCommit]; }
873 
875  void setCommitted() { status.set(Committed); }
876 
878  bool isCommitted() const { return status[Committed]; }
879 
881  void setSquashed();
882 
884  bool isSquashed() const { return status[Squashed]; }
885 
886  //Instruction Queue Entry
887  //-----------------------
889  void setInIQ() { status.set(IqEntry); }
890 
892  void clearInIQ() { status.reset(IqEntry); }
893 
895  bool isInIQ() const { return status[IqEntry]; }
896 
899 
901  bool isSquashedInIQ() const { return status[SquashedInIQ]; }
902 
903 
904  //Load / Store Queue Functions
905  //-----------------------
907  void setInLSQ() { status.set(LsqEntry); }
908 
910  void removeInLSQ() { status.reset(LsqEntry); }
911 
913  bool isInLSQ() const { return status[LsqEntry]; }
914 
917 
919  bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
920 
921 
922  //Reorder Buffer Functions
923  //-----------------------
925  void setInROB() { status.set(RobEntry); }
926 
928  void clearInROB() { status.reset(RobEntry); }
929 
931  bool isInROB() const { return status[RobEntry]; }
932 
935 
937  bool isSquashedInROB() const { return status[SquashedInROB]; }
938 
940  bool isPinnedRegsRenamed() const { return status[PinnedRegsRenamed]; }
941 
943  void
945  {
946  assert(!status[PinnedRegsSquashDone]);
947  assert(!status[PinnedRegsWritten]);
949  }
950 
952  bool isPinnedRegsWritten() const { return status[PinnedRegsWritten]; }
953 
955  void
957  {
958  assert(!status[PinnedRegsSquashDone]);
959  assert(status[PinnedRegsRenamed]);
961  }
962 
964  bool
966  {
968  }
969 
971  void
973  {
974  assert(!status[PinnedRegsSquashDone]);
976  }
977 
979  TheISA::PCState pcState() const override { return pc; }
980 
982  void pcState(const TheISA::PCState &val) override { pc = val; }
983 
985  Addr instAddr() const { return pc.instAddr(); }
986 
988  Addr nextInstAddr() const { return pc.nextInstAddr(); }
989 
991  Addr microPC() const { return pc.microPC(); }
992 
993  bool readPredicate() const override { return instFlags[Predicate]; }
994 
995  void
996  setPredicate(bool val) override
997  {
999 
1000  if (traceData) {
1002  }
1003  }
1004 
1005  bool
1006  readMemAccPredicate() const override
1007  {
1008  return instFlags[MemAccPredicate];
1009  }
1010 
1011  void
1012  setMemAccPredicate(bool val) override
1013  {
1015  }
1016 
1018  void setTid(ThreadID tid) { threadNumber = tid; }
1019 
1021  void setThreadState(ThreadState *state) { thread = state; }
1022 
1024  gem5::ThreadContext *tcBase() const override { return thread->getTC(); }
1025 
1026  public:
1028  bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; }
1030 
1032  bool hasRequest() const { return instFlags[ReqMade]; }
1034  void setRequest() { instFlags[ReqMade] = true; }
1035 
1038 
1040  void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
1041 
1042  public:
1044  unsigned int
1045  readStCondFailures() const override
1046  {
1047  return thread->storeCondFailures;
1048  }
1049 
1051  void
1052  setStCondFailures(unsigned int sc_failures) override
1053  {
1054  thread->storeCondFailures = sc_failures;
1055  }
1056 
1057  public:
1058  // monitor/mwait funtions
1059  void
1060  armMonitor(Addr address) override
1061  {
1062  cpu->armMonitor(threadNumber, address);
1063  }
1064  bool
1065  mwait(PacketPtr pkt) override
1066  {
1067  return cpu->mwait(threadNumber, pkt);
1068  }
1069  void
1071  {
1072  return cpu->mwaitAtomic(threadNumber, tc, cpu->mmu);
1073  }
1074  AddressMonitor *
1075  getAddrMonitor() override
1076  {
1078  }
1079 
1080  private:
1081  // hardware transactional memory
1082  uint64_t htmUid = -1;
1083  uint64_t htmDepth = 0;
1084 
1085  public:
1086 #if TRACING_ON
1087  // Value -1 indicates that particular phase
1088  // hasn't happened (yet).
1090  Tick fetchTick = -1; // instruction fetch is completed.
1091  int32_t decodeTick = -1; // instruction enters decode phase
1092  int32_t renameTick = -1; // instruction enters rename phase
1093  int32_t dispatchTick = -1;
1094  int32_t issueTick = -1;
1095  int32_t completeTick = -1;
1096  int32_t commitTick = -1;
1097  int32_t storeTick = -1;
1098 #endif
1099 
1100  /* Values used by LoadToUse stat */
1103 
1107  RegVal
1108  readMiscReg(int misc_reg) override
1109  {
1110  return this->cpu->readMiscReg(misc_reg, this->threadNumber);
1111  }
1112 
1116  void
1117  setMiscReg(int misc_reg, RegVal val) override
1118  {
1125  for (auto &idx: _destMiscRegIdx) {
1126  if (idx == misc_reg)
1127  return;
1128  }
1129 
1130  _destMiscRegIdx.push_back(misc_reg);
1131  _destMiscRegVal.push_back(val);
1132  }
1133 
1137  RegVal
1138  readMiscRegOperand(const StaticInst *si, int idx) override
1139  {
1140  const RegId& reg = si->srcRegIdx(idx);
1141  assert(reg.is(MiscRegClass));
1142  return this->cpu->readMiscReg(reg.index(), this->threadNumber);
1143  }
1144 
1148  void
1149  setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
1150  {
1151  const RegId& reg = si->destRegIdx(idx);
1152  assert(reg.is(MiscRegClass));
1153  setMiscReg(reg.index(), val);
1154  }
1155 
1157  void
1159  {
1160  // @todo: Pretty convoluted way to avoid squashing from happening when
1161  // using the TC during an instruction's execution (specifically for
1162  // instructions that have side-effects that use the TC). Fix this.
1163  // See cpu/o3/dyn_inst_impl.hh.
1164  bool no_squash_from_TC = this->thread->noSquashFromTC;
1165  this->thread->noSquashFromTC = true;
1166 
1167  for (int i = 0; i < _destMiscRegIdx.size(); i++)
1168  this->cpu->setMiscReg(
1169  _destMiscRegIdx[i], _destMiscRegVal[i], this->threadNumber);
1170 
1171  this->thread->noSquashFromTC = no_squash_from_TC;
1172  }
1173 
1174  void
1176  {
1177 
1178  for (int idx = 0; idx < this->numDestRegs(); idx++) {
1179  PhysRegIdPtr prev_phys_reg = this->regs.prevDestIdx(idx);
1180  const RegId& original_dest_reg = this->staticInst->destRegIdx(idx);
1181  switch (original_dest_reg.classValue()) {
1182  case IntRegClass:
1183  this->setIntRegOperand(this->staticInst.get(), idx,
1184  this->cpu->readIntReg(prev_phys_reg));
1185  break;
1186  case FloatRegClass:
1187  this->setFloatRegOperandBits(this->staticInst.get(), idx,
1188  this->cpu->readFloatReg(prev_phys_reg));
1189  break;
1190  case VecRegClass:
1191  this->setVecRegOperand(this->staticInst.get(), idx,
1192  this->cpu->readVecReg(prev_phys_reg));
1193  break;
1194  case VecElemClass:
1195  this->setVecElemOperand(this->staticInst.get(), idx,
1196  this->cpu->readVecElem(prev_phys_reg));
1197  break;
1198  case VecPredRegClass:
1199  this->setVecPredRegOperand(this->staticInst.get(), idx,
1200  this->cpu->readVecPredReg(prev_phys_reg));
1201  break;
1202  case CCRegClass:
1203  this->setCCRegOperand(this->staticInst.get(), idx,
1204  this->cpu->readCCReg(prev_phys_reg));
1205  break;
1206  case MiscRegClass:
1207  // no need to forward misc reg values
1208  break;
1209  default:
1210  panic("Unknown register class: %d",
1211  (int)original_dest_reg.classValue());
1212  }
1213  }
1214  }
1216  void trap(const Fault &fault);
1217 
1218  public:
1219 
1220  // The register accessor methods provide the index of the
1221  // instruction's operand (e.g., 0 or 1), not the architectural
1222  // register index, to simplify the implementation of register
1223  // renaming. We find the architectural register index by indexing
1224  // into the instruction's own operand index table. Note that a
1225  // raw pointer to the StaticInst is provided instead of a
1226  // ref-counted StaticInstPtr to redice overhead. This is fine as
1227  // long as these methods don't copy the pointer into any long-term
1228  // storage (which is pretty hard to imagine they would have reason
1229  // to do).
1230 
1231  RegVal
1232  readIntRegOperand(const StaticInst *si, int idx) override
1233  {
1234  return this->cpu->readIntReg(this->regs.renamedSrcIdx(idx));
1235  }
1236 
1237  RegVal
1238  readFloatRegOperandBits(const StaticInst *si, int idx) override
1239  {
1240  return this->cpu->readFloatReg(this->regs.renamedSrcIdx(idx));
1241  }
1242 
1244  readVecRegOperand(const StaticInst *si, int idx) const override
1245  {
1246  return this->cpu->readVecReg(this->regs.renamedSrcIdx(idx));
1247  }
1248 
1253  getWritableVecRegOperand(const StaticInst *si, int idx) override
1254  {
1255  return this->cpu->getWritableVecReg(this->regs.renamedDestIdx(idx));
1256  }
1257 
1259  readVecElemOperand(const StaticInst *si, int idx) const override
1260  {
1261  return this->cpu->readVecElem(this->regs.renamedSrcIdx(idx));
1262  }
1263 
1265  readVecPredRegOperand(const StaticInst *si, int idx) const override
1266  {
1267  return this->cpu->readVecPredReg(this->regs.renamedSrcIdx(idx));
1268  }
1269 
1271  getWritableVecPredRegOperand(const StaticInst *si, int idx) override
1272  {
1273  return this->cpu->getWritableVecPredReg(
1274  this->regs.renamedDestIdx(idx));
1275  }
1276 
1277  RegVal
1278  readCCRegOperand(const StaticInst *si, int idx) override
1279  {
1280  return this->cpu->readCCReg(this->regs.renamedSrcIdx(idx));
1281  }
1282 
1286  void
1287  setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
1288  {
1289  this->cpu->setIntReg(this->regs.renamedDestIdx(idx), val);
1291  }
1292 
1293  void
1294  setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
1295  {
1296  this->cpu->setFloatReg(this->regs.renamedDestIdx(idx), val);
1298  }
1299 
1300  void
1301  setVecRegOperand(const StaticInst *si, int idx,
1302  const TheISA::VecRegContainer& val) override
1303  {
1304  this->cpu->setVecReg(this->regs.renamedDestIdx(idx), val);
1305  setVecResult(val);
1306  }
1307 
1308  void
1310  const TheISA::VecElem val) override
1311  {
1312  int reg_idx = idx;
1313  this->cpu->setVecElem(this->regs.renamedDestIdx(reg_idx), val);
1315  }
1316 
1317  void
1319  const TheISA::VecPredRegContainer& val) override
1320  {
1321  this->cpu->setVecPredReg(this->regs.renamedDestIdx(idx), val);
1323  }
1324 
1325  void
1326  setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
1327  {
1328  this->cpu->setCCReg(this->regs.renamedDestIdx(idx), val);
1330  }
1331 };
1332 
1333 } // namespace o3
1334 } // namespace gem5
1335 
1336 #endif // __CPU_O3_DYN_INST_HH__
gem5::o3::DynInst::getInstListIt
ListIt & getInstListIt()
Returns iterator to this instruction in the list of all insts.
Definition: dyn_inst.hh:1037
gem5::o3::DynInst::isInLSQ
bool isInLSQ() const
Returns whether or not this instruction is in the LSQ.
Definition: dyn_inst.hh:913
gem5::o3::DynInst::setSquashedInIQ
void setSquashedInIQ()
Sets this instruction as squashed in the IQ.
Definition: dyn_inst.hh:898
gem5::o3::DynInst::Regs::readySrcIdx
void readySrcIdx(int idx, bool ready)
Definition: dyn_inst.hh:346
gem5::o3::DynInst::Regs::_srcIdx
PhysRegIdPtr * _srcIdx
Definition: dyn_inst.hh:236
refcnt.hh
gem5::MipsISA::fill
fill
Definition: pra_constants.hh:57
gem5::VecElemClass
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:62
gem5::o3::DynInst::PinnedRegsRenamed
@ PinnedRegsRenamed
Instruction is squashed in the ROB.
Definition: dyn_inst.hh:139
gem5::o3::DynInst::PinnedRegsSquashDone
@ PinnedRegsSquashDone
Pinned registers are written back.
Definition: dyn_inst.hh:141
gem5::o3::DynInst::isMicroop
bool isMicroop() const
Definition: dyn_inst.hh:627
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:64
gem5::o3::DynInst::ThreadsyncWait
@ ThreadsyncWait
Is a blocking instruction.
Definition: dyn_inst.hh:144
gem5::o3::CPU::readVecElem
const TheISA::VecElem & readVecElem(PhysRegIdPtr reg_idx) const
Definition: cpu.cc:1176
gem5::BaseCPU::armMonitor
void armMonitor(ThreadID tid, Addr address)
Definition: base.cc:205
gem5::o3::LSQ::LSQRequest
Memory operation metadata.
Definition: lsq.hh:231
gem5::PhysRegId::isPinned
bool isPinned() const
Definition: reg_class.hh:290
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::o3::DynInst::setMiscRegOperand
void setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
Sets a misc.
Definition: dyn_inst.hh:1149
gem5::StaticInst::isMicroop
bool isMicroop() const
Definition: static_inst.hh:208
gem5::o3::CPU::setVecElem
void setVecElem(PhysRegIdPtr reg_idx, const TheISA::VecElem &val)
Definition: cpu.cc:1225
gem5::StaticInst::isWriteBarrier
bool isWriteBarrier() const
Definition: static_inst.hh:202
gem5::StaticInst::isSerializeBefore
bool isSerializeBefore() const
Definition: static_inst.hh:193
gem5::o3::DynInst::Squashed
@ Squashed
Instruction has committed.
Definition: dyn_inst.hh:135
gem5::o3::DynInst::setVecRegOperand
void setVecRegOperand(const StaticInst *si, int idx, const TheISA::VecRegContainer &val) override
Sets a destination vector register operand to a value.
Definition: dyn_inst.hh:1301
gem5::o3::DynInst::microPC
Addr microPC() const
Read the micro PC of this instruction.
Definition: dyn_inst.hh:991
gem5::o3::DynInst::initiateAcc
Fault initiateAcc()
Initiates the access.
Definition: dyn_inst.cc:245
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::o3::CPU::readCCReg
RegVal readCCReg(PhysRegIdPtr phys_reg)
Definition: cpu.cc:1197
gem5::o3::DynInst::setInIQ
void setInIQ()
Sets this instruction as a entry the IQ.
Definition: dyn_inst.hh:889
gem5::o3::DynInst::threadNumber
ThreadID threadNumber
The thread this instruction is from.
Definition: dyn_inst.hh:357
gem5::o3::DynInst::newHtmTransactionUid
uint64_t newHtmTransactionUid() const override
Definition: dyn_inst.hh:645
gem5::BaseCPU::mwaitAtomic
void mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseMMU *mmu)
Definition: base.cc:240
gem5::o3::DynInst::setPredTarg
void setPredTarg(const TheISA::PCState &_predPC)
Set the predicted target of this current instruction.
Definition: dyn_inst.hh:554
gem5::o3::DynInst::TranslationCompleted
@ TranslationCompleted
Definition: dyn_inst.hh:156
gem5::o3::CPU::mmu
BaseMMU * mmu
Definition: cpu.hh:112
gem5::ArmISA::VecPredRegContainer
VecPredReg::Container VecPredRegContainer
Definition: vec.hh:68
gem5::o3::DynInst::setCanCommit
void setCanCommit()
Sets this instruction as ready to commit.
Definition: dyn_inst.hh:862
op_class.hh
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::StaticInst::isNonSpeculative
bool isNonSpeculative() const
Definition: static_inst.hh:203
gem5::o3::DynInst::RecordResult
@ RecordResult
Definition: dyn_inst.hh:160
gem5::o3::DynInst::numSrcRegs
size_t numSrcRegs() const
Returns the number of source registers.
Definition: dyn_inst.hh:727
gem5::o3::DynInst::getCpuPtr
BaseCPU * getCpuPtr()
Definition: dyn_inst.hh:110
gem5::o3::DynInst::sqIt
LSQUnit::SQIterator sqIt
Definition: dyn_inst.hh:395
gem5::StaticInst::isQuiesce
bool isQuiesce() const
Definition: static_inst.hh:204
gem5::o3::DynInst::isCompleted
bool isCompleted() const
Returns whether or not this instruction is completed.
Definition: dyn_inst.hh:829
gem5::o3::DynInst::isMemRef
bool isMemRef() const
Definition: dyn_inst.hh:589
gem5::o3::DynInst::pc
TheISA::PCState pc
PC state for this instruction.
Definition: dyn_inst.hh:185
gem5::o3::DynInst::ListIt
std::list< DynInstPtr >::iterator ListIt
Definition: dyn_inst.hh:80
gem5::o3::DynInst::Regs::numSrcs
size_t numSrcs() const
Definition: dyn_inst.hh:257
gem5::o3::DynInst::socketId
uint32_t socketId() const
Read this CPU's Socket ID.
Definition: dyn_inst.hh:532
gem5::o3::DynInst::isControl
bool isControl() const
Definition: dyn_inst.hh:600
gem5::o3::DynInst::HtmFromTransaction
@ HtmFromTransaction
Definition: dyn_inst.hh:167
gem5::StaticInst::numCCDestRegs
int8_t numCCDestRegs() const
Number of coprocesor destination regs.
Definition: static_inst.hh:153
gem5::StaticInst::isIndirectCtrl
bool isIndirectCtrl() const
Definition: static_inst.hh:186
gem5::o3::DynInst::setVecElemOperand
void setVecElemOperand(const StaticInst *si, int idx, const TheISA::VecElem val) override
Sets a vector register to a value.
Definition: dyn_inst.hh:1309
gem5::o3::DynInst::isQuiesce
bool isQuiesce() const
Definition: dyn_inst.hh:623
gem5::StaticInst::isUnverifiable
bool isUnverifiable() const
Definition: static_inst.hh:205
gem5::StaticInst::isNop
bool isNop() const
Definition: static_inst.hh:162
gem5::o3::DynInst::setCompleted
void setCompleted()
Sets this instruction as completed.
Definition: dyn_inst.hh:826
gem5::o3::DynInst::setCanIssue
void setCanIssue()
Sets this instruction as ready to issue.
Definition: dyn_inst.hh:838
gem5::o3::DynInst::Regs::BackingStorePtr
std::unique_ptr< uint8_t[]> BackingStorePtr
Definition: dyn_inst.hh:209
gem5::o3::DynInst::Regs::renamedSrcIdx
void renamedSrcIdx(int idx, PhysRegIdPtr phys_reg_id)
Definition: dyn_inst.hh:333
gem5::StaticInst::isSerializeAfter
bool isSerializeAfter() const
Definition: static_inst.hh:194
gem5::o3::DynInst::isIssued
bool isIssued() const
Returns whether or not this instruction has issued.
Definition: dyn_inst.hh:850
gem5::o3::DynInst::predNextInstAddr
Addr predNextInstAddr()
Returns the predicted PC two instructions after the branch.
Definition: dyn_inst.hh:562
gem5::o3::DynInst::memReqFlags
unsigned memReqFlags
The memory request flags (from translation).
Definition: dyn_inst.hh:381
gem5::o3::DynInst::setSerializeAfter
void setSerializeAfter()
Temporarily sets this instruction as a serialize after instruction.
Definition: dyn_inst.hh:698
gem5::InstResult::ResultType::Scalar
@ Scalar
gem5::o3::DynInst::isTranslationDelayed
bool isTranslationDelayed() const
Returns true if the DTB address translation is being delayed due to a hw page table walk.
Definition: dyn_inst.hh:489
gem5::StaticInst::isControl
bool isControl() const
Definition: static_inst.hh:182
gem5::o3::DynInst::setMiscReg
void setMiscReg(int misc_reg, RegVal val) override
Sets a misc.
Definition: dyn_inst.hh:1117
gem5::o3::DynInst::regs
Regs regs
Definition: dyn_inst.hh:354
gem5::ArmISA::f
Bitfield< 6 > f
Definition: misc_types.hh:67
gem5::o3::DynInst::instListIt
ListIt instListIt
Iterator pointing to this BaseDynInst in the list of all insts.
Definition: dyn_inst.hh:360
gem5::o3::DynInst::readVecElemOperand
TheISA::VecElem readVecElemOperand(const StaticInst *si, int idx) const override
Vector Elem Interfaces.
Definition: dyn_inst.hh:1259
gem5::o3::DynInst::updateMiscRegs
void updateMiscRegs()
Called at the commit stage to update the misc.
Definition: dyn_inst.hh:1158
gem5::replaceBits
constexpr void replaceBits(T &val, unsigned first, unsigned last, B bit_val)
A convenience function to replace bits first to last of val with bit_val in place.
Definition: bitfield.hh:197
gem5::o3::DynInst::instResult
std::queue< InstResult > instResult
The result of the instruction; assumes an instruction can have many destination registers.
Definition: dyn_inst.hh:182
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:58
gem5::o3::DynInst::isInROB
bool isInROB() const
Returns whether or not this instruction is in the ROB.
Definition: dyn_inst.hh:931
gem5::o3::DynInst::cpuId
int cpuId() const
Read this CPU's ID.
Definition: dyn_inst.hh:529
gem5::o3::DynInst::isStoreConditional
bool isStoreConditional() const
Definition: dyn_inst.hh:593
gem5::o3::DynInst::TranslationStarted
@ TranslationStarted
Definition: dyn_inst.hh:155
gem5::o3::DynInst::setThreadState
void setThreadState(ThreadState *state)
Sets the pointer to the thread state.
Definition: dyn_inst.hh:1021
gem5::o3::DynInst::isDirectCtrl
bool isDirectCtrl() const
Definition: dyn_inst.hh:603
gem5::o3::DynInst::isSquashedInIQ
bool isSquashedInIQ() const
Returns whether or not this instruction is squashed in the IQ.
Definition: dyn_inst.hh:901
gem5::o3::DynInst::possibleLoadViolation
void possibleLoadViolation(bool f)
Definition: dyn_inst.hh:472
gem5::o3::DynInst::getWritableVecRegOperand
TheISA::VecRegContainer & getWritableVecRegOperand(const StaticInst *si, int idx) override
Read destination vector register operand for modification.
Definition: dyn_inst.hh:1253
gem5::o3::DynInst::lqIt
LSQUnit::LQIterator lqIt
Definition: dyn_inst.hh:391
gem5::o3::DynInst::_destMiscRegIdx
std::vector< short > _destMiscRegIdx
Indexes of the destination misc.
Definition: dyn_inst.hh:194
gem5::o3::DynInst::readIntRegOperand
RegVal readIntRegOperand(const StaticInst *si, int idx) override
Reads an integer register.
Definition: dyn_inst.hh:1232
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::o3::DynInst::effSize
unsigned effSize
The size of the request.
Definition: dyn_inst.hh:384
gem5::o3::DynInst::isInstPrefetch
bool isInstPrefetch() const
Definition: dyn_inst.hh:595
exetrace.hh
gem5::o3::DynInst::SerializeHandled
@ SerializeHandled
Needs to serialize instructions behind it.
Definition: dyn_inst.hh:148
gem5::o3::DynInst::setRequest
void setRequest()
Assert this instruction has generated a memory request.
Definition: dyn_inst.hh:1034
gem5::o3::DynInst::status
std::bitset< NumStatus > status
The status of this BaseDynInst.
Definition: dyn_inst.hh:176
gem5::o3::DynInst::recordResult
void recordResult(bool f)
Records changes to result?
Definition: dyn_inst.hh:411
gem5::o3::DynInst::setCCRegOperand
void setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
Definition: dyn_inst.hh:1326
gem5::o3::DynInst::isSyscall
bool isSyscall() const
Definition: dyn_inst.hh:625
gem5::StaticInst::isCondCtrl
bool isCondCtrl() const
Definition: static_inst.hh:187
gem5::MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:65
gem5::o3::DynInst::getAddrMonitor
AddressMonitor * getAddrMonitor() override
Definition: dyn_inst.hh:1075
gem5::o3::DynInst::instFlags
std::bitset< MaxFlags > instFlags
Definition: dyn_inst.hh:173
gem5::o3::DynInst::isNop
bool isNop() const
Definition: dyn_inst.hh:588
gem5::o3::DynInst::Completed
@ Completed
Instruction is in the LSQ.
Definition: dyn_inst.hh:127
gem5::VecPredRegClass
@ VecPredRegClass
Definition: reg_class.hh:63
gem5::o3::DynInst::isPinnedRegsRenamed
bool isPinnedRegsRenamed() const
Returns whether pinned registers are renamed.
Definition: dyn_inst.hh:940
gem5::o3::DynInst::seqNum
InstSeqNum seqNum
The sequence number of the instruction.
Definition: dyn_inst.hh:102
gem5::o3::DynInst::renameSrcReg
void renameSrcReg(int idx, PhysRegIdPtr renamed_src)
Renames a source logical register to the physical register which has/will produce that logical regist...
Definition: dyn_inst.hh:517
gem5::o3::DynInst::doneTargCalc
bool doneTargCalc()
Checks whether or not this instruction has had its branch target calculated yet.
Definition: dyn_inst.hh:551
gem5::o3::DynInst::getHtmTransactionUid
uint64_t getHtmTransactionUid() const override
Definition: dyn_inst.hh:638
gem5::o3::CPU::setVecReg
void setVecReg(PhysRegIdPtr reg_idx, const TheISA::VecRegContainer &val)
Definition: cpu.cc:1218
gem5::o3::DynInst::Regs::Regs
Regs(size_t srcs, size_t dests)
Definition: dyn_inst.hh:266
gem5::o3::DynInst::tcBase
gem5::ThreadContext * tcBase() const override
Returns the thread context.
Definition: dyn_inst.hh:1024
std::vector< RegVal >
gem5::o3::DynInst::RecoverInst
@ RecoverInst
Regs pinning status updated after squash.
Definition: dyn_inst.hh:142
gem5::o3::DynInst::Regs::flattenedDestIdx
void flattenedDestIdx(int idx, const RegId &reg_id)
Definition: dyn_inst.hh:290
gem5::o3::DynInst::Regs::bytesForSources
static size_t bytesForSources(size_t num)
Definition: dyn_inst.hh:242
gem5::o3::CPU::setMiscReg
void setMiscReg(int misc_reg, RegVal val, ThreadID tid)
Sets a misc.
Definition: cpu.cc:1141
gem5::o3::CPU::getWritableVecPredReg
TheISA::VecPredRegContainer & getWritableVecPredReg(PhysRegIdPtr reg_idx)
Definition: cpu.cc:1190
gem5::o3::DynInst::Regs::flattenedDestIdx
const RegId & flattenedDestIdx(int idx) const
Definition: dyn_inst.hh:282
gem5::StaticInst::isDelayedCommit
bool isDelayedCommit() const
Definition: static_inst.hh:209
gem5::Trace::InstRecord::setPredicate
void setPredicate(bool val)
Definition: insttracer.hh:228
gem5::o3::DynInst::Regs::_flatDestIdx
RegId * _flatDestIdx
Definition: dyn_inst.hh:219
gem5::RefCountingPtr::get
T * get() const
Directly access the pointer itself without taking a reference.
Definition: refcnt.hh:227
gem5::o3::DynInst::numDestRegs
size_t numDestRegs() const
Returns the number of destination registers.
Definition: dyn_inst.hh:730
gem5::StaticInst::numVecDestRegs
int8_t numVecDestRegs() const
Number of vector destination regs.
Definition: static_inst.hh:147
gem5::o3::DynInst::isTempSerializeAfter
bool isTempSerializeAfter()
Checks if this serializeAfter is only temporarily set.
Definition: dyn_inst.hh:704
gem5::o3::DynInst::translationStarted
void translationStarted(bool f)
Definition: dyn_inst.hh:451
gem5::RegId::classValue
RegClass classValue() const
Class accessor.
Definition: reg_class.hh:180
gem5::o3::DynInst::isCommitted
bool isCommitted() const
Returns whether or not this instruction is committed.
Definition: dyn_inst.hh:878
gem5::o3::DynInst::notAnInst
bool notAnInst() const
Definition: dyn_inst.hh:421
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::StaticInst::isFirstMicroop
bool isFirstMicroop() const
Definition: static_inst.hh:211
gem5::o3::DynInst::setResultReady
void setResultReady()
Marks the result as ready.
Definition: dyn_inst.hh:832
gem5::o3::DynInst::Predicate
@ Predicate
Definition: dyn_inst.hh:161
gem5::BaseCPU::socketId
uint32_t socketId() const
Reads this CPU's Socket ID.
Definition: base.hh:191
gem5::o3::DynInst::setPinnedRegsWritten
void setPinnedRegsWritten()
Sets destination registers as written.
Definition: dyn_inst.hh:956
inst_res.hh
gem5::o3::CPU::readFloatReg
RegVal readFloatReg(PhysRegIdPtr phys_reg)
Definition: cpu.cc:1155
gem5::o3::DynInst::ReqMade
@ ReqMade
Definition: dyn_inst.hh:165
gem5::o3::DynInst::Regs::init
void init()
Definition: dyn_inst.hh:261
gem5::o3::DynInst::setNotAnInst
void setNotAnInst()
Definition: dyn_inst.hh:422
gem5::o3::DynInst::SquashedInLSQ
@ SquashedInLSQ
Instruction is squashed in the IQ.
Definition: dyn_inst.hh:137
gem5::StaticInst::destRegIdx
const RegId & destRegIdx(int i) const
Return logical index (architectural reg num) of i'th destination reg.
Definition: static_inst.hh:237
gem5::o3::DynInst::setAtCommit
void setAtCommit()
Definition: dyn_inst.hh:870
gem5::o3::DynInst::thread
ThreadState * thread
Pointer to the thread state.
Definition: dyn_inst.hh:113
gem5::o3::DynInst::setVecPredResult
void setVecPredResult(T &&t)
Predicate result.
Definition: dyn_inst.hh:810
gem5::o3::DynInst::numVecPredDestRegs
int8_t numVecPredDestRegs() const
Definition: dyn_inst.hh:744
gem5::o3::DynInst::MemAccPredicate
@ MemAccPredicate
Definition: dyn_inst.hh:162
gem5::o3::DynInst::setHtmTransactionalState
void setHtmTransactionalState(uint64_t htm_uid, uint64_t htm_depth)
Definition: dyn_inst.hh:667
gem5::o3::CPU::demapPage
void demapPage(Addr vaddr, uint64_t asn)
Definition: cpu.hh:180
gem5::o3::DynInst::readMemAccPredicate
bool readMemAccPredicate() const override
Definition: dyn_inst.hh:1006
gem5::o3::DynInst::Regs
Collect register related information into a single struct.
Definition: dyn_inst.hh:203
gem5::o3::DynInst::translationStarted
bool translationStarted() const
True if the DTB address translation has started.
Definition: dyn_inst.hh:450
gem5::o3::DynInst::IqEntry
@ IqEntry
Definition: dyn_inst.hh:124
gem5::o3::DynInst::hasRequest
bool hasRequest() const
Has this instruction generated a memory request.
Definition: dyn_inst.hh:1032
gem5::o3::DynInst::clearInROB
void clearInROB()
Sets this instruction as a entry the ROB.
Definition: dyn_inst.hh:928
gem5::o3::DynInst::popResult
InstResult popResult(InstResult dflt=InstResult())
Pops a result off the instResult queue.
Definition: dyn_inst.hh:762
gem5::o3::DynInst::numVecElemDestRegs
int8_t numVecElemDestRegs() const
Definition: dyn_inst.hh:739
gem5::o3::DynInst::isInIQ
bool isInIQ() const
Returns whether or not this instruction has issued.
Definition: dyn_inst.hh:895
gem5::RefCountingPtr< StaticInst >
gem5::o3::DynInst::possibleLoadViolation
bool possibleLoadViolation() const
True if this address was found to match a previous load and they issued out of order.
Definition: dyn_inst.hh:467
gem5::AddressMonitor
Definition: base.hh:73
gem5::o3::DynInst::readyToCommit
bool readyToCommit() const
Returns whether or not this instruction is ready to commit.
Definition: dyn_inst.hh:868
gem5::o3::DynInst::~DynInst
~DynInst()
Definition: dyn_inst.cc:98
gem5::o3::DynInst::savedReq
LSQ::LSQRequest * savedReq
Saved memory request (needed when the DTB address translation is delayed due to a hw page table walk)...
Definition: dyn_inst.hh:403
gem5::o3::DynInst::dump
void dump()
Dumps out contents of this BaseDynInst.
Definition: dyn_inst.cc:167
gem5::StaticInst::numVecPredDestRegs
int8_t numVecPredDestRegs() const
Number of predicate destination regs.
Definition: static_inst.hh:151
gem5::o3::DynInst::physEffAddr
Addr physEffAddr
The effective physical address.
Definition: dyn_inst.hh:378
gem5::o3::DynInst::cpu
CPU * cpu
Pointer to the Impl's CPU object.
Definition: dyn_inst.hh:108
gem5::StaticInst::numVecElemDestRegs
int8_t numVecElemDestRegs() const
Number of vector element destination regs.
Definition: static_inst.hh:149
gem5::StaticInst::numFPDestRegs
int8_t numFPDestRegs() const
Number of floating-point destination regs.
Definition: static_inst.hh:143
gem5::StaticInst::opClass
OpClass opClass() const
Operation class. Used to select appropriate function unit in issue.
Definition: static_inst.hh:232
gem5::o3::DynInst::readVecRegOperand
const TheISA::VecRegContainer & readVecRegOperand(const StaticInst *si, int idx) const override
Vector Register Interfaces.
Definition: dyn_inst.hh:1244
gem5::o3::DynInst::readyToIssue
bool readyToIssue() const
Returns whether or not this instruction is ready to issue.
Definition: dyn_inst.hh:841
gem5::o3::DynInst::readPredTarg
const TheISA::PCState & readPredTarg()
Definition: dyn_inst.hh:556
gem5::o3::DynInst::Regs::prevDestIdx
PhysRegIdPtr prevDestIdx(int idx) const
Definition: dyn_inst.hh:313
gem5::PhysRegIdPtr
PhysRegId * PhysRegIdPtr
Definition: reg_class.hh:308
gem5::o3::DynInst::setInstListIt
void setInstListIt(ListIt _instListIt)
Sets iterator for this instruction in the list of all insts.
Definition: dyn_inst.hh:1040
gem5::o3::DynInst::markSrcRegReady
void markSrcRegReady()
Records that one of the source registers is ready.
Definition: dyn_inst.cc:185
gem5::o3::DynInst::setExecuted
void setExecuted()
Sets this instruction as executed.
Definition: dyn_inst.hh:856
gem5::StaticInst::isHtmCancel
bool isHtmCancel() const
Definition: static_inst.hh:217
gem5::o3::DynInst::readCCRegOperand
RegVal readCCRegOperand(const StaticInst *si, int idx) override
Definition: dyn_inst.hh:1278
gem5::StaticInst::isFloating
bool isFloating() const
Definition: static_inst.hh:179
gem5::o3::DynInst::EffAddrValid
@ EffAddrValid
Definition: dyn_inst.hh:159
gem5::o3::ThreadState::getTC
gem5::ThreadContext * getTC()
Returns a pointer to the TC of this thread.
Definition: thread_state.hh:103
gem5::StaticInst::isHtmCmd
bool isHtmCmd() const
Definition: static_inst.hh:220
gem5::o3::DynInst::setVecPredRegOperand
void setVecPredRegOperand(const StaticInst *si, int idx, const TheISA::VecPredRegContainer &val) override
Sets a destination predicate register operand to a value.
Definition: dyn_inst.hh:1318
gem5::Flags< FlagsType >
gem5::o3::CPU::getWritableVecReg
TheISA::VecRegContainer & getWritableVecReg(PhysRegIdPtr reg_idx)
Read physical vector register for modification.
Definition: cpu.cc:1169
gem5::StaticInst::isReturn
bool isReturn() const
Definition: static_inst.hh:184
gem5::o3::DynInst::Committed
@ Committed
Instruction has reached commit.
Definition: dyn_inst.hh:134
gem5::o3::DynInst::destRegIdx
const RegId & destRegIdx(int i) const
Returns the logical register index of the i'th destination register.
Definition: dyn_inst.hh:750
gem5::o3::DynInst::readPredTaken
bool readPredTaken()
Returns whether the instruction was predicted taken or not.
Definition: dyn_inst.hh:568
gem5::ArmISA::b
Bitfield< 7 > b
Definition: misc_types.hh:381
gem5::StaticInst::isHtmStart
bool isHtmStart() const
Definition: static_inst.hh:215
gem5::StaticInst::isDataPrefetch
bool isDataPrefetch() const
Definition: static_inst.hh:174
inst_seq.hh
gem5::o3::CPU
O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buff...
Definition: cpu.hh:95
gem5::StaticInst::branchTarget
virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const
Return the target address for a PC-relative branch.
Definition: static_inst.cc:61
gem5::o3::CPU::setCCReg
void setCCReg(PhysRegIdPtr phys_reg, RegVal val)
Definition: cpu.cc:1240
translation.hh
gem5::StaticInst
Base, ISA-independent static instruction class.
Definition: static_inst.hh:88
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::o3::DynInst::sqIdx
ssize_t sqIdx
Store queue index.
Definition: dyn_inst.hh:394
gem5::o3::DynInst::Regs::BufCursor
BackingStorePtr::pointer BufCursor
Definition: dyn_inst.hh:210
gem5::o3::DynInst::readMiscReg
RegVal readMiscReg(int misc_reg) override
Reads a misc.
Definition: dyn_inst.hh:1108
gem5::o3::DynInst::isSerializeHandled
bool isSerializeHandled()
Checks if the serialization part of this instruction has been handled.
Definition: dyn_inst.hh:714
gem5::o3::DynInst::isFloating
bool isFloating() const
Definition: dyn_inst.hh:598
gem5::o3::CPU::setIntReg
void setIntReg(PhysRegIdPtr phys_reg, RegVal val)
Definition: cpu.cc:1204
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::o3::DynInst::trap
void trap(const Fault &fault)
Traps to handle specified fault.
Definition: dyn_inst.cc:285
gem5::o3::DynInst::setPinnedRegsSquashDone
void setPinnedRegsSquashDone()
Sets dest registers' status updated after squash.
Definition: dyn_inst.hh:972
gem5::o3::DynInst::Regs::renamedSrcIdx
PhysRegIdPtr renamedSrcIdx(int idx) const
Definition: dyn_inst.hh:327
gem5::StaticInst::srcRegIdx
const RegId & srcRegIdx(int i) const
Return logical index (architectural reg num) of i'th source reg.
Definition: static_inst.hh:247
gem5::o3::DynInst::Regs::allocate
static void allocate(T *&ptr, BufCursor &cur, size_t count)
Definition: dyn_inst.hh:250
gem5::o3::DynInst::setFloatRegOperandBits
void setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
Sets the bits of a floating point register of single width to a binary value.
Definition: dyn_inst.hh:1294
gem5::o3::DynInst::setIntRegOperand
void setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
Definition: dyn_inst.hh:1287
gem5::StaticInst::isAtomic
bool isAtomic() const
Definition: static_inst.hh:171
gem5::o3::DynInst::setTid
void setTid(ThreadID tid)
Sets the thread id.
Definition: dyn_inst.hh:1018
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::o3::DynInst::renameDestReg
void renameDestReg(int idx, PhysRegIdPtr renamed_dest, PhysRegIdPtr previous_rename)
Renames a destination register to a physical register.
Definition: dyn_inst.hh:503
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::o3::DynInst::execute
Fault execute()
Executes the instruction.
Definition: dyn_inst.cc:228
gem5::ThreadState::storeCondFailures
unsigned storeCondFailures
Definition: thread_state.hh:152
gem5::o3::DynInst::htmUid
uint64_t htmUid
Definition: dyn_inst.hh:1082
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::probing::Packet
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:109
gem5::o3::DynInst::removeInLSQ
void removeInLSQ()
Sets this instruction as a entry the LSQ.
Definition: dyn_inst.hh:910
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::StaticInst::isHtmStop
bool isHtmStop() const
Definition: static_inst.hh:216
gem5::o3::DynInst::numIntDestRegs
int8_t numIntDestRegs() const
Definition: dyn_inst.hh:735
gem5::o3::DynInst::Regs::_readySrcIdx
uint8_t * _readySrcIdx
Definition: dyn_inst.hh:239
gem5::o3::DynInst::isSquashedInROB
bool isSquashedInROB() const
Returns whether or not this instruction is squashed in the ROB.
Definition: dyn_inst.hh:937
gem5::o3::DynInst::isResultReady
bool isResultReady() const
Returns whether or not the result is ready.
Definition: dyn_inst.hh:835
gem5::o3::DynInst::requestorId
RequestorID requestorId() const
Read this CPU's data requestor ID.
Definition: dyn_inst.hh:535
cpu.hh
gem5::o3::DynInst::setInLSQ
void setInLSQ()
Sets this instruction as a entry the LSQ.
Definition: dyn_inst.hh:907
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::o3::DynInst::armMonitor
void armMonitor(Addr address) override
Definition: dyn_inst.hh:1060
gem5::o3::CPU::readIntReg
RegVal readIntReg(PhysRegIdPtr phys_reg)
Definition: cpu.cc:1148
gem5::o3::DynInst::isLastMicroop
bool isLastMicroop() const
Definition: dyn_inst.hh:629
gem5::o3::DynInst::SerializeAfter
@ SerializeAfter
Needs to serialize on instructions ahead of it.
Definition: dyn_inst.hh:147
gem5::o3::DynInst::lastWakeDependents
Tick lastWakeDependents
Definition: dyn_inst.hh:1102
gem5::RefCounted::count
int count
Definition: refcnt.hh:67
gem5::o3::DynInst::contextId
ContextID contextId() const
Read this context's system-wide ID.
Definition: dyn_inst.hh:538
gem5::o3::DynInst::isUnverifiable
bool isUnverifiable() const
Definition: dyn_inst.hh:624
gem5::o3::DynInst::staticInst
const StaticInstPtr staticInst
The StaticInst used by this BaseDynInst.
Definition: dyn_inst.hh:105
gem5::o3::DynInst::nextInstAddr
Addr nextInstAddr() const
Read the PC of the next instruction.
Definition: dyn_inst.hh:988
gem5::o3::DynInst::setCommitted
void setCommitted()
Sets this instruction as committed.
Definition: dyn_inst.hh:875
gem5::o3::DynInst::IsStrictlyOrdered
@ IsStrictlyOrdered
Definition: dyn_inst.hh:164
gem5::StaticInst::isLoad
bool isLoad() const
Definition: static_inst.hh:169
gem5::o3::DynInst::branchTarget
TheISA::PCState branchTarget() const
Returns the branch target address.
Definition: dyn_inst.hh:721
gem5::o3::DynInst::numFPDestRegs
int8_t numFPDestRegs() const
Definition: dyn_inst.hh:734
gem5::o3::DynInst::numCCDestRegs
int8_t numCCDestRegs() const
Definition: dyn_inst.hh:736
gem5::o3::DynInst::Regs::_numSrcs
size_t _numSrcs
Definition: dyn_inst.hh:206
gem5::StaticInst::isStore
bool isStore() const
Definition: static_inst.hh:170
gem5::o3::DynInst::readFloatRegOperandBits
RegVal readFloatRegOperandBits(const StaticInst *si, int idx) override
Reads a floating point register in its binary format, instead of by value.
Definition: dyn_inst.hh:1238
gem5::o3::DynInst::MaxFlags
@ MaxFlags
Definition: dyn_inst.hh:168
gem5::BaseCPU
Definition: base.hh:107
gem5::o3::DynInst::isSquashAfter
bool isSquashAfter() const
Definition: dyn_inst.hh:618
gem5::o3::CPU::readVecReg
const TheISA::VecRegContainer & readVecReg(PhysRegIdPtr reg_idx) const
Definition: cpu.cc:1162
gem5::o3::DynInst::hitExternalSnoop
void hitExternalSnoop(bool f)
Definition: dyn_inst.hh:482
gem5::o3::DynInst::isFullMemBarrier
bool isFullMemBarrier() const
Definition: dyn_inst.hh:619
gem5::ArmISA::VecRegContainer
gem5::VecRegContainer< NumVecElemPerVecReg *sizeof(VecElem)> VecRegContainer
Definition: vec.hh:62
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::o3::DynInst::readyRegs
uint8_t readyRegs
How many source registers are ready.
Definition: dyn_inst.hh:370
static_inst.hh
gem5::o3::DynInst::setPredTaken
void setPredTaken(bool predicted_taken)
Definition: dyn_inst.hh:571
gem5::o3::DynInst::isInteger
bool isInteger() const
Definition: dyn_inst.hh:597
gem5::o3::DynInst::writeMem
Fault writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable) override
Definition: dyn_inst.cc:310
gem5::StaticInst::isDirectCtrl
bool isDirectCtrl() const
Definition: static_inst.hh:185
gem5::StaticInst::isVector
bool isVector() const
Definition: static_inst.hh:180
gem5::o3::DynInst::RobEntry
@ RobEntry
Instruction is in the IQ.
Definition: dyn_inst.hh:125
gem5::o3::DynInst::isMacroop
bool isMacroop() const
Definition: dyn_inst.hh:626
gem5::o3::LSQUnit::LQIterator
CircularQueue< LQEntry >::iterator LQIterator
Definition: lsq_unit.hh:604
gem5::o3::DynInst::ResultReady
@ ResultReady
Instruction has completed.
Definition: dyn_inst.hh:128
gem5::o3::DynInst::PinnedRegsWritten
@ PinnedRegsWritten
Pinned registers are renamed.
Definition: dyn_inst.hh:140
gem5::ArmISA::t
Bitfield< 5 > t
Definition: misc_types.hh:70
gem5::StaticInst::numIntDestRegs
int8_t numIntDestRegs() const
Number of integer destination regs.
Definition: static_inst.hh:145
gem5::o3::DynInst::translationCompleted
bool translationCompleted() const
True if the DTB address translation has completed.
Definition: dyn_inst.hh:455
gem5::o3::DynInst::clearCanIssue
void clearCanIssue()
Clears this instruction being able to issue.
Definition: dyn_inst.hh:844
gem5::InstResult::ResultType::VecReg
@ VecReg
gem5::o3::DynInst::readPredicate
bool readPredicate() const override
Definition: dyn_inst.hh:993
gem5::ArmISA::si
Bitfield< 6 > si
Definition: misc_types.hh:772
gem5::BaseCPU::getCpuAddrMonitor
AddressMonitor * getCpuAddrMonitor(ThreadID tid)
Definition: base.hh:609
gem5::o3::DynInst::isFirstMicroop
bool isFirstMicroop() const
Definition: dyn_inst.hh:630
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::o3::DynInst::isHtmStop
bool isHtmStop() const
Definition: dyn_inst.hh:633
dyn_inst_ptr.hh
gem5::o3::DynInst::isCall
bool isCall() const
Definition: dyn_inst.hh:601
gem5::o3::DynInst::isAtCommit
bool isAtCommit()
Definition: dyn_inst.hh:872
gem5::o3::DynInst::setSerializeBefore
void setSerializeBefore()
Temporarily sets this instruction as a serialize before instruction.
Definition: dyn_inst.hh:689
gem5::o3::DynInst::_destMiscRegVal
std::vector< RegVal > _destMiscRegVal
Values to be written to the destination misc.
Definition: dyn_inst.hh:188
gem5::InstResult::ResultType::VecPredReg
@ VecPredReg
gem5::o3::DynInst::Regs::readySrcIdx
bool readySrcIdx(int idx) const
Definition: dyn_inst.hh:339
gem5::o3::DynInst::opClass
OpClass opClass() const
Returns the opclass of this instruction.
Definition: dyn_inst.hh:717
gem5::o3::DynInst::Regs::_numDests
size_t _numDests
Definition: dyn_inst.hh:207
gem5::StaticInst::isLastMicroop
bool isLastMicroop() const
Definition: static_inst.hh:210
gem5::o3::DynInst::isSquashedInLSQ
bool isSquashedInLSQ() const
Returns whether or not this instruction is squashed in the LSQ.
Definition: dyn_inst.hh:919
gem5::o3::DynInst::setSerializeHandled
void setSerializeHandled()
Sets the serialization part of this instruction as handled.
Definition: dyn_inst.hh:707
gem5::o3::LSQUnit::SQIterator
CircularQueue< SQEntry >::iterator SQIterator
Definition: lsq_unit.hh:605
gem5::o3::DynInst::isLoad
bool isLoad() const
Definition: dyn_inst.hh:590
gem5::StaticInst::isMemRef
bool isMemRef() const
Definition: static_inst.hh:165
gem5::o3::DynInst::completeAcc
Fault completeAcc(PacketPtr pkt)
Completes the access.
Definition: dyn_inst.cc:262
gem5::PowerISA::so
Bitfield< 28 > so
Definition: misc.hh:54
gem5::o3::DynInst::mispredicted
bool mispredicted()
Returns whether the instruction mispredicted.
Definition: dyn_inst.hh:578
gem5::o3::DynInst::Executed
@ Executed
Instruction has issued.
Definition: dyn_inst.hh:131
gem5::o3::DynInst::setSquashed
void setSquashed()
Sets this instruction as squashed.
Definition: dyn_inst.cc:203
gem5::o3::DynInst::isSerializing
bool isSerializing() const
Definition: dyn_inst.hh:607
gem5::o3::DynInst::Regs::bytesForDests
static size_t bytesForDests(size_t num)
Definition: dyn_inst.hh:230
gem5::o3::DynInst::mwait
bool mwait(PacketPtr pkt) override
Definition: dyn_inst.hh:1065
gem5::o3::DynInst::inHtmTransactionalState
bool inHtmTransactionalState() const override
Definition: dyn_inst.hh:652
gem5::o3::DynInst::NumStatus
@ NumStatus
Serialization has been handled.
Definition: dyn_inst.hh:149
gem5::ThreadState::contextId
ContextID contextId() const
Definition: thread_state.hh:63
gem5::o3::DynInst::Regs::renamedDestIdx
PhysRegIdPtr renamedDestIdx(int idx) const
Definition: dyn_inst.hh:298
gem5::o3::CPU::setFloatReg
void setFloatReg(PhysRegIdPtr phys_reg, RegVal val)
Definition: cpu.cc:1211
gem5::o3::CPU::setVecPredReg
void setVecPredReg(PhysRegIdPtr reg_idx, const TheISA::VecPredRegContainer &val)
Definition: cpu.cc:1232
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::o3::DynInst::Issued
@ Issued
Instruction can issue and execute.
Definition: dyn_inst.hh:130
gem5::o3::DynInst::predMicroPC
Addr predMicroPC()
Returns the predicted micro PC after the branch.
Definition: dyn_inst.hh:565
gem5::o3::ThreadState::noSquashFromTC
bool noSquashFromTC
Definition: thread_state.hh:84
gem5::InstResult::ResultType::VecElem
@ VecElem
gem5::o3::DynInst::clearSerializeAfter
void clearSerializeAfter()
Clears the serializeAfter part of this instruction.
Definition: dyn_inst.hh:701
gem5::o3::DynInst::isPinnedRegsSquashDone
bool isPinnedRegsSquashDone() const
Return whether dest registers' pinning status updated after squash.
Definition: dyn_inst.hh:965
gem5::StaticInst::isReadBarrier
bool isReadBarrier() const
Definition: static_inst.hh:201
gem5::o3::ThreadState
Class that has various thread state, such as the status, the current instruction being processed,...
Definition: thread_state.hh:66
gem5::o3::DynInst::initiateMemAMO
Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override
Definition: dyn_inst.cc:322
gem5::RefCounted
Derive from RefCounted if you want to enable reference counting of this class.
Definition: refcnt.hh:60
gem5::o3::DynInst::isTempSerializeBefore
bool isTempSerializeBefore()
Checks if this serializeBefore is only temporarily set.
Definition: dyn_inst.hh:695
gem5::o3::DynInst::strictlyOrdered
bool strictlyOrdered() const
Is this instruction's memory access strictly ordered?
Definition: dyn_inst.hh:1028
gem5::o3::DynInst::isReturn
bool isReturn() const
Definition: dyn_inst.hh:602
gem5::o3::DynInst::resultSize
uint8_t resultSize()
Return the size of the instResult queue.
Definition: dyn_inst.hh:756
gem5::o3::DynInst::getFault
Fault & getFault()
TODO: This I added for the LSQRequest side to be able to modify the fault.
Definition: dyn_inst.hh:544
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:60
gem5::o3::DynInst::isNonSpeculative
bool isNonSpeculative() const
Definition: dyn_inst.hh:622
gem5::StaticInst::isInstPrefetch
bool isInstPrefetch() const
Definition: static_inst.hh:173
gem5::o3::DynInst::clearInIQ
void clearInIQ()
Sets this instruction as a entry the IQ.
Definition: dyn_inst.hh:892
gem5::o3::DynInst::HitExternalSnoop
@ HitExternalSnoop
Definition: dyn_inst.hh:158
gem5::o3::DynInst::getHtmTransactionalDepth
uint64_t getHtmTransactionalDepth() const override
Definition: dyn_inst.hh:658
gem5::o3::DynInst::clearSerializeBefore
void clearSerializeBefore()
Clears the serializeBefore part of this instruction.
Definition: dyn_inst.hh:692
gem5::o3::DynInst::SquashedInROB
@ SquashedInROB
Instruction is squashed in the LSQ.
Definition: dyn_inst.hh:138
gem5::o3::DynInst::translationCompleted
void translationCompleted(bool f)
Definition: dyn_inst.hh:459
gem5::o3::DynInst::Regs::prevDestIdx
void prevDestIdx(int idx, PhysRegIdPtr phys_reg_id)
Definition: dyn_inst.hh:320
gem5::o3::DynInst::predPC
TheISA::PCState predPC
Predicted PC state after this instruction.
Definition: dyn_inst.hh:364
gem5::o3::DynInst::setVecElemResult
void setVecElemResult(T &&t)
Vector element result.
Definition: dyn_inst.hh:799
gem5::o3::DynInst::Flags
Flags
Definition: dyn_inst.hh:152
gem5::o3::DynInst::CanCommit
@ CanCommit
Instruction has executed.
Definition: dyn_inst.hh:132
gem5::o3::DynInst::readMiscRegOperand
RegVal readMiscRegOperand(const StaticInst *si, int idx) override
Reads a misc.
Definition: dyn_inst.hh:1138
gem5::ArmISA::VecElem
uint32_t VecElem
Definition: vec.hh:60
gem5::o3::DynInst::SerializeBefore
@ SerializeBefore
Is a thread synchronization instruction.
Definition: dyn_inst.hh:145
gem5::o3::DynInst::AtCommit
@ AtCommit
Instruction can commit.
Definition: dyn_inst.hh:133
gem5::o3::DynInst::clearHtmTransactionalState
void clearHtmTransactionalState()
Definition: dyn_inst.hh:675
gem5::o3::DynInst::mwaitAtomic
void mwaitAtomic(gem5::ThreadContext *tc) override
Definition: dyn_inst.hh:1070
gem5::o3::DynInst::isDataPrefetch
bool isDataPrefetch() const
Definition: dyn_inst.hh:596
gem5::o3::DynInst::getFault
Fault getFault() const
Returns the fault type.
Definition: dyn_inst.hh:541
gem5::BaseCPU::cpuId
int cpuId() const
Reads this CPU's ID.
Definition: base.hh:188
gem5::o3::DynInst::MemOpDone
@ MemOpDone
Definition: dyn_inst.hh:166
gem5::o3::DynInst::pcState
TheISA::PCState pcState() const override
Read the PC state of this instruction.
Definition: dyn_inst.hh:979
gem5::o3::DynInst::setSquashedInLSQ
void setSquashedInLSQ()
Sets this instruction as squashed in the LSQ.
Definition: dyn_inst.hh:916
gem5::StaticInst::isMacroop
bool isMacroop() const
Definition: static_inst.hh:207
gem5::o3::DynInst::getWritableVecPredRegOperand
TheISA::VecPredRegContainer & getWritableVecPredRegOperand(const StaticInst *si, int idx) override
Gets destination predicate register operand for modification.
Definition: dyn_inst.hh:1271
gem5::o3::DynInst::isCondCtrl
bool isCondCtrl() const
Definition: dyn_inst.hh:605
gem5::StaticInst::isSquashAfter
bool isSquashAfter() const
Definition: static_inst.hh:195
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:246
gem5::o3::DynInst::isStore
bool isStore() const
Definition: dyn_inst.hh:591
exec_context.hh
gem5::o3::DynInst::clearIssued
void clearIssued()
Clears this instruction as being issued.
Definition: dyn_inst.hh:853
gem5::o3::DynInst::srcRegIdx
const RegId & srcRegIdx(int i) const
Returns the logical register index of the i'th source register.
Definition: dyn_inst.hh:753
gem5::o3::DynInst::Regs::buf
BackingStorePtr buf
Definition: dyn_inst.hh:212
reg_class.hh
gem5::o3::DynInst::traceData
Trace::InstRecord * traceData
InstRecord that tracks this instructions.
Definition: dyn_inst.hh:119
gem5::StaticInst::isSerializing
bool isSerializing() const
Definition: static_inst.hh:190
lsq_unit.hh
gem5::o3::DynInst::Regs::_destIdx
PhysRegIdPtr * _destIdx
Definition: dyn_inst.hh:223
gem5::o3::DynInst::predInstAddr
Addr predInstAddr()
Returns the predicted PC immediately after the branch.
Definition: dyn_inst.hh:559
gem5::o3::CPU::readMiscReg
RegVal readMiscReg(int misc_reg, ThreadID tid)
Reads a misc.
Definition: cpu.cc:1128
gem5::StaticInst::isInteger
bool isInteger() const
Definition: static_inst.hh:178
gem5::o3::DynInst::setPinnedRegsRenamed
void setPinnedRegsRenamed()
Sets the destination registers as renamed.
Definition: dyn_inst.hh:944
gem5::o3::DynInst::initiateMemRead
Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable) override
Definition: dyn_inst.cc:291
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:73
gem5::StaticInst::isCall
bool isCall() const
Definition: static_inst.hh:183
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::o3::DynInst::setIssued
void setIssued()
Sets this instruction as issued from the IQ.
Definition: dyn_inst.hh:847
gem5::PhysRegId
Physical register ID.
Definition: reg_class.hh:198
gem5::o3::DynInst::NotAnInst
@ NotAnInst
Definition: dyn_inst.hh:154
gem5::o3::DynInst::memOpDone
bool memOpDone() const
Whether or not the memory operation is done.
Definition: dyn_inst.hh:418
gem5::o3::DynInst::DynInst
DynInst(const StaticInstPtr &staticInst, const StaticInstPtr &macroop, TheISA::PCState pc, TheISA::PCState predPC, InstSeqNum seq_num, CPU *cpu)
BaseDynInst constructor given a binary instruction.
Definition: dyn_inst.cc:55
gem5::o3::DynInst::isWriteBarrier
bool isWriteBarrier() const
Definition: dyn_inst.hh:621
gem5::o3::DynInst::initiateHtmCmd
Fault initiateHtmCmd(Request::Flags flags) override
Initiate an HTM command, e.g.
Definition: dyn_inst.cc:302
gem5::o3::DynInst::isExecuted
bool isExecuted() const
Returns whether or not this instruction has executed.
Definition: dyn_inst.hh:859
gem5::o3::DynInst::clearCanCommit
void clearCanCommit()
Clears this instruction as being ready to commit.
Definition: dyn_inst.hh:865
gem5::o3::DynInst::Regs::_prevDestIdx
PhysRegIdPtr * _prevDestIdx
Definition: dyn_inst.hh:227
gem5::o3::DynInst::isPinnedRegsWritten
bool isPinnedRegsWritten() const
Returns whether destination registers are written.
Definition: dyn_inst.hh:952
gem5::o3::DynInst::PossibleLoadViolation
@ PossibleLoadViolation
Definition: dyn_inst.hh:157
gem5::o3::DynInst::macroop
const StaticInstPtr macroop
The Macroop if one exists.
Definition: dyn_inst.hh:367
gem5::o3::DynInst::isIndirectCtrl
bool isIndirectCtrl() const
Definition: dyn_inst.hh:604
gem5::RequestorID
uint16_t RequestorID
Definition: request.hh:95
gem5::o3::DynInst::effAddr
Addr effAddr
The effective virtual address (lds & stores only).
Definition: dyn_inst.hh:375
gem5::BaseCPU::dataRequestorId
RequestorID dataRequestorId() const
Reads this CPU's unique data requestor ID.
Definition: base.hh:194
trace.hh
gem5::o3::DynInst::Regs::numDests
size_t numDests() const
Definition: dyn_inst.hh:258
gem5::StaticInst::isFullMemBarrier
bool isFullMemBarrier() const
Definition: static_inst.hh:197
gem5::StaticInst::isUncondCtrl
bool isUncondCtrl() const
Definition: static_inst.hh:188
gem5::o3::DynInst::isHtmCancel
bool isHtmCancel() const
Definition: dyn_inst.hh:634
gem5::o3::DynInst::effAddrValid
void effAddrValid(bool b)
Definition: dyn_inst.hh:415
gem5::Trace::InstRecord
Definition: insttracer.hh:58
gem5::o3::DynInst::isReadBarrier
bool isReadBarrier() const
Definition: dyn_inst.hh:620
gem5::BaseCPU::mwait
bool mwait(ThreadID tid, PacketPtr pkt)
Definition: base.cc:217
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::StaticInst::isSyscall
bool isSyscall() const
Definition: static_inst.hh:206
gem5::o3::DynInst::htmDepth
uint64_t htmDepth
Definition: dyn_inst.hh:1083
gem5::o3::DynInst::readStCondFailures
unsigned int readStCondFailures() const override
Returns the number of consecutive store conditional failures.
Definition: dyn_inst.hh:1045
gem5::StaticInst::isStoreConditional
bool isStoreConditional() const
Definition: static_inst.hh:172
gem5::o3::DynInst::isDelayedCommit
bool isDelayedCommit() const
Definition: dyn_inst.hh:628
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
cpu.hh
std::list
STL list class.
Definition: stl.hh:51
gem5::o3::DynInst::SquashedInIQ
@ SquashedInIQ
Instruction is squashed.
Definition: dyn_inst.hh:136
gem5::o3::DynInst::setMemAccPredicate
void setMemAccPredicate(bool val) override
Definition: dyn_inst.hh:1012
gem5::o3::DynInst::forwardOldRegs
void forwardOldRegs()
Definition: dyn_inst.hh:1175
gem5::AtomicOpFunctorPtr
std::unique_ptr< AtomicOpFunctor > AtomicOpFunctorPtr
Definition: amo.hh:242
gem5::o3::DynInst::fault
Fault fault
The kind of fault this instruction has generated.
Definition: dyn_inst.hh:116
gem5::o3::DynInst::firstIssue
Tick firstIssue
Definition: dyn_inst.hh:1101
gem5::o3::DynInst::Regs::renamedDestIdx
void renamedDestIdx(int idx, PhysRegIdPtr phys_reg_id)
Definition: dyn_inst.hh:305
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:57
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::o3::CPU::readVecPredReg
const TheISA::VecPredRegContainer & readVecPredReg(PhysRegIdPtr reg_idx) const
Definition: cpu.cc:1183
gem5::o3::DynInst::demapPage
void demapPage(Addr vaddr, uint64_t asn) override
Invalidate a page in the DTLB and ITLB.
Definition: dyn_inst.hh:432
gem5::o3::DynInst::strictlyOrdered
void strictlyOrdered(bool so)
Definition: dyn_inst.hh:1029
gem5::o3::DynInst::setVecResult
void setVecResult(T &&t)
Full vector result.
Definition: dyn_inst.hh:788
gem5::o3::DynInst::isVector
bool isVector() const
Definition: dyn_inst.hh:599
gem5::o3::DynInst::CanIssue
@ CanIssue
Instruction has its result.
Definition: dyn_inst.hh:129
gem5::o3::DynInst::isHtmCmd
bool isHtmCmd() const
Definition: dyn_inst.hh:635
gem5::o3::DynInst::numVecDestRegs
int8_t numVecDestRegs() const
Definition: dyn_inst.hh:737
gem5::o3::DynInst::isUncondCtrl
bool isUncondCtrl() const
Definition: dyn_inst.hh:606
gem5::o3::DynInst::instAddr
Addr instAddr() const
Read the PC of this instruction.
Definition: dyn_inst.hh:985
gem5::o3::DynInst::LsqEntry
@ LsqEntry
Instruction is in the ROB.
Definition: dyn_inst.hh:126
gem5::o3::DynInst::setSquashedInROB
void setSquashedInROB()
Sets this instruction as squashed in the ROB.
Definition: dyn_inst.hh:934
gem5::o3::DynInst::effAddrValid
bool effAddrValid() const
Is the effective virtual address valid.
Definition: dyn_inst.hh:414
gem5::o3::DynInst::readVecPredRegOperand
const TheISA::VecPredRegContainer & readVecPredRegOperand(const StaticInst *si, int idx) const override
Predicate registers interface.
Definition: dyn_inst.hh:1265
gem5::o3::DynInst::pcState
void pcState(const TheISA::PCState &val) override
Set the PC state of this instruction.
Definition: dyn_inst.hh:982
gem5::o3::DynInst::reqToVerify
RequestPtr reqToVerify
Definition: dyn_inst.hh:407
gem5::o3::DynInst::lqIdx
ssize_t lqIdx
Load queue index.
Definition: dyn_inst.hh:390
gem5::o3::DynInst::isSquashed
bool isSquashed() const
Returns whether or not this instruction is squashed.
Definition: dyn_inst.hh:884
gem5::InstResult
Definition: inst_res.hh:49
gem5::StaticInst::advancePC
virtual void advancePC(TheISA::PCState &pc_state) const =0
gem5::o3::DynInst::memOpDone
void memOpDone(bool f)
Definition: dyn_inst.hh:419
gem5::o3::DynInst::PredTaken
@ PredTaken
Definition: dyn_inst.hh:163
gem5::o3::DynInst::setStCondFailures
void setStCondFailures(unsigned int sc_failures) override
Sets the number of consecutive store conditional failures.
Definition: dyn_inst.hh:1052
gem5::o3::DynInst::Status
Status
Definition: dyn_inst.hh:122
gem5::o3::DynInst::BlockingInst
@ BlockingInst
Is a recover instruction.
Definition: dyn_inst.hh:143
gem5::o3::DynInst::isHtmStart
bool isHtmStart() const
Definition: dyn_inst.hh:632
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242
gem5::o3::DynInst::isAtomic
bool isAtomic() const
Definition: dyn_inst.hh:592
gem5::o3::DynInst
Definition: dyn_inst.hh:76
gem5::o3::DynInst::setPredicate
void setPredicate(bool val) override
Definition: dyn_inst.hh:996
gem5::o3::DynInst::memData
uint8_t * memData
Pointer to the data for the memory access.
Definition: dyn_inst.hh:387
gem5::o3::DynInst::hitExternalSnoop
bool hitExternalSnoop() const
True if the address hit a external snoop while sitting in the LSQ.
Definition: dyn_inst.hh:481
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::o3::DynInst::isSerializeAfter
bool isSerializeAfter() const
Definition: dyn_inst.hh:614
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::o3::DynInst::isSerializeBefore
bool isSerializeBefore() const
Definition: dyn_inst.hh:609
gem5::o3::DynInst::setInROB
void setInROB()
Sets this instruction as a entry the ROB.
Definition: dyn_inst.hh:925
gem5::o3::DynInst::setScalarResult
void setScalarResult(T &&t)
Pushes a result onto the instResult queue.
Definition: dyn_inst.hh:777

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