gem5  v21.2.1.1
dyn_inst.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2010, 2016 ARM Limited
3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
4  * All rights reserved
5  *
6  * The license below extends only to copyright in the software and shall
7  * not be construed as granting a license to any other intellectual
8  * property including but not limited to intellectual property relating
9  * to a hardware implementation of the functionality of the software
10  * licensed hereunder. You may use the software subject to the license
11  * terms below provided that you ensure that this notice is replicated
12  * unmodified and in its entirety in all distributions of the software,
13  * modified or unmodified, in source code or in binary form.
14  *
15  * Copyright (c) 2004-2006 The Regents of The University of Michigan
16  * All rights reserved.
17  *
18  * Redistribution and use in source and binary forms, with or without
19  * modification, are permitted provided that the following conditions are
20  * met: redistributions of source code must retain the above copyright
21  * notice, this list of conditions and the following disclaimer;
22  * redistributions in binary form must reproduce the above copyright
23  * notice, this list of conditions and the following disclaimer in the
24  * documentation and/or other materials provided with the distribution;
25  * neither the name of the copyright holders nor the names of its
26  * contributors may be used to endorse or promote products derived from
27  * this software without specific prior written permission.
28  *
29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40  */
41 
42 #ifndef __CPU_O3_DYN_INST_HH__
43 #define __CPU_O3_DYN_INST_HH__
44 
45 #include <algorithm>
46 #include <array>
47 #include <deque>
48 #include <list>
49 #include <string>
50 
51 #include "base/refcnt.hh"
52 #include "base/trace.hh"
53 #include "config/the_isa.hh"
54 #include "cpu/checker/cpu.hh"
55 #include "cpu/exec_context.hh"
56 #include "cpu/exetrace.hh"
57 #include "cpu/inst_res.hh"
58 #include "cpu/inst_seq.hh"
59 #include "cpu/o3/cpu.hh"
60 #include "cpu/o3/dyn_inst_ptr.hh"
61 #include "cpu/o3/lsq_unit.hh"
62 #include "cpu/op_class.hh"
63 #include "cpu/reg_class.hh"
64 #include "cpu/static_inst.hh"
65 #include "cpu/translation.hh"
66 #include "debug/HtmCpu.hh"
67 
68 namespace gem5
69 {
70 
71 class Packet;
72 
73 namespace o3
74 {
75 
76 class DynInst : public ExecContext, public RefCounted
77 {
78  private:
80  InstSeqNum seq_num, CPU *cpu);
81 
82  public:
83  // The list of instructions iterator type.
85 
86  struct Arrays
87  {
88  size_t numSrcs;
89  size_t numDests;
90 
95  uint8_t *readySrcIdx;
96  };
97 
98  static void *operator new(size_t count, Arrays &arrays);
99 
101  DynInst(const Arrays &arrays, const StaticInstPtr &staticInst,
102  const StaticInstPtr &macroop, InstSeqNum seq_num, CPU *cpu);
103 
104  DynInst(const Arrays &arrays, const StaticInstPtr &staticInst,
105  const StaticInstPtr &macroop, const PCStateBase &pc,
106  const PCStateBase &pred_pc, InstSeqNum seq_num, CPU *cpu);
107 
109  DynInst(const Arrays &arrays, const StaticInstPtr &_staticInst,
110  const StaticInstPtr &_macroop);
111 
112  ~DynInst();
113 
115  Fault execute();
116 
118  Fault initiateAcc();
119 
122 
125 
128 
130  CPU *cpu = nullptr;
131 
132  BaseCPU *getCpuPtr() { return cpu; }
133 
135  ThreadState *thread = nullptr;
136 
139 
142 
143  protected:
144  enum Status
145  {
172  };
173 
174  enum Flags
175  {
191  };
192 
193  private:
194  /* An amalgamation of a lot of boolean values into one */
195  std::bitset<MaxFlags> instFlags;
196 
198  std::bitset<NumStatus> status;
199 
200  protected:
204  std::queue<InstResult> instResult;
205 
207  std::unique_ptr<PCStateBase> pc;
208 
211 
217 
218  size_t _numSrcs;
219  size_t _numDests;
220 
221  // Flattened register index of the destination registers of this
222  // instruction.
224 
225  // Physical register index of the destination registers of this
226  // instruction.
228 
229  // Physical register index of the previous producers of the
230  // architected destinations.
232 
233  // Physical register index of the source registers of this instruction.
235 
236  // Whether or not the source register is ready, one bit per register.
237  uint8_t *_readySrcIdx;
238 
239  public:
240  size_t numSrcs() const { return _numSrcs; }
241  size_t numDests() const { return _numDests; }
242 
243  // Returns the flattened register index of the idx'th destination
244  // register.
245  const RegId &
246  flattenedDestIdx(int idx) const
247  {
248  return _flatDestIdx[idx];
249  }
250 
251  // Flattens a destination architectural register index into a logical
252  // index.
253  void
254  flattenedDestIdx(int idx, const RegId &reg_id)
255  {
256  _flatDestIdx[idx] = reg_id;
257  }
258 
259  // Returns the physical register index of the idx'th destination
260  // register.
262  renamedDestIdx(int idx) const
263  {
264  return _destIdx[idx];
265  }
266 
267  // Set the renamed dest register id.
268  void
269  renamedDestIdx(int idx, PhysRegIdPtr phys_reg_id)
270  {
271  _destIdx[idx] = phys_reg_id;
272  }
273 
274  // Returns the physical register index of the previous physical
275  // register that remapped to the same logical register index.
277  prevDestIdx(int idx) const
278  {
279  return _prevDestIdx[idx];
280  }
281 
282  // Set the previous renamed dest register id.
283  void
284  prevDestIdx(int idx, PhysRegIdPtr phys_reg_id)
285  {
286  _prevDestIdx[idx] = phys_reg_id;
287  }
288 
289  // Returns the physical register index of the i'th source register.
291  renamedSrcIdx(int idx) const
292  {
293  return _srcIdx[idx];
294  }
295 
296  void
297  renamedSrcIdx(int idx, PhysRegIdPtr phys_reg_id)
298  {
299  _srcIdx[idx] = phys_reg_id;
300  }
301 
302  bool
303  readySrcIdx(int idx) const
304  {
305  uint8_t &byte = _readySrcIdx[idx / 8];
306  return bits(byte, idx % 8);
307  }
308 
309  void
310  readySrcIdx(int idx, bool ready)
311  {
312  uint8_t &byte = _readySrcIdx[idx / 8];
313  replaceBits(byte, idx % 8, ready ? 1 : 0);
314  }
315 
318 
321 
323 
324  std::unique_ptr<PCStateBase> predPC;
325 
328 
330  uint8_t readyRegs = 0;
331 
332  public:
334 
336 
339 
341  unsigned memReqFlags = 0;
342 
344  unsigned effSize;
345 
347  uint8_t *memData = nullptr;
348 
350  ssize_t lqIdx = -1;
352 
354  ssize_t sqIdx = -1;
356 
357 
359 
364 
366  // Need a copy of main request pointer to verify on writes.
368 
369  public:
371  void recordResult(bool f) { instFlags[RecordResult] = f; }
372 
374  bool effAddrValid() const { return instFlags[EffAddrValid]; }
375  void effAddrValid(bool b) { instFlags[EffAddrValid] = b; }
376 
378  bool memOpDone() const { return instFlags[MemOpDone]; }
379  void memOpDone(bool f) { instFlags[MemOpDone] = f; }
380 
381  bool notAnInst() const { return instFlags[NotAnInst]; }
382  void setNotAnInst() { instFlags[NotAnInst] = true; }
383 
384 
386  //
387  // INSTRUCTION EXECUTION
388  //
390 
391  void
392  demapPage(Addr vaddr, uint64_t asn) override
393  {
394  cpu->demapPage(vaddr, asn);
395  }
396 
397  Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags,
398  const std::vector<bool> &byte_enable) override;
399 
400  Fault initiateHtmCmd(Request::Flags flags) override;
401 
402  Fault writeMem(uint8_t *data, unsigned size, Addr addr,
403  Request::Flags flags, uint64_t *res,
404  const std::vector<bool> &byte_enable) override;
405 
406  Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags,
407  AtomicOpFunctorPtr amo_op) override;
408 
412 
414  bool
416  {
418  }
420 
426  bool
428  {
430  }
431  void
433  {
435  }
436 
441  bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; }
443 
448  bool
450  {
451  return (translationStarted() && !translationCompleted());
452  }
453 
454  public:
455 #ifdef DEBUG
456  void dumpSNList();
457 #endif
458 
462  void
463  renameDestReg(int idx, PhysRegIdPtr renamed_dest,
464  PhysRegIdPtr previous_rename)
465  {
466  renamedDestIdx(idx, renamed_dest);
467  prevDestIdx(idx, previous_rename);
468  if (renamed_dest->isPinned())
470  }
471 
476  void
477  renameSrcReg(int idx, PhysRegIdPtr renamed_src)
478  {
479  renamedSrcIdx(idx, renamed_src);
480  }
481 
483  void dump();
484 
486  void dump(std::string &outstring);
487 
489  int cpuId() const { return cpu->cpuId(); }
490 
492  uint32_t socketId() const { return cpu->socketId(); }
493 
495  RequestorID requestorId() const { return cpu->dataRequestorId(); }
496 
498  ContextID contextId() const { return thread->contextId(); }
499 
501  Fault getFault() const { return fault; }
504  Fault& getFault() { return fault; }
505 
511  bool doneTargCalc() { return false; }
512 
514  void setPredTarg(const PCStateBase &pred_pc) { set(predPC, pred_pc); }
515 
516  const PCStateBase &readPredTarg() { return *predPC; }
517 
519  bool readPredTaken() { return instFlags[PredTaken]; }
520 
521  void
522  setPredTaken(bool predicted_taken)
523  {
524  instFlags[PredTaken] = predicted_taken;
525  }
526 
528  bool
530  {
531  std::unique_ptr<PCStateBase> next_pc(pc->clone());
532  staticInst->advancePC(*next_pc);
533  return *next_pc != *predPC;
534  }
535 
536  //
537  // Instruction types. Forward checks to StaticInst object.
538  //
539  bool isNop() const { return staticInst->isNop(); }
540  bool isMemRef() const { return staticInst->isMemRef(); }
541  bool isLoad() const { return staticInst->isLoad(); }
542  bool isStore() const { return staticInst->isStore(); }
543  bool isAtomic() const { return staticInst->isAtomic(); }
544  bool isStoreConditional() const
545  { return staticInst->isStoreConditional(); }
546  bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
547  bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
548  bool isInteger() const { return staticInst->isInteger(); }
549  bool isFloating() const { return staticInst->isFloating(); }
550  bool isVector() const { return staticInst->isVector(); }
551  bool isControl() const { return staticInst->isControl(); }
552  bool isCall() const { return staticInst->isCall(); }
553  bool isReturn() const { return staticInst->isReturn(); }
554  bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
555  bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
556  bool isCondCtrl() const { return staticInst->isCondCtrl(); }
557  bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
558  bool isSerializing() const { return staticInst->isSerializing(); }
559  bool
561  {
563  }
564  bool
566  {
568  }
569  bool isSquashAfter() const { return staticInst->isSquashAfter(); }
570  bool isFullMemBarrier() const { return staticInst->isFullMemBarrier(); }
571  bool isReadBarrier() const { return staticInst->isReadBarrier(); }
572  bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
573  bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
574  bool isQuiesce() const { return staticInst->isQuiesce(); }
575  bool isUnverifiable() const { return staticInst->isUnverifiable(); }
576  bool isSyscall() const { return staticInst->isSyscall(); }
577  bool isMacroop() const { return staticInst->isMacroop(); }
578  bool isMicroop() const { return staticInst->isMicroop(); }
579  bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
580  bool isLastMicroop() const { return staticInst->isLastMicroop(); }
581  bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
582  // hardware transactional memory
583  bool isHtmStart() const { return staticInst->isHtmStart(); }
584  bool isHtmStop() const { return staticInst->isHtmStop(); }
585  bool isHtmCancel() const { return staticInst->isHtmCancel(); }
586  bool isHtmCmd() const { return staticInst->isHtmCmd(); }
587 
588  uint64_t
589  getHtmTransactionUid() const override
590  {
591  assert(instFlags[HtmFromTransaction]);
592  return htmUid;
593  }
594 
595  uint64_t
596  newHtmTransactionUid() const override
597  {
598  panic("Not yet implemented\n");
599  return 0;
600  }
601 
602  bool
603  inHtmTransactionalState() const override
604  {
606  }
607 
608  uint64_t
609  getHtmTransactionalDepth() const override
610  {
612  return htmDepth;
613  else
614  return 0;
615  }
616 
617  void
618  setHtmTransactionalState(uint64_t htm_uid, uint64_t htm_depth)
619  {
621  htmUid = htm_uid;
622  htmDepth = htm_depth;
623  }
624 
625  void
627  {
628  if (inHtmTransactionalState()) {
629  DPRINTF(HtmCpu,
630  "clearing instuction's transactional state htmUid=%u\n",
632 
634  htmUid = -1;
635  htmDepth = 0;
636  }
637  }
638 
641 
644 
647 
650 
653 
656 
659 
666 
668  OpClass opClass() const { return staticInst->opClass(); }
669 
671  std::unique_ptr<PCStateBase>
672  branchTarget() const
673  {
674  return staticInst->branchTarget(*pc);
675  }
676 
678  size_t numSrcRegs() const { return numSrcs(); }
679 
681  size_t numDestRegs() const { return numDests(); }
682 
683  // the following are used to track physical register usage
684  // for machines with separate int & FP reg files
685  int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
686  int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
687  int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); }
688  int8_t numVecDestRegs() const { return staticInst->numVecDestRegs(); }
689  int8_t
691  {
692  return staticInst->numVecElemDestRegs();
693  }
694  int8_t
696  {
697  return staticInst->numVecPredDestRegs();
698  }
699 
701  const RegId& destRegIdx(int i) const { return staticInst->destRegIdx(i); }
702 
704  const RegId& srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
705 
707  uint8_t resultSize() { return instResult.size(); }
708 
712  InstResult
714  {
715  if (!instResult.empty()) {
716  InstResult t = instResult.front();
717  instResult.pop();
718  return t;
719  }
720  return dflt;
721  }
722 
725  template<typename T>
726  void
728  {
729  if (instFlags[RecordResult]) {
730  instResult.emplace(std::forward<T>(t));
731  }
732  }
736  void markSrcRegReady();
737 
739  void markSrcRegReady(RegIndex src_idx);
740 
742  void setCompleted() { status.set(Completed); }
743 
745  bool isCompleted() const { return status[Completed]; }
746 
749 
751  bool isResultReady() const { return status[ResultReady]; }
752 
754  void setCanIssue() { status.set(CanIssue); }
755 
757  bool readyToIssue() const { return status[CanIssue]; }
758 
760  void clearCanIssue() { status.reset(CanIssue); }
761 
763  void setIssued() { status.set(Issued); }
764 
766  bool isIssued() const { return status[Issued]; }
767 
769  void clearIssued() { status.reset(Issued); }
770 
772  void setExecuted() { status.set(Executed); }
773 
775  bool isExecuted() const { return status[Executed]; }
776 
778  void setCanCommit() { status.set(CanCommit); }
779 
781  void clearCanCommit() { status.reset(CanCommit); }
782 
784  bool readyToCommit() const { return status[CanCommit]; }
785 
786  void setAtCommit() { status.set(AtCommit); }
787 
788  bool isAtCommit() { return status[AtCommit]; }
789 
791  void setCommitted() { status.set(Committed); }
792 
794  bool isCommitted() const { return status[Committed]; }
795 
797  void setSquashed();
798 
800  bool isSquashed() const { return status[Squashed]; }
801 
802  //Instruction Queue Entry
803  //-----------------------
805  void setInIQ() { status.set(IqEntry); }
806 
808  void clearInIQ() { status.reset(IqEntry); }
809 
811  bool isInIQ() const { return status[IqEntry]; }
812 
815 
817  bool isSquashedInIQ() const { return status[SquashedInIQ]; }
818 
819 
820  //Load / Store Queue Functions
821  //-----------------------
823  void setInLSQ() { status.set(LsqEntry); }
824 
826  void removeInLSQ() { status.reset(LsqEntry); }
827 
829  bool isInLSQ() const { return status[LsqEntry]; }
830 
833 
835  bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
836 
837 
838  //Reorder Buffer Functions
839  //-----------------------
841  void setInROB() { status.set(RobEntry); }
842 
844  void clearInROB() { status.reset(RobEntry); }
845 
847  bool isInROB() const { return status[RobEntry]; }
848 
851 
853  bool isSquashedInROB() const { return status[SquashedInROB]; }
854 
856  bool isPinnedRegsRenamed() const { return status[PinnedRegsRenamed]; }
857 
859  void
861  {
862  assert(!status[PinnedRegsSquashDone]);
863  assert(!status[PinnedRegsWritten]);
865  }
866 
868  bool isPinnedRegsWritten() const { return status[PinnedRegsWritten]; }
869 
871  void
873  {
874  assert(!status[PinnedRegsSquashDone]);
875  assert(status[PinnedRegsRenamed]);
877  }
878 
880  bool
882  {
884  }
885 
887  void
889  {
890  assert(!status[PinnedRegsSquashDone]);
892  }
893 
895  const PCStateBase &
896  pcState() const override
897  {
898  return *pc;
899  }
900 
902  void pcState(const PCStateBase &val) override { set(pc, val); }
903 
904  bool readPredicate() const override { return instFlags[Predicate]; }
905 
906  void
907  setPredicate(bool val) override
908  {
910 
911  if (traceData) {
913  }
914  }
915 
916  bool
917  readMemAccPredicate() const override
918  {
919  return instFlags[MemAccPredicate];
920  }
921 
922  void
923  setMemAccPredicate(bool val) override
924  {
926  }
927 
929  void setTid(ThreadID tid) { threadNumber = tid; }
930 
932  void setThreadState(ThreadState *state) { thread = state; }
933 
935  gem5::ThreadContext *tcBase() const override { return thread->getTC(); }
936 
937  public:
939  bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; }
941 
943  bool hasRequest() const { return instFlags[ReqMade]; }
945  void setRequest() { instFlags[ReqMade] = true; }
946 
949 
951  void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
952 
953  public:
955  unsigned int
956  readStCondFailures() const override
957  {
958  return thread->storeCondFailures;
959  }
960 
962  void
963  setStCondFailures(unsigned int sc_failures) override
964  {
965  thread->storeCondFailures = sc_failures;
966  }
967 
968  public:
969  // monitor/mwait funtions
970  void
971  armMonitor(Addr address) override
972  {
973  cpu->armMonitor(threadNumber, address);
974  }
975  bool
976  mwait(PacketPtr pkt) override
977  {
978  return cpu->mwait(threadNumber, pkt);
979  }
980  void
982  {
983  return cpu->mwaitAtomic(threadNumber, tc, cpu->mmu);
984  }
985  AddressMonitor *
986  getAddrMonitor() override
987  {
988  return cpu->getCpuAddrMonitor(threadNumber);
989  }
990 
991  private:
992  // hardware transactional memory
993  uint64_t htmUid = -1;
994  uint64_t htmDepth = 0;
995 
996  public:
997 #if TRACING_ON
998  // Value -1 indicates that particular phase
999  // hasn't happened (yet).
1001  Tick fetchTick = -1; // instruction fetch is completed.
1002  int32_t decodeTick = -1; // instruction enters decode phase
1003  int32_t renameTick = -1; // instruction enters rename phase
1004  int32_t dispatchTick = -1;
1005  int32_t issueTick = -1;
1006  int32_t completeTick = -1;
1007  int32_t commitTick = -1;
1008  int32_t storeTick = -1;
1009 #endif
1010 
1011  /* Values used by LoadToUse stat */
1014 
1018  RegVal
1019  readMiscReg(int misc_reg) override
1020  {
1021  return cpu->readMiscReg(misc_reg, threadNumber);
1022  }
1023 
1027  void
1028  setMiscReg(int misc_reg, RegVal val) override
1029  {
1036  for (auto &idx: _destMiscRegIdx) {
1037  if (idx == misc_reg)
1038  return;
1039  }
1040 
1041  _destMiscRegIdx.push_back(misc_reg);
1042  _destMiscRegVal.push_back(val);
1043  }
1044 
1048  RegVal
1049  readMiscRegOperand(const StaticInst *si, int idx) override
1050  {
1051  const RegId& reg = si->srcRegIdx(idx);
1052  assert(reg.is(MiscRegClass));
1053  return cpu->readMiscReg(reg.index(), threadNumber);
1054  }
1055 
1059  void
1060  setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
1061  {
1062  const RegId& reg = si->destRegIdx(idx);
1063  assert(reg.is(MiscRegClass));
1064  setMiscReg(reg.index(), val);
1065  }
1066 
1068  void
1070  {
1071  // @todo: Pretty convoluted way to avoid squashing from happening when
1072  // using the TC during an instruction's execution (specifically for
1073  // instructions that have side-effects that use the TC). Fix this.
1074  // See cpu/o3/dyn_inst_impl.hh.
1075  bool no_squash_from_TC = thread->noSquashFromTC;
1076  thread->noSquashFromTC = true;
1077 
1078  for (int i = 0; i < _destMiscRegIdx.size(); i++)
1079  cpu->setMiscReg(
1081 
1082  thread->noSquashFromTC = no_squash_from_TC;
1083  }
1084 
1085  void
1087  {
1088 
1089  for (int idx = 0; idx < numDestRegs(); idx++) {
1090  PhysRegIdPtr prev_phys_reg = prevDestIdx(idx);
1091  const RegId& original_dest_reg = staticInst->destRegIdx(idx);
1092  switch (original_dest_reg.classValue()) {
1093  case IntRegClass:
1095  cpu->readIntReg(prev_phys_reg));
1096  break;
1097  case FloatRegClass:
1099  cpu->readFloatReg(prev_phys_reg));
1100  break;
1101  case VecRegClass:
1103  cpu->readVecReg(prev_phys_reg));
1104  break;
1105  case VecElemClass:
1107  cpu->readVecElem(prev_phys_reg));
1108  break;
1109  case VecPredRegClass:
1111  cpu->readVecPredReg(prev_phys_reg));
1112  break;
1113  case CCRegClass:
1115  cpu->readCCReg(prev_phys_reg));
1116  break;
1117  case MiscRegClass:
1118  // no need to forward misc reg values
1119  break;
1120  default:
1121  panic("Unknown register class: %d",
1122  (int)original_dest_reg.classValue());
1123  }
1124  }
1125  }
1127  void trap(const Fault &fault);
1128 
1129  public:
1130 
1131  // The register accessor methods provide the index of the
1132  // instruction's operand (e.g., 0 or 1), not the architectural
1133  // register index, to simplify the implementation of register
1134  // renaming. We find the architectural register index by indexing
1135  // into the instruction's own operand index table. Note that a
1136  // raw pointer to the StaticInst is provided instead of a
1137  // ref-counted StaticInstPtr to redice overhead. This is fine as
1138  // long as these methods don't copy the pointer into any long-term
1139  // storage (which is pretty hard to imagine they would have reason
1140  // to do).
1141 
1142  RegVal
1143  readIntRegOperand(const StaticInst *si, int idx) override
1144  {
1145  return cpu->readIntReg(renamedSrcIdx(idx));
1146  }
1147 
1148  RegVal
1149  readFloatRegOperandBits(const StaticInst *si, int idx) override
1150  {
1151  return cpu->readFloatReg(renamedSrcIdx(idx));
1152  }
1153 
1155  readVecRegOperand(const StaticInst *si, int idx) const override
1156  {
1157  return cpu->readVecReg(renamedSrcIdx(idx));
1158  }
1159 
1164  getWritableVecRegOperand(const StaticInst *si, int idx) override
1165  {
1166  return cpu->getWritableVecReg(renamedDestIdx(idx));
1167  }
1168 
1169  RegVal
1170  readVecElemOperand(const StaticInst *si, int idx) const override
1171  {
1172  return cpu->readVecElem(renamedSrcIdx(idx));
1173  }
1174 
1176  readVecPredRegOperand(const StaticInst *si, int idx) const override
1177  {
1178  return cpu->readVecPredReg(renamedSrcIdx(idx));
1179  }
1180 
1182  getWritableVecPredRegOperand(const StaticInst *si, int idx) override
1183  {
1185  }
1186 
1187  RegVal
1188  readCCRegOperand(const StaticInst *si, int idx) override
1189  {
1190  return cpu->readCCReg(renamedSrcIdx(idx));
1191  }
1192 
1196  void
1197  setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
1198  {
1199  cpu->setIntReg(renamedDestIdx(idx), val);
1200  setResult(val);
1201  }
1202 
1203  void
1204  setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
1205  {
1207  setResult(val);
1208  }
1209 
1210  void
1211  setVecRegOperand(const StaticInst *si, int idx,
1212  const TheISA::VecRegContainer& val) override
1213  {
1214  cpu->setVecReg(renamedDestIdx(idx), val);
1215  setResult(val);
1216  }
1217 
1218  void
1219  setVecElemOperand(const StaticInst *si, int idx, RegVal val) override
1220  {
1221  int reg_idx = idx;
1222  cpu->setVecElem(renamedDestIdx(reg_idx), val);
1223  setResult(val);
1224  }
1225 
1226  void
1228  const TheISA::VecPredRegContainer& val) override
1229  {
1231  setResult(val);
1232  }
1233 
1234  void
1235  setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
1236  {
1237  cpu->setCCReg(renamedDestIdx(idx), val);
1238  setResult(val);
1239  }
1240 };
1241 
1242 } // namespace o3
1243 } // namespace gem5
1244 
1245 #endif // __CPU_O3_DYN_INST_HH__
gem5::o3::DynInst::getInstListIt
ListIt & getInstListIt()
Returns iterator to this instruction in the list of all insts.
Definition: dyn_inst.hh:948
gem5::o3::DynInst::isInLSQ
bool isInLSQ() const
Returns whether or not this instruction is in the LSQ.
Definition: dyn_inst.hh:829
gem5::o3::DynInst::setSquashedInIQ
void setSquashedInIQ()
Sets this instruction as squashed in the IQ.
Definition: dyn_inst.hh:814
refcnt.hh
gem5::o3::CPU::setVecElem
void setVecElem(PhysRegIdPtr reg_idx, RegVal val)
Definition: cpu.cc:1167
gem5::o3::DynInst::PinnedRegsRenamed
@ PinnedRegsRenamed
Instruction is squashed in the ROB.
Definition: dyn_inst.hh:161
gem5::o3::DynInst::PinnedRegsSquashDone
@ PinnedRegsSquashDone
Pinned registers are written back.
Definition: dyn_inst.hh:163
gem5::o3::DynInst::isMicroop
bool isMicroop() const
Definition: dyn_inst.hh:578
gem5::o3::DynInst::ThreadsyncWait
@ ThreadsyncWait
Is a blocking instruction.
Definition: dyn_inst.hh:166
gem5::o3::DynInst::Arrays
Definition: dyn_inst.hh:86
gem5::o3::LSQ::LSQRequest
Memory operation metadata.
Definition: lsq.hh:189
gem5::PhysRegId::isPinned
bool isPinned() const
Definition: reg_class.hh:316
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::o3::DynInst::setMiscRegOperand
void setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
Sets a misc.
Definition: dyn_inst.hh:1060
gem5::StaticInst::isMicroop
bool isMicroop() const
Definition: static_inst.hh:207
gem5::StaticInst::isWriteBarrier
bool isWriteBarrier() const
Definition: static_inst.hh:201
gem5::StaticInst::isSerializeBefore
bool isSerializeBefore() const
Definition: static_inst.hh:192
gem5::o3::DynInst::predPC
std::unique_ptr< PCStateBase > predPC
Predicted PC state after this instruction.
Definition: dyn_inst.hh:324
gem5::o3::DynInst::Squashed
@ Squashed
Instruction has committed.
Definition: dyn_inst.hh:157
gem5::o3::DynInst::setVecRegOperand
void setVecRegOperand(const StaticInst *si, int idx, const TheISA::VecRegContainer &val) override
Sets a destination vector register operand to a value.
Definition: dyn_inst.hh:1211
gem5::o3::DynInst::initiateAcc
Fault initiateAcc()
Initiates the access.
Definition: dyn_inst.cc:356
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::o3::CPU::readCCReg
RegVal readCCReg(PhysRegIdPtr phys_reg)
Definition: cpu.cc:1139
gem5::o3::DynInst::setInIQ
void setInIQ()
Sets this instruction as a entry the IQ.
Definition: dyn_inst.hh:805
gem5::o3::DynInst::readySrcIdx
bool readySrcIdx(int idx) const
Definition: dyn_inst.hh:303
gem5::o3::DynInst::threadNumber
ThreadID threadNumber
The thread this instruction is from.
Definition: dyn_inst.hh:317
gem5::o3::DynInst::newHtmTransactionUid
uint64_t newHtmTransactionUid() const override
Definition: dyn_inst.hh:596
gem5::o3::DynInst::TranslationCompleted
@ TranslationCompleted
Definition: dyn_inst.hh:178
gem5::o3::CPU::mmu
BaseMMU * mmu
Definition: cpu.hh:111
gem5::ArmISA::VecPredRegContainer
VecPredReg::Container VecPredRegContainer
Definition: vec.hh:68
gem5::o3::DynInst::setCanCommit
void setCanCommit()
Sets this instruction as ready to commit.
Definition: dyn_inst.hh:778
op_class.hh
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::StaticInst::isNonSpeculative
bool isNonSpeculative() const
Definition: static_inst.hh:202
gem5::o3::DynInst::RecordResult
@ RecordResult
Definition: dyn_inst.hh:182
gem5::o3::DynInst::numSrcRegs
size_t numSrcRegs() const
Returns the number of source registers.
Definition: dyn_inst.hh:678
gem5::o3::DynInst::getCpuPtr
BaseCPU * getCpuPtr()
Definition: dyn_inst.hh:132
gem5::o3::DynInst::sqIt
LSQUnit::SQIterator sqIt
Definition: dyn_inst.hh:355
gem5::StaticInst::isQuiesce
bool isQuiesce() const
Definition: static_inst.hh:203
gem5::o3::DynInst::isCompleted
bool isCompleted() const
Returns whether or not this instruction is completed.
Definition: dyn_inst.hh:745
gem5::o3::DynInst::isMemRef
bool isMemRef() const
Definition: dyn_inst.hh:540
gem5::o3::DynInst::ListIt
std::list< DynInstPtr >::iterator ListIt
Definition: dyn_inst.hh:84
gem5::o3::DynInst::socketId
uint32_t socketId() const
Read this CPU's Socket ID.
Definition: dyn_inst.hh:492
gem5::o3::DynInst::isControl
bool isControl() const
Definition: dyn_inst.hh:551
gem5::o3::DynInst::HtmFromTransaction
@ HtmFromTransaction
Definition: dyn_inst.hh:189
gem5::o3::DynInst::renamedDestIdx
void renamedDestIdx(int idx, PhysRegIdPtr phys_reg_id)
Definition: dyn_inst.hh:269
gem5::o3::DynInst::savedRequest
LSQ::LSQRequest * savedRequest
Saved memory request (needed when the DTB address translation is delayed due to a hw page table walk)...
Definition: dyn_inst.hh:363
gem5::StaticInst::numCCDestRegs
int8_t numCCDestRegs() const
Number of coprocesor destination regs.
Definition: static_inst.hh:152
gem5::o3::DynInst::flattenedDestIdx
const RegId & flattenedDestIdx(int idx) const
Definition: dyn_inst.hh:246
gem5::VecElemClass
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:63
gem5::StaticInst::isIndirectCtrl
bool isIndirectCtrl() const
Definition: static_inst.hh:185
gem5::o3::DynInst::isQuiesce
bool isQuiesce() const
Definition: dyn_inst.hh:574
gem5::StaticInst::isUnverifiable
bool isUnverifiable() const
Definition: static_inst.hh:204
gem5::StaticInst::isNop
bool isNop() const
Definition: static_inst.hh:161
gem5::o3::DynInst::setCompleted
void setCompleted()
Sets this instruction as completed.
Definition: dyn_inst.hh:742
gem5::o3::DynInst::setCanIssue
void setCanIssue()
Sets this instruction as ready to issue.
Definition: dyn_inst.hh:754
gem5::StaticInst::isSerializeAfter
bool isSerializeAfter() const
Definition: static_inst.hh:193
gem5::o3::DynInst::isIssued
bool isIssued() const
Returns whether or not this instruction has issued.
Definition: dyn_inst.hh:766
gem5::o3::DynInst::memReqFlags
unsigned memReqFlags
The memory request flags (from translation).
Definition: dyn_inst.hh:341
gem5::o3::DynInst::setSerializeAfter
void setSerializeAfter()
Temporarily sets this instruction as a serialize after instruction.
Definition: dyn_inst.hh:649
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:65
gem5::o3::DynInst::Arrays::numSrcs
size_t numSrcs
Definition: dyn_inst.hh:88
gem5::o3::DynInst::isTranslationDelayed
bool isTranslationDelayed() const
Returns true if the DTB address translation is being delayed due to a hw page table walk.
Definition: dyn_inst.hh:449
gem5::StaticInst::isControl
bool isControl() const
Definition: static_inst.hh:181
gem5::o3::DynInst::setMiscReg
void setMiscReg(int misc_reg, RegVal val) override
Sets a misc.
Definition: dyn_inst.hh:1028
gem5::ArmISA::f
Bitfield< 6 > f
Definition: misc_types.hh:68
gem5::o3::DynInst::Arrays::flatDestIdx
RegId * flatDestIdx
Definition: dyn_inst.hh:91
gem5::o3::DynInst::instListIt
ListIt instListIt
Iterator pointing to this BaseDynInst in the list of all insts.
Definition: dyn_inst.hh:320
gem5::o3::DynInst::updateMiscRegs
void updateMiscRegs()
Called at the commit stage to update the misc.
Definition: dyn_inst.hh:1069
gem5::o3::DynInst::Arrays::srcIdx
PhysRegIdPtr * srcIdx
Definition: dyn_inst.hh:94
gem5::o3::DynInst::prevDestIdx
PhysRegIdPtr prevDestIdx(int idx) const
Definition: dyn_inst.hh:277
gem5::o3::DynInst::Arrays::prevDestIdx
PhysRegIdPtr * prevDestIdx
Definition: dyn_inst.hh:93
gem5::replaceBits
constexpr void replaceBits(T &val, unsigned first, unsigned last, B bit_val)
A convenience function to replace bits first to last of val with bit_val in place.
Definition: bitfield.hh:197
gem5::o3::DynInst::pc
std::unique_ptr< PCStateBase > pc
PC state for this instruction.
Definition: dyn_inst.hh:207
gem5::o3::DynInst::instResult
std::queue< InstResult > instResult
The result of the instruction; assumes an instruction can have many destination registers.
Definition: dyn_inst.hh:204
gem5::o3::DynInst::isInROB
bool isInROB() const
Returns whether or not this instruction is in the ROB.
Definition: dyn_inst.hh:847
gem5::o3::DynInst::cpuId
int cpuId() const
Read this CPU's ID.
Definition: dyn_inst.hh:489
gem5::o3::DynInst::isStoreConditional
bool isStoreConditional() const
Definition: dyn_inst.hh:544
gem5::o3::DynInst::TranslationStarted
@ TranslationStarted
Definition: dyn_inst.hh:177
gem5::o3::DynInst::setThreadState
void setThreadState(ThreadState *state)
Sets the pointer to the thread state.
Definition: dyn_inst.hh:932
gem5::o3::DynInst::isDirectCtrl
bool isDirectCtrl() const
Definition: dyn_inst.hh:554
gem5::o3::DynInst::isSquashedInIQ
bool isSquashedInIQ() const
Returns whether or not this instruction is squashed in the IQ.
Definition: dyn_inst.hh:817
gem5::o3::DynInst::possibleLoadViolation
void possibleLoadViolation(bool f)
Definition: dyn_inst.hh:432
gem5::o3::DynInst::getWritableVecRegOperand
TheISA::VecRegContainer & getWritableVecRegOperand(const StaticInst *si, int idx) override
Read destination vector register operand for modification.
Definition: dyn_inst.hh:1164
gem5::o3::DynInst::lqIt
LSQUnit::LQIterator lqIt
Definition: dyn_inst.hh:351
gem5::o3::DynInst::_destMiscRegIdx
std::vector< short > _destMiscRegIdx
Indexes of the destination misc.
Definition: dyn_inst.hh:216
gem5::o3::DynInst::readIntRegOperand
RegVal readIntRegOperand(const StaticInst *si, int idx) override
Reads an integer register.
Definition: dyn_inst.hh:1143
gem5::o3::DynInst::_readySrcIdx
uint8_t * _readySrcIdx
Definition: dyn_inst.hh:237
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::o3::DynInst::effSize
unsigned effSize
The size of the request.
Definition: dyn_inst.hh:344
gem5::o3::DynInst::isInstPrefetch
bool isInstPrefetch() const
Definition: dyn_inst.hh:546
exetrace.hh
gem5::o3::DynInst::SerializeHandled
@ SerializeHandled
Needs to serialize instructions behind it.
Definition: dyn_inst.hh:170
gem5::o3::CPU::readVecElem
RegVal readVecElem(PhysRegIdPtr reg_idx) const
Definition: cpu.cc:1118
gem5::o3::DynInst::setRequest
void setRequest()
Assert this instruction has generated a memory request.
Definition: dyn_inst.hh:945
gem5::o3::DynInst::status
std::bitset< NumStatus > status
The status of this BaseDynInst.
Definition: dyn_inst.hh:198
gem5::o3::DynInst::recordResult
void recordResult(bool f)
Records changes to result?
Definition: dyn_inst.hh:371
gem5::o3::DynInst::setCCRegOperand
void setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
Definition: dyn_inst.hh:1235
gem5::o3::DynInst::isSyscall
bool isSyscall() const
Definition: dyn_inst.hh:576
gem5::o3::DynInst::_numDests
size_t _numDests
Definition: dyn_inst.hh:219
gem5::StaticInst::isCondCtrl
bool isCondCtrl() const
Definition: static_inst.hh:186
gem5::o3::DynInst::getAddrMonitor
AddressMonitor * getAddrMonitor() override
Definition: dyn_inst.hh:986
gem5::o3::DynInst::instFlags
std::bitset< MaxFlags > instFlags
Definition: dyn_inst.hh:195
gem5::o3::DynInst::isNop
bool isNop() const
Definition: dyn_inst.hh:539
gem5::o3::DynInst::Completed
@ Completed
Instruction is in the LSQ.
Definition: dyn_inst.hh:149
gem5::o3::DynInst::isPinnedRegsRenamed
bool isPinnedRegsRenamed() const
Returns whether pinned registers are renamed.
Definition: dyn_inst.hh:856
gem5::o3::DynInst::seqNum
InstSeqNum seqNum
The sequence number of the instruction.
Definition: dyn_inst.hh:124
gem5::o3::DynInst::branchTarget
std::unique_ptr< PCStateBase > branchTarget() const
Returns the branch target address.
Definition: dyn_inst.hh:672
gem5::o3::DynInst::Arrays::destIdx
PhysRegIdPtr * destIdx
Definition: dyn_inst.hh:92
gem5::o3::DynInst::renameSrcReg
void renameSrcReg(int idx, PhysRegIdPtr renamed_src)
Renames a source logical register to the physical register which has/will produce that logical regist...
Definition: dyn_inst.hh:477
gem5::o3::DynInst::doneTargCalc
bool doneTargCalc()
Checks whether or not this instruction has had its branch target calculated yet.
Definition: dyn_inst.hh:511
gem5::o3::DynInst::getHtmTransactionUid
uint64_t getHtmTransactionUid() const override
Definition: dyn_inst.hh:589
gem5::o3::CPU::setVecReg
void setVecReg(PhysRegIdPtr reg_idx, const TheISA::VecRegContainer &val)
Definition: cpu.cc:1160
gem5::o3::DynInst::tcBase
gem5::ThreadContext * tcBase() const override
Returns the thread context.
Definition: dyn_inst.hh:935
std::vector< RegVal >
gem5::o3::DynInst::RecoverInst
@ RecoverInst
Regs pinning status updated after squash.
Definition: dyn_inst.hh:164
gem5::o3::CPU::setMiscReg
void setMiscReg(int misc_reg, RegVal val, ThreadID tid)
Sets a misc.
Definition: cpu.cc:1083
gem5::o3::CPU::getWritableVecPredReg
TheISA::VecPredRegContainer & getWritableVecPredReg(PhysRegIdPtr reg_idx)
Definition: cpu.cc:1132
gem5::StaticInst::isDelayedCommit
bool isDelayedCommit() const
Definition: static_inst.hh:208
gem5::Trace::InstRecord::setPredicate
void setPredicate(bool val)
Definition: insttracer.hh:230
gem5::RefCountingPtr::get
T * get() const
Directly access the pointer itself without taking a reference.
Definition: refcnt.hh:227
gem5::o3::DynInst::numDestRegs
size_t numDestRegs() const
Returns the number of destination registers.
Definition: dyn_inst.hh:681
gem5::StaticInst::numVecDestRegs
int8_t numVecDestRegs() const
Number of vector destination regs.
Definition: static_inst.hh:146
gem5::o3::DynInst::isTempSerializeAfter
bool isTempSerializeAfter()
Checks if this serializeAfter is only temporarily set.
Definition: dyn_inst.hh:655
gem5::o3::DynInst::translationStarted
void translationStarted(bool f)
Definition: dyn_inst.hh:411
gem5::o3::DynInst::isCommitted
bool isCommitted() const
Returns whether or not this instruction is committed.
Definition: dyn_inst.hh:794
gem5::o3::DynInst::pcState
const PCStateBase & pcState() const override
Read the PC state of this instruction.
Definition: dyn_inst.hh:896
gem5::o3::DynInst::notAnInst
bool notAnInst() const
Definition: dyn_inst.hh:381
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::StaticInst::isFirstMicroop
bool isFirstMicroop() const
Definition: static_inst.hh:210
gem5::o3::DynInst::_prevDestIdx
PhysRegIdPtr * _prevDestIdx
Definition: dyn_inst.hh:231
gem5::o3::DynInst::setResultReady
void setResultReady()
Marks the result as ready.
Definition: dyn_inst.hh:748
gem5::o3::DynInst::Predicate
@ Predicate
Definition: dyn_inst.hh:183
gem5::o3::DynInst::setPinnedRegsWritten
void setPinnedRegsWritten()
Sets destination registers as written.
Definition: dyn_inst.hh:872
inst_res.hh
gem5::o3::CPU::readFloatReg
RegVal readFloatReg(PhysRegIdPtr phys_reg)
Definition: cpu.cc:1097
gem5::o3::DynInst::ReqMade
@ ReqMade
Definition: dyn_inst.hh:187
gem5::o3::DynInst::setNotAnInst
void setNotAnInst()
Definition: dyn_inst.hh:382
gem5::o3::DynInst::SquashedInLSQ
@ SquashedInLSQ
Instruction is squashed in the IQ.
Definition: dyn_inst.hh:159
gem5::StaticInst::advancePC
virtual void advancePC(PCStateBase &pc_state) const =0
gem5::StaticInst::destRegIdx
const RegId & destRegIdx(int i) const
Return logical index (architectural reg num) of i'th destination reg.
Definition: static_inst.hh:236
gem5::o3::DynInst::setAtCommit
void setAtCommit()
Definition: dyn_inst.hh:786
gem5::o3::DynInst::thread
ThreadState * thread
Pointer to the thread state.
Definition: dyn_inst.hh:135
gem5::o3::DynInst::numVecPredDestRegs
int8_t numVecPredDestRegs() const
Definition: dyn_inst.hh:695
gem5::o3::DynInst::MemAccPredicate
@ MemAccPredicate
Definition: dyn_inst.hh:184
gem5::o3::DynInst::setHtmTransactionalState
void setHtmTransactionalState(uint64_t htm_uid, uint64_t htm_depth)
Definition: dyn_inst.hh:618
gem5::o3::CPU::demapPage
void demapPage(Addr vaddr, uint64_t asn)
Definition: cpu.hh:181
gem5::o3::DynInst::readMemAccPredicate
bool readMemAccPredicate() const override
Definition: dyn_inst.hh:917
gem5::o3::DynInst::readPredTarg
const PCStateBase & readPredTarg()
Definition: dyn_inst.hh:516
gem5::o3::DynInst::translationStarted
bool translationStarted() const
True if the DTB address translation has started.
Definition: dyn_inst.hh:410
gem5::o3::DynInst::IqEntry
@ IqEntry
Definition: dyn_inst.hh:146
gem5::o3::DynInst::hasRequest
bool hasRequest() const
Has this instruction generated a memory request.
Definition: dyn_inst.hh:943
gem5::VecPredRegClass
@ VecPredRegClass
Definition: reg_class.hh:64
gem5::o3::DynInst::clearInROB
void clearInROB()
Sets this instruction as a entry the ROB.
Definition: dyn_inst.hh:844
gem5::o3::DynInst::popResult
InstResult popResult(InstResult dflt=InstResult())
Pops a result off the instResult queue.
Definition: dyn_inst.hh:713
gem5::o3::DynInst::numVecElemDestRegs
int8_t numVecElemDestRegs() const
Definition: dyn_inst.hh:690
gem5::o3::DynInst::isInIQ
bool isInIQ() const
Returns whether or not this instruction has issued.
Definition: dyn_inst.hh:811
gem5::RefCountingPtr< StaticInst >
gem5::o3::DynInst::possibleLoadViolation
bool possibleLoadViolation() const
True if this address was found to match a previous load and they issued out of order.
Definition: dyn_inst.hh:427
gem5::o3::DynInst::readyToCommit
bool readyToCommit() const
Returns whether or not this instruction is ready to commit.
Definition: dyn_inst.hh:784
gem5::o3::DynInst::~DynInst
~DynInst()
Definition: dyn_inst.cc:190
gem5::o3::DynInst::dump
void dump()
Dumps out contents of this BaseDynInst.
Definition: dyn_inst.cc:278
gem5::StaticInst::numVecPredDestRegs
int8_t numVecPredDestRegs() const
Number of predicate destination regs.
Definition: static_inst.hh:150
gem5::o3::DynInst::physEffAddr
Addr physEffAddr
The effective physical address.
Definition: dyn_inst.hh:338
gem5::o3::DynInst::cpu
CPU * cpu
Pointer to the Impl's CPU object.
Definition: dyn_inst.hh:130
gem5::StaticInst::numVecElemDestRegs
int8_t numVecElemDestRegs() const
Number of vector element destination regs.
Definition: static_inst.hh:148
gem5::StaticInst::numFPDestRegs
int8_t numFPDestRegs() const
Number of floating-point destination regs.
Definition: static_inst.hh:142
gem5::StaticInst::opClass
OpClass opClass() const
Operation class. Used to select appropriate function unit in issue.
Definition: static_inst.hh:231
gem5::o3::DynInst::readVecRegOperand
const TheISA::VecRegContainer & readVecRegOperand(const StaticInst *si, int idx) const override
Vector Register Interfaces.
Definition: dyn_inst.hh:1155
gem5::o3::DynInst::readyToIssue
bool readyToIssue() const
Returns whether or not this instruction is ready to issue.
Definition: dyn_inst.hh:757
gem5::o3::DynInst::setInstListIt
void setInstListIt(ListIt _instListIt)
Sets iterator for this instruction in the list of all insts.
Definition: dyn_inst.hh:951
gem5::o3::DynInst::markSrcRegReady
void markSrcRegReady()
Records that one of the source registers is ready.
Definition: dyn_inst.cc:296
gem5::o3::DynInst::setExecuted
void setExecuted()
Sets this instruction as executed.
Definition: dyn_inst.hh:772
gem5::StaticInst::isHtmCancel
bool isHtmCancel() const
Definition: static_inst.hh:216
gem5::o3::DynInst::readCCRegOperand
RegVal readCCRegOperand(const StaticInst *si, int idx) override
Definition: dyn_inst.hh:1188
gem5::StaticInst::isFloating
bool isFloating() const
Definition: static_inst.hh:178
gem5::o3::DynInst::EffAddrValid
@ EffAddrValid
Definition: dyn_inst.hh:181
gem5::o3::ThreadState::getTC
gem5::ThreadContext * getTC()
Returns a pointer to the TC of this thread.
Definition: thread_state.hh:103
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:59
gem5::StaticInst::isHtmCmd
bool isHtmCmd() const
Definition: static_inst.hh:219
gem5::o3::DynInst::setVecPredRegOperand
void setVecPredRegOperand(const StaticInst *si, int idx, const TheISA::VecPredRegContainer &val) override
Sets a destination predicate register operand to a value.
Definition: dyn_inst.hh:1227
gem5::o3::DynInst::numSrcs
size_t numSrcs() const
Definition: dyn_inst.hh:240
gem5::Flags< FlagsType >
gem5::o3::CPU::getWritableVecReg
TheISA::VecRegContainer & getWritableVecReg(PhysRegIdPtr reg_idx)
Read physical vector register for modification.
Definition: cpu.cc:1111
gem5::StaticInst::isReturn
bool isReturn() const
Definition: static_inst.hh:183
gem5::o3::DynInst::Committed
@ Committed
Instruction has reached commit.
Definition: dyn_inst.hh:156
gem5::o3::DynInst::prevDestIdx
void prevDestIdx(int idx, PhysRegIdPtr phys_reg_id)
Definition: dyn_inst.hh:284
gem5::o3::DynInst::destRegIdx
const RegId & destRegIdx(int i) const
Returns the logical register index of the i'th destination register.
Definition: dyn_inst.hh:701
gem5::o3::DynInst::renamedSrcIdx
void renamedSrcIdx(int idx, PhysRegIdPtr phys_reg_id)
Definition: dyn_inst.hh:297
gem5::o3::DynInst::readPredTaken
bool readPredTaken()
Returns whether the instruction was predicted taken or not.
Definition: dyn_inst.hh:519
gem5::ArmISA::b
Bitfield< 7 > b
Definition: misc_types.hh:382
gem5::StaticInst::isHtmStart
bool isHtmStart() const
Definition: static_inst.hh:214
gem5::StaticInst::isDataPrefetch
bool isDataPrefetch() const
Definition: static_inst.hh:173
inst_seq.hh
gem5::o3::CPU
O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buff...
Definition: cpu.hh:94
gem5::o3::CPU::setCCReg
void setCCReg(PhysRegIdPtr phys_reg, RegVal val)
Definition: cpu.cc:1182
translation.hh
gem5::StaticInst
Base, ISA-independent static instruction class.
Definition: static_inst.hh:87
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::o3::DynInst::sqIdx
ssize_t sqIdx
Store queue index.
Definition: dyn_inst.hh:354
gem5::o3::DynInst::readMiscReg
RegVal readMiscReg(int misc_reg) override
Reads a misc.
Definition: dyn_inst.hh:1019
gem5::o3::DynInst::isSerializeHandled
bool isSerializeHandled()
Checks if the serialization part of this instruction has been handled.
Definition: dyn_inst.hh:665
gem5::o3::DynInst::isFloating
bool isFloating() const
Definition: dyn_inst.hh:549
gem5::o3::CPU::setIntReg
void setIntReg(PhysRegIdPtr phys_reg, RegVal val)
Definition: cpu.cc:1146
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::o3::DynInst::trap
void trap(const Fault &fault)
Traps to handle specified fault.
Definition: dyn_inst.cc:396
gem5::o3::DynInst::setPinnedRegsSquashDone
void setPinnedRegsSquashDone()
Sets dest registers' status updated after squash.
Definition: dyn_inst.hh:888
gem5::StaticInst::srcRegIdx
const RegId & srcRegIdx(int i) const
Return logical index (architectural reg num) of i'th source reg.
Definition: static_inst.hh:246
gem5::o3::DynInst::setFloatRegOperandBits
void setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
Sets the bits of a floating point register of single width to a binary value.
Definition: dyn_inst.hh:1204
gem5::o3::DynInst::setIntRegOperand
void setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
Definition: dyn_inst.hh:1197
gem5::o3::DynInst::pcState
void pcState(const PCStateBase &val) override
Set the PC state of this instruction.
Definition: dyn_inst.hh:902
gem5::StaticInst::isAtomic
bool isAtomic() const
Definition: static_inst.hh:170
gem5::o3::DynInst::setTid
void setTid(ThreadID tid)
Sets the thread id.
Definition: dyn_inst.hh:929
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::o3::DynInst::renameDestReg
void renameDestReg(int idx, PhysRegIdPtr renamed_dest, PhysRegIdPtr previous_rename)
Renames a destination register to a physical register.
Definition: dyn_inst.hh:463
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::o3::DynInst::execute
Fault execute()
Executes the instruction.
Definition: dyn_inst.cc:339
gem5::ThreadState::storeCondFailures
unsigned storeCondFailures
Definition: thread_state.hh:138
gem5::o3::DynInst::htmUid
uint64_t htmUid
Definition: dyn_inst.hh:993
gem5::probing::Packet
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:109
gem5::o3::DynInst::removeInLSQ
void removeInLSQ()
Sets this instruction as a entry the LSQ.
Definition: dyn_inst.hh:826
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::StaticInst::isHtmStop
bool isHtmStop() const
Definition: static_inst.hh:215
gem5::o3::DynInst::numIntDestRegs
int8_t numIntDestRegs() const
Definition: dyn_inst.hh:686
gem5::o3::DynInst::isSquashedInROB
bool isSquashedInROB() const
Returns whether or not this instruction is squashed in the ROB.
Definition: dyn_inst.hh:853
gem5::o3::DynInst::isResultReady
bool isResultReady() const
Returns whether or not the result is ready.
Definition: dyn_inst.hh:751
gem5::o3::DynInst::requestorId
RequestorID requestorId() const
Read this CPU's data requestor ID.
Definition: dyn_inst.hh:495
cpu.hh
gem5::o3::DynInst::setInLSQ
void setInLSQ()
Sets this instruction as a entry the LSQ.
Definition: dyn_inst.hh:823
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::o3::DynInst::armMonitor
void armMonitor(Addr address) override
Definition: dyn_inst.hh:971
gem5::o3::CPU::readIntReg
RegVal readIntReg(PhysRegIdPtr phys_reg)
Definition: cpu.cc:1090
gem5::o3::DynInst::isLastMicroop
bool isLastMicroop() const
Definition: dyn_inst.hh:580
gem5::o3::DynInst::SerializeAfter
@ SerializeAfter
Needs to serialize on instructions ahead of it.
Definition: dyn_inst.hh:169
gem5::o3::DynInst::lastWakeDependents
Tick lastWakeDependents
Definition: dyn_inst.hh:1013
gem5::RefCounted::count
int count
Definition: refcnt.hh:67
gem5::o3::DynInst::contextId
ContextID contextId() const
Read this context's system-wide ID.
Definition: dyn_inst.hh:498
gem5::o3::DynInst::isUnverifiable
bool isUnverifiable() const
Definition: dyn_inst.hh:575
gem5::o3::DynInst::staticInst
const StaticInstPtr staticInst
The StaticInst used by this BaseDynInst.
Definition: dyn_inst.hh:127
gem5::o3::DynInst::setCommitted
void setCommitted()
Sets this instruction as committed.
Definition: dyn_inst.hh:791
gem5::o3::DynInst::IsStrictlyOrdered
@ IsStrictlyOrdered
Definition: dyn_inst.hh:186
gem5::StaticInst::isLoad
bool isLoad() const
Definition: static_inst.hh:168
gem5::o3::DynInst::numFPDestRegs
int8_t numFPDestRegs() const
Definition: dyn_inst.hh:685
gem5::o3::DynInst::numCCDestRegs
int8_t numCCDestRegs() const
Definition: dyn_inst.hh:687
gem5::StaticInst::isStore
bool isStore() const
Definition: static_inst.hh:169
gem5::o3::DynInst::readFloatRegOperandBits
RegVal readFloatRegOperandBits(const StaticInst *si, int idx) override
Reads a floating point register in its binary format, instead of by value.
Definition: dyn_inst.hh:1149
gem5::o3::DynInst::MaxFlags
@ MaxFlags
Definition: dyn_inst.hh:190
gem5::o3::DynInst::isSquashAfter
bool isSquashAfter() const
Definition: dyn_inst.hh:569
gem5::o3::CPU::readVecReg
const TheISA::VecRegContainer & readVecReg(PhysRegIdPtr reg_idx) const
Definition: cpu.cc:1104
gem5::o3::DynInst::hitExternalSnoop
void hitExternalSnoop(bool f)
Definition: dyn_inst.hh:442
gem5::o3::DynInst::isFullMemBarrier
bool isFullMemBarrier() const
Definition: dyn_inst.hh:570
gem5::ArmISA::VecRegContainer
gem5::VecRegContainer< NumVecElemPerVecReg *sizeof(VecElem)> VecRegContainer
Definition: vec.hh:62
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::o3::DynInst::readyRegs
uint8_t readyRegs
How many source registers are ready.
Definition: dyn_inst.hh:330
static_inst.hh
gem5::o3::DynInst::setPredTaken
void setPredTaken(bool predicted_taken)
Definition: dyn_inst.hh:522
gem5::o3::DynInst::isInteger
bool isInteger() const
Definition: dyn_inst.hh:548
gem5::o3::DynInst::writeMem
Fault writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable) override
Definition: dyn_inst.cc:423
gem5::StaticInst::isDirectCtrl
bool isDirectCtrl() const
Definition: static_inst.hh:184
gem5::StaticInst::isVector
bool isVector() const
Definition: static_inst.hh:179
gem5::o3::DynInst::RobEntry
@ RobEntry
Instruction is in the IQ.
Definition: dyn_inst.hh:147
gem5::o3::DynInst::isMacroop
bool isMacroop() const
Definition: dyn_inst.hh:577
gem5::o3::LSQUnit::LQIterator
CircularQueue< LQEntry >::iterator LQIterator
Definition: lsq_unit.hh:561
gem5::o3::DynInst::ResultReady
@ ResultReady
Instruction has completed.
Definition: dyn_inst.hh:150
gem5::RegId::classValue
RegClassType classValue() const
Class accessor.
Definition: reg_class.hh:206
gem5::o3::DynInst::PinnedRegsWritten
@ PinnedRegsWritten
Pinned registers are renamed.
Definition: dyn_inst.hh:162
gem5::ArmISA::t
Bitfield< 5 > t
Definition: misc_types.hh:71
gem5::StaticInst::numIntDestRegs
int8_t numIntDestRegs() const
Number of integer destination regs.
Definition: static_inst.hh:144
gem5::o3::DynInst::translationCompleted
bool translationCompleted() const
True if the DTB address translation has completed.
Definition: dyn_inst.hh:415
gem5::o3::DynInst::clearCanIssue
void clearCanIssue()
Clears this instruction being able to issue.
Definition: dyn_inst.hh:760
gem5::o3::DynInst::Arrays::readySrcIdx
uint8_t * readySrcIdx
Definition: dyn_inst.hh:95
gem5::o3::DynInst::readPredicate
bool readPredicate() const override
Definition: dyn_inst.hh:904
gem5::ArmISA::si
Bitfield< 6 > si
Definition: misc_types.hh:773
gem5::o3::DynInst::isFirstMicroop
bool isFirstMicroop() const
Definition: dyn_inst.hh:581
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::o3::DynInst::isHtmStop
bool isHtmStop() const
Definition: dyn_inst.hh:584
dyn_inst_ptr.hh
gem5::o3::DynInst::DynInst
DynInst(const StaticInstPtr &staticInst, const StaticInstPtr &macroop, InstSeqNum seq_num, CPU *cpu)
gem5::o3::DynInst::isCall
bool isCall() const
Definition: dyn_inst.hh:552
gem5::o3::DynInst::isAtCommit
bool isAtCommit()
Definition: dyn_inst.hh:788
gem5::o3::DynInst::setSerializeBefore
void setSerializeBefore()
Temporarily sets this instruction as a serialize before instruction.
Definition: dyn_inst.hh:640
gem5::o3::DynInst::_destMiscRegVal
std::vector< RegVal > _destMiscRegVal
Values to be written to the destination misc.
Definition: dyn_inst.hh:210
gem5::o3::DynInst::opClass
OpClass opClass() const
Returns the opclass of this instruction.
Definition: dyn_inst.hh:668
gem5::StaticInst::isLastMicroop
bool isLastMicroop() const
Definition: static_inst.hh:209
gem5::o3::DynInst::isSquashedInLSQ
bool isSquashedInLSQ() const
Returns whether or not this instruction is squashed in the LSQ.
Definition: dyn_inst.hh:835
gem5::o3::DynInst::setSerializeHandled
void setSerializeHandled()
Sets the serialization part of this instruction as handled.
Definition: dyn_inst.hh:658
gem5::o3::LSQUnit::SQIterator
CircularQueue< SQEntry >::iterator SQIterator
Definition: lsq_unit.hh:562
gem5::o3::DynInst::isLoad
bool isLoad() const
Definition: dyn_inst.hh:541
gem5::StaticInst::isMemRef
bool isMemRef() const
Definition: static_inst.hh:164
gem5::o3::DynInst::completeAcc
Fault completeAcc(PacketPtr pkt)
Completes the access.
Definition: dyn_inst.cc:373
gem5::PowerISA::so
Bitfield< 28 > so
Definition: misc.hh:54
gem5::o3::DynInst::mispredicted
bool mispredicted()
Returns whether the instruction mispredicted.
Definition: dyn_inst.hh:529
gem5::o3::DynInst::Executed
@ Executed
Instruction has issued.
Definition: dyn_inst.hh:153
gem5::o3::DynInst::setSquashed
void setSquashed()
Sets this instruction as squashed.
Definition: dyn_inst.cc:314
gem5::o3::DynInst::isSerializing
bool isSerializing() const
Definition: dyn_inst.hh:558
gem5::o3::DynInst::mwait
bool mwait(PacketPtr pkt) override
Definition: dyn_inst.hh:976
gem5::o3::DynInst::inHtmTransactionalState
bool inHtmTransactionalState() const override
Definition: dyn_inst.hh:603
gem5::o3::DynInst::NumStatus
@ NumStatus
Serialization has been handled.
Definition: dyn_inst.hh:171
gem5::ThreadState::contextId
ContextID contextId() const
Definition: thread_state.hh:63
gem5::o3::DynInst::_srcIdx
PhysRegIdPtr * _srcIdx
Definition: dyn_inst.hh:234
gem5::o3::DynInst::readVecElemOperand
RegVal readVecElemOperand(const StaticInst *si, int idx) const override
Vector Elem Interfaces.
Definition: dyn_inst.hh:1170
gem5::o3::CPU::setFloatReg
void setFloatReg(PhysRegIdPtr phys_reg, RegVal val)
Definition: cpu.cc:1153
gem5::o3::CPU::setVecPredReg
void setVecPredReg(PhysRegIdPtr reg_idx, const TheISA::VecPredRegContainer &val)
Definition: cpu.cc:1174
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::o3::DynInst::Issued
@ Issued
Instruction can issue and execute.
Definition: dyn_inst.hh:152
gem5::o3::ThreadState::noSquashFromTC
bool noSquashFromTC
Definition: thread_state.hh:84
gem5::o3::DynInst::clearSerializeAfter
void clearSerializeAfter()
Clears the serializeAfter part of this instruction.
Definition: dyn_inst.hh:652
gem5::o3::DynInst::isPinnedRegsSquashDone
bool isPinnedRegsSquashDone() const
Return whether dest registers' pinning status updated after squash.
Definition: dyn_inst.hh:881
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:58
gem5::StaticInst::isReadBarrier
bool isReadBarrier() const
Definition: static_inst.hh:200
gem5::o3::ThreadState
Class that has various thread state, such as the status, the current instruction being processed,...
Definition: thread_state.hh:66
gem5::o3::DynInst::initiateMemAMO
Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override
Definition: dyn_inst.cc:435
gem5::RefCounted
Derive from RefCounted if you want to enable reference counting of this class.
Definition: refcnt.hh:60
gem5::o3::DynInst::isTempSerializeBefore
bool isTempSerializeBefore()
Checks if this serializeBefore is only temporarily set.
Definition: dyn_inst.hh:646
gem5::o3::DynInst::strictlyOrdered
bool strictlyOrdered() const
Is this instruction's memory access strictly ordered?
Definition: dyn_inst.hh:939
gem5::o3::DynInst::isReturn
bool isReturn() const
Definition: dyn_inst.hh:553
gem5::o3::DynInst::resultSize
uint8_t resultSize()
Return the size of the instResult queue.
Definition: dyn_inst.hh:707
gem5::o3::DynInst::getFault
Fault & getFault()
TODO: This I added for the LSQRequest side to be able to modify the fault.
Definition: dyn_inst.hh:504
gem5::o3::DynInst::setResult
void setResult(T &&t)
Pushes a result onto the instResult queue.
Definition: dyn_inst.hh:727
gem5::o3::DynInst::isNonSpeculative
bool isNonSpeculative() const
Definition: dyn_inst.hh:573
gem5::StaticInst::isInstPrefetch
bool isInstPrefetch() const
Definition: static_inst.hh:172
gem5::o3::DynInst::flattenedDestIdx
void flattenedDestIdx(int idx, const RegId &reg_id)
Definition: dyn_inst.hh:254
gem5::o3::DynInst::clearInIQ
void clearInIQ()
Sets this instruction as a entry the IQ.
Definition: dyn_inst.hh:808
gem5::o3::DynInst::HitExternalSnoop
@ HitExternalSnoop
Definition: dyn_inst.hh:180
gem5::o3::DynInst::getHtmTransactionalDepth
uint64_t getHtmTransactionalDepth() const override
Definition: dyn_inst.hh:609
gem5::o3::DynInst::clearSerializeBefore
void clearSerializeBefore()
Clears the serializeBefore part of this instruction.
Definition: dyn_inst.hh:643
gem5::o3::DynInst::setPredTarg
void setPredTarg(const PCStateBase &pred_pc)
Set the predicted target of this current instruction.
Definition: dyn_inst.hh:514
gem5::o3::DynInst::SquashedInROB
@ SquashedInROB
Instruction is squashed in the LSQ.
Definition: dyn_inst.hh:160
gem5::o3::DynInst::translationCompleted
void translationCompleted(bool f)
Definition: dyn_inst.hh:419
gem5::o3::DynInst::Flags
Flags
Definition: dyn_inst.hh:174
gem5::o3::DynInst::CanCommit
@ CanCommit
Instruction has executed.
Definition: dyn_inst.hh:154
gem5::o3::DynInst::readMiscRegOperand
RegVal readMiscRegOperand(const StaticInst *si, int idx) override
Reads a misc.
Definition: dyn_inst.hh:1049
gem5::MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:66
gem5::o3::DynInst::readySrcIdx
void readySrcIdx(int idx, bool ready)
Definition: dyn_inst.hh:310
gem5::o3::DynInst::SerializeBefore
@ SerializeBefore
Is a thread synchronization instruction.
Definition: dyn_inst.hh:167
gem5::o3::DynInst::AtCommit
@ AtCommit
Instruction can commit.
Definition: dyn_inst.hh:155
gem5::o3::DynInst::clearHtmTransactionalState
void clearHtmTransactionalState()
Definition: dyn_inst.hh:626
gem5::o3::DynInst::mwaitAtomic
void mwaitAtomic(gem5::ThreadContext *tc) override
Definition: dyn_inst.hh:981
gem5::o3::DynInst::isDataPrefetch
bool isDataPrefetch() const
Definition: dyn_inst.hh:547
gem5::o3::DynInst::getFault
Fault getFault() const
Returns the fault type.
Definition: dyn_inst.hh:501
gem5::o3::DynInst::MemOpDone
@ MemOpDone
Definition: dyn_inst.hh:188
gem5::o3::DynInst::setSquashedInLSQ
void setSquashedInLSQ()
Sets this instruction as squashed in the LSQ.
Definition: dyn_inst.hh:832
gem5::StaticInst::isMacroop
bool isMacroop() const
Definition: static_inst.hh:206
gem5::o3::DynInst::getWritableVecPredRegOperand
TheISA::VecPredRegContainer & getWritableVecPredRegOperand(const StaticInst *si, int idx) override
Gets destination predicate register operand for modification.
Definition: dyn_inst.hh:1182
gem5::o3::DynInst::isCondCtrl
bool isCondCtrl() const
Definition: dyn_inst.hh:556
gem5::StaticInst::isSquashAfter
bool isSquashAfter() const
Definition: static_inst.hh:194
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:246
gem5::o3::DynInst::isStore
bool isStore() const
Definition: dyn_inst.hh:542
exec_context.hh
gem5::o3::DynInst::clearIssued
void clearIssued()
Clears this instruction as being issued.
Definition: dyn_inst.hh:769
gem5::o3::DynInst::srcRegIdx
const RegId & srcRegIdx(int i) const
Returns the logical register index of the i'th source register.
Definition: dyn_inst.hh:704
reg_class.hh
gem5::o3::DynInst::traceData
Trace::InstRecord * traceData
InstRecord that tracks this instructions.
Definition: dyn_inst.hh:141
gem5::StaticInst::isSerializing
bool isSerializing() const
Definition: static_inst.hh:189
lsq_unit.hh
gem5::o3::CPU::readMiscReg
RegVal readMiscReg(int misc_reg, ThreadID tid)
Reads a misc.
Definition: cpu.cc:1070
gem5::StaticInst::isInteger
bool isInteger() const
Definition: static_inst.hh:177
gem5::o3::DynInst::setPinnedRegsRenamed
void setPinnedRegsRenamed()
Sets the destination registers as renamed.
Definition: dyn_inst.hh:860
gem5::o3::DynInst::initiateMemRead
Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable) override
Definition: dyn_inst.cc:402
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:73
gem5::StaticInst::isCall
bool isCall() const
Definition: static_inst.hh:182
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::o3::DynInst::setIssued
void setIssued()
Sets this instruction as issued from the IQ.
Definition: dyn_inst.hh:763
gem5::StaticInst::branchTarget
virtual std::unique_ptr< PCStateBase > branchTarget(const PCStateBase &pc) const
Return the target address for a PC-relative branch.
Definition: static_inst.cc:46
gem5::PhysRegId
Physical register ID.
Definition: reg_class.hh:224
gem5::o3::DynInst::NotAnInst
@ NotAnInst
Definition: dyn_inst.hh:176
gem5::o3::DynInst::memOpDone
bool memOpDone() const
Whether or not the memory operation is done.
Definition: dyn_inst.hh:378
gem5::o3::DynInst::isWriteBarrier
bool isWriteBarrier() const
Definition: dyn_inst.hh:572
gem5::o3::DynInst::initiateHtmCmd
Fault initiateHtmCmd(Request::Flags flags) override
Initiate an HTM command, e.g.
Definition: dyn_inst.cc:413
gem5::o3::DynInst::isExecuted
bool isExecuted() const
Returns whether or not this instruction has executed.
Definition: dyn_inst.hh:775
gem5::o3::DynInst::clearCanCommit
void clearCanCommit()
Clears this instruction as being ready to commit.
Definition: dyn_inst.hh:781
gem5::o3::DynInst::isPinnedRegsWritten
bool isPinnedRegsWritten() const
Returns whether destination registers are written.
Definition: dyn_inst.hh:868
gem5::o3::DynInst::PossibleLoadViolation
@ PossibleLoadViolation
Definition: dyn_inst.hh:179
gem5::o3::DynInst::macroop
const StaticInstPtr macroop
The Macroop if one exists.
Definition: dyn_inst.hh:327
gem5::o3::DynInst::setVecElemOperand
void setVecElemOperand(const StaticInst *si, int idx, RegVal val) override
Sets a vector register to a value.
Definition: dyn_inst.hh:1219
gem5::o3::DynInst::isIndirectCtrl
bool isIndirectCtrl() const
Definition: dyn_inst.hh:555
gem5::RequestorID
uint16_t RequestorID
Definition: request.hh:95
gem5::o3::DynInst::effAddr
Addr effAddr
The effective virtual address (lds & stores only).
Definition: dyn_inst.hh:335
trace.hh
gem5::StaticInst::isFullMemBarrier
bool isFullMemBarrier() const
Definition: static_inst.hh:196
gem5::StaticInst::isUncondCtrl
bool isUncondCtrl() const
Definition: static_inst.hh:187
gem5::o3::DynInst::isHtmCancel
bool isHtmCancel() const
Definition: dyn_inst.hh:585
gem5::o3::DynInst::effAddrValid
void effAddrValid(bool b)
Definition: dyn_inst.hh:375
gem5::Trace::InstRecord
Definition: insttracer.hh:61
gem5::o3::DynInst::isReadBarrier
bool isReadBarrier() const
Definition: dyn_inst.hh:571
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:61
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::StaticInst::isSyscall
bool isSyscall() const
Definition: static_inst.hh:205
gem5::o3::DynInst::htmDepth
uint64_t htmDepth
Definition: dyn_inst.hh:994
gem5::o3::DynInst::readStCondFailures
unsigned int readStCondFailures() const override
Returns the number of consecutive store conditional failures.
Definition: dyn_inst.hh:956
gem5::StaticInst::isStoreConditional
bool isStoreConditional() const
Definition: static_inst.hh:171
gem5::o3::DynInst::isDelayedCommit
bool isDelayedCommit() const
Definition: dyn_inst.hh:579
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
cpu.hh
std::list
STL list class.
Definition: stl.hh:51
gem5::o3::DynInst::renamedDestIdx
PhysRegIdPtr renamedDestIdx(int idx) const
Definition: dyn_inst.hh:262
gem5::o3::DynInst::SquashedInIQ
@ SquashedInIQ
Instruction is squashed.
Definition: dyn_inst.hh:158
gem5::o3::DynInst::setMemAccPredicate
void setMemAccPredicate(bool val) override
Definition: dyn_inst.hh:923
gem5::o3::DynInst::forwardOldRegs
void forwardOldRegs()
Definition: dyn_inst.hh:1086
gem5::AtomicOpFunctorPtr
std::unique_ptr< AtomicOpFunctor > AtomicOpFunctorPtr
Definition: amo.hh:242
gem5::o3::DynInst::fault
Fault fault
The kind of fault this instruction has generated.
Definition: dyn_inst.hh:138
gem5::o3::DynInst::firstIssue
Tick firstIssue
Definition: dyn_inst.hh:1012
gem5::o3::DynInst::renamedSrcIdx
PhysRegIdPtr renamedSrcIdx(int idx) const
Definition: dyn_inst.hh:291
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::o3::CPU::readVecPredReg
const TheISA::VecPredRegContainer & readVecPredReg(PhysRegIdPtr reg_idx) const
Definition: cpu.cc:1125
gem5::o3::DynInst::demapPage
void demapPage(Addr vaddr, uint64_t asn) override
Invalidate a page in the DTLB and ITLB.
Definition: dyn_inst.hh:392
gem5::o3::DynInst::strictlyOrdered
void strictlyOrdered(bool so)
Definition: dyn_inst.hh:940
gem5::o3::DynInst::isVector
bool isVector() const
Definition: dyn_inst.hh:550
gem5::o3::DynInst::CanIssue
@ CanIssue
Instruction has its result.
Definition: dyn_inst.hh:151
gem5::o3::DynInst::isHtmCmd
bool isHtmCmd() const
Definition: dyn_inst.hh:586
gem5::o3::DynInst::Arrays::numDests
size_t numDests
Definition: dyn_inst.hh:89
gem5::o3::DynInst::numVecDestRegs
int8_t numVecDestRegs() const
Definition: dyn_inst.hh:688
gem5::o3::DynInst::_numSrcs
size_t _numSrcs
Definition: dyn_inst.hh:218
gem5::o3::DynInst::isUncondCtrl
bool isUncondCtrl() const
Definition: dyn_inst.hh:557
gem5::o3::DynInst::LsqEntry
@ LsqEntry
Instruction is in the ROB.
Definition: dyn_inst.hh:148
gem5::o3::DynInst::_flatDestIdx
RegId * _flatDestIdx
Definition: dyn_inst.hh:223
gem5::o3::DynInst::setSquashedInROB
void setSquashedInROB()
Sets this instruction as squashed in the ROB.
Definition: dyn_inst.hh:850
gem5::o3::DynInst::numDests
size_t numDests() const
Definition: dyn_inst.hh:241
gem5::o3::DynInst::_destIdx
PhysRegIdPtr * _destIdx
Definition: dyn_inst.hh:227
gem5::o3::DynInst::effAddrValid
bool effAddrValid() const
Is the effective virtual address valid.
Definition: dyn_inst.hh:374
gem5::o3::DynInst::readVecPredRegOperand
const TheISA::VecPredRegContainer & readVecPredRegOperand(const StaticInst *si, int idx) const override
Predicate registers interface.
Definition: dyn_inst.hh:1176
gem5::o3::DynInst::reqToVerify
RequestPtr reqToVerify
Definition: dyn_inst.hh:367
gem5::o3::DynInst::lqIdx
ssize_t lqIdx
Load queue index.
Definition: dyn_inst.hh:350
gem5::o3::DynInst::isSquashed
bool isSquashed() const
Returns whether or not this instruction is squashed.
Definition: dyn_inst.hh:800
gem5::InstResult
Definition: inst_res.hh:50
gem5::o3::DynInst::memOpDone
void memOpDone(bool f)
Definition: dyn_inst.hh:379
gem5::o3::DynInst::PredTaken
@ PredTaken
Definition: dyn_inst.hh:185
gem5::o3::DynInst::setStCondFailures
void setStCondFailures(unsigned int sc_failures) override
Sets the number of consecutive store conditional failures.
Definition: dyn_inst.hh:963
gem5::o3::DynInst::Status
Status
Definition: dyn_inst.hh:144
gem5::o3::DynInst::BlockingInst
@ BlockingInst
Is a recover instruction.
Definition: dyn_inst.hh:165
gem5::o3::DynInst::isHtmStart
bool isHtmStart() const
Definition: dyn_inst.hh:583
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242
gem5::o3::DynInst::isAtomic
bool isAtomic() const
Definition: dyn_inst.hh:543
gem5::o3::DynInst
Definition: dyn_inst.hh:76
gem5::o3::DynInst::setPredicate
void setPredicate(bool val) override
Definition: dyn_inst.hh:907
gem5::o3::DynInst::memData
uint8_t * memData
Pointer to the data for the memory access.
Definition: dyn_inst.hh:347
gem5::o3::DynInst::hitExternalSnoop
bool hitExternalSnoop() const
True if the address hit a external snoop while sitting in the LSQ.
Definition: dyn_inst.hh:441
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:113
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::o3::DynInst::isSerializeAfter
bool isSerializeAfter() const
Definition: dyn_inst.hh:565
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::o3::DynInst::isSerializeBefore
bool isSerializeBefore() const
Definition: dyn_inst.hh:560
gem5::o3::DynInst::setInROB
void setInROB()
Sets this instruction as a entry the ROB.
Definition: dyn_inst.hh:841

Generated on Wed May 4 2022 12:13:53 for gem5 by doxygen 1.8.17