gem5  v21.2.1.1
pagetable_walker.cc
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50 
52 
53 #include <memory>
54 
55 #include "arch/riscv/faults.hh"
56 #include "arch/riscv/page_size.hh"
57 #include "arch/riscv/pagetable.hh"
58 #include "arch/riscv/tlb.hh"
59 #include "base/bitfield.hh"
60 #include "base/trie.hh"
61 #include "cpu/base.hh"
62 #include "cpu/thread_context.hh"
63 #include "debug/PageTableWalker.hh"
64 #include "mem/packet_access.hh"
65 #include "mem/request.hh"
66 
67 namespace gem5
68 {
69 
70 namespace RiscvISA {
71 
72 Fault
74  const RequestPtr &_req, BaseMMU::Mode _mode)
75 {
76  // TODO: in timing mode, instead of blocking when there are other
77  // outstanding requests, see if this request can be coalesced with
78  // another one (i.e. either coalesce or start walk)
79  WalkerState * newState = new WalkerState(this, _translation, _req);
80  newState->initState(_tc, _mode, sys->isTimingMode());
81  if (currStates.size()) {
82  assert(newState->isTiming());
83  DPRINTF(PageTableWalker, "Walks in progress: %d\n", currStates.size());
84  currStates.push_back(newState);
85  return NoFault;
86  } else {
87  currStates.push_back(newState);
88  Fault fault = newState->startWalk();
89  if (!newState->isTiming()) {
90  currStates.pop_front();
91  delete newState;
92  }
93  return fault;
94  }
95 }
96 
97 Fault
98 Walker::startFunctional(ThreadContext * _tc, Addr &addr, unsigned &logBytes,
99  BaseMMU::Mode _mode)
100 {
101  funcState.initState(_tc, _mode);
102  return funcState.startFunctional(addr, logBytes);
103 }
104 
105 bool
107 {
108  return walker->recvTimingResp(pkt);
109 }
110 
111 bool
113 {
114  WalkerSenderState * senderState =
115  dynamic_cast<WalkerSenderState *>(pkt->popSenderState());
116  WalkerState * senderWalk = senderState->senderWalk;
117  bool walkComplete = senderWalk->recvPacket(pkt);
118  delete senderState;
119  if (walkComplete) {
121  for (iter = currStates.begin(); iter != currStates.end(); iter++) {
122  WalkerState * walkerState = *(iter);
123  if (walkerState == senderWalk) {
124  iter = currStates.erase(iter);
125  break;
126  }
127  }
128  delete senderWalk;
129  // Since we block requests when another is outstanding, we
130  // need to check if there is a waiting request to be serviced
131  if (currStates.size() && !startWalkWrapperEvent.scheduled())
132  // delay sending any new requests until we are finished
133  // with the responses
135  }
136  return true;
137 }
138 
139 void
141 {
142  walker->recvReqRetry();
143 }
144 
145 void
147 {
149  for (iter = currStates.begin(); iter != currStates.end(); iter++) {
150  WalkerState * walkerState = *(iter);
151  if (walkerState->isRetrying()) {
152  walkerState->retry();
153  }
154  }
155 }
156 
157 bool Walker::sendTiming(WalkerState* sendingState, PacketPtr pkt)
158 {
159  WalkerSenderState* walker_state = new WalkerSenderState(sendingState);
160  pkt->pushSenderState(walker_state);
161  if (port.sendTimingReq(pkt)) {
162  return true;
163  } else {
164  // undo the adding of the sender state and delete it, as we
165  // will do it again the next time we attempt to send it
166  pkt->popSenderState();
167  delete walker_state;
168  return false;
169  }
170 
171 }
172 
173 Port &
174 Walker::getPort(const std::string &if_name, PortID idx)
175 {
176  if (if_name == "port")
177  return port;
178  else
179  return ClockedObject::getPort(if_name, idx);
180 }
181 
182 void
184  BaseMMU::Mode _mode, bool _isTiming)
185 {
186  assert(state == Ready);
187  started = false;
188  tc = _tc;
189  mode = _mode;
190  timing = _isTiming;
191  // fetch these now in case they change during the walk
192  status = tc->readMiscReg(MISCREG_STATUS);
193  pmode = walker->tlb->getMemPriv(tc, mode);
194  satp = tc->readMiscReg(MISCREG_SATP);
195  assert(satp.mode == AddrXlateMode::SV39);
196 }
197 
198 void
200 {
201  unsigned num_squashed = 0;
202  WalkerState *currState = currStates.front();
203  while ((num_squashed < numSquashable) && currState &&
204  currState->translation->squashed()) {
205  currStates.pop_front();
206  num_squashed++;
207 
208  DPRINTF(PageTableWalker, "Squashing table walk for address %#x\n",
209  currState->req->getVaddr());
210 
211  // finish the translation which will delete the translation object
212  currState->translation->finish(
213  std::make_shared<UnimpFault>("Squashed Inst"),
214  currState->req, currState->tc, currState->mode);
215 
216  // delete the current request if there are no inflight packets.
217  // if there is something in flight, delete when the packets are
218  // received and inflight is zero.
219  if (currState->numInflight() == 0) {
220  delete currState;
221  } else {
222  currState->squash();
223  }
224 
225  // check the next translation request, if it exists
226  if (currStates.size())
227  currState = currStates.front();
228  else
229  currState = NULL;
230  }
231  if (currState && !currState->wasStarted())
232  currState->startWalk();
233 }
234 
235 Fault
237 {
238  Fault fault = NoFault;
239  assert(!started);
240  started = true;
241  setupWalk(req->getVaddr());
242  if (timing) {
243  nextState = state;
244  state = Waiting;
245  timingFault = NoFault;
246  sendPackets();
247  } else {
248  do {
249  walker->port.sendAtomic(read);
250  PacketPtr write = NULL;
251  fault = stepWalk(write);
252  assert(fault == NoFault || read == NULL);
253  state = nextState;
254  nextState = Ready;
255  if (write)
256  walker->port.sendAtomic(write);
257  } while (read);
258  state = Ready;
259  nextState = Waiting;
260  }
261  return fault;
262 }
263 
264 Fault
266 {
267  Fault fault = NoFault;
268  assert(!started);
269  started = true;
270  setupWalk(addr);
271 
272  do {
273  walker->port.sendFunctional(read);
274  // On a functional access (page table lookup), writes should
275  // not happen so this pointer is ignored after stepWalk
276  PacketPtr write = NULL;
277  fault = stepWalk(write);
278  assert(fault == NoFault || read == NULL);
279  state = nextState;
280  nextState = Ready;
281  } while (read);
282  logBytes = entry.logBytes;
283  addr = entry.paddr << PageShift;
284 
285  return fault;
286 }
287 
288 Fault
290 {
291  assert(state != Ready && state != Waiting);
292  Fault fault = NoFault;
293  write = NULL;
294  PTESv39 pte = read->getLE<uint64_t>();
295  Addr nextRead = 0;
296  bool doWrite = false;
297  bool doTLBInsert = false;
298  bool doEndWalk = false;
299 
300  DPRINTF(PageTableWalker, "Got level%d PTE: %#x\n", level, pte);
301 
302  // step 2:
303  // Performing PMA/PMP checks on physical address of PTE
304 
305  walker->pma->check(read->req);
306  // Effective privilege mode for pmp checks for page table
307  // walks is S mode according to specs
308  fault = walker->pmp->pmpCheck(read->req, mode,
309  RiscvISA::PrivilegeMode::PRV_S, tc, entry.vaddr);
310 
311  if (fault == NoFault) {
312  // step 3:
313  if (!pte.v || (!pte.r && pte.w)) {
314  doEndWalk = true;
315  DPRINTF(PageTableWalker, "PTE invalid, raising PF\n");
316  fault = pageFault(pte.v);
317  }
318  else {
319  // step 4:
320  if (pte.r || pte.x) {
321  // step 5: leaf PTE
322  doEndWalk = true;
323  fault = walker->tlb->checkPermissions(status, pmode,
324  entry.vaddr, mode, pte);
325 
326  // step 6
327  if (fault == NoFault) {
328  if (level >= 1 && pte.ppn0 != 0) {
329  DPRINTF(PageTableWalker,
330  "PTE has misaligned PPN, raising PF\n");
331  fault = pageFault(true);
332  }
333  else if (level == 2 && pte.ppn1 != 0) {
334  DPRINTF(PageTableWalker,
335  "PTE has misaligned PPN, raising PF\n");
336  fault = pageFault(true);
337  }
338  }
339 
340  if (fault == NoFault) {
341  // step 7
342  if (!pte.a) {
343  pte.a = 1;
344  doWrite = true;
345  }
346  if (!pte.d && mode == BaseMMU::Write) {
347  pte.d = 1;
348  doWrite = true;
349  }
350  // Performing PMA/PMP checks
351 
352  if (doWrite) {
353 
354  // this read will eventually become write
355  // if doWrite is True
356 
357  walker->pma->check(read->req);
358 
359  fault = walker->pmp->pmpCheck(read->req,
360  mode, pmode, tc, entry.vaddr);
361 
362  }
363  // perform step 8 only if pmp checks pass
364  if (fault == NoFault) {
365 
366  // step 8
367  entry.logBytes = PageShift + (level * LEVEL_BITS);
368  entry.paddr = pte.ppn;
369  entry.vaddr &= ~((1 << entry.logBytes) - 1);
370  entry.pte = pte;
371  // put it non-writable into the TLB to detect
372  // writes and redo the page table walk in order
373  // to update the dirty flag.
374  if (!pte.d && mode != BaseMMU::Write)
375  entry.pte.w = 0;
376  doTLBInsert = true;
377  }
378  }
379  } else {
380  level--;
381  if (level < 0) {
382  DPRINTF(PageTableWalker, "No leaf PTE found,"
383  "raising PF\n");
384  doEndWalk = true;
385  fault = pageFault(true);
386  } else {
388  Addr idx = (entry.vaddr >> shift) & LEVEL_MASK;
389  nextRead = (pte.ppn << PageShift) + (idx * sizeof(pte));
390  nextState = Translate;
391  }
392  }
393  }
394  } else {
395  doEndWalk = true;
396  }
397  PacketPtr oldRead = read;
398  Request::Flags flags = oldRead->req->getFlags();
399 
400  if (doEndWalk) {
401  // If we need to write, adjust the read packet to write the modified
402  // value back to memory.
403  if (!functional && doWrite) {
404  DPRINTF(PageTableWalker, "Writing level%d PTE to %#x: %#x\n",
405  level, oldRead->getAddr(), pte);
406  write = oldRead;
407  write->setLE<uint64_t>(pte);
408  write->cmd = MemCmd::WriteReq;
409  read = NULL;
410  } else {
411  write = NULL;
412  }
413 
414  if (doTLBInsert) {
415  if (!functional)
416  walker->tlb->insert(entry.vaddr, entry);
417  else {
418  DPRINTF(PageTableWalker, "Translated %#x -> %#x\n",
419  entry.vaddr, entry.paddr << PageShift |
420  (entry.vaddr & mask(entry.logBytes)));
421  }
422  }
423  endWalk();
424  }
425  else {
426  //If we didn't return, we're setting up another read.
427  RequestPtr request = std::make_shared<Request>(
428  nextRead, oldRead->getSize(), flags, walker->requestorId);
429  read = new Packet(request, MemCmd::ReadReq);
430  read->allocate();
431 
432  DPRINTF(PageTableWalker,
433  "Loading level%d PTE from %#x\n", level, nextRead);
434  }
435 
436  return fault;
437 }
438 
439 void
441 {
442  nextState = Ready;
443  delete read;
444  read = NULL;
445 }
446 
447 void
449 {
450  vaddr = Addr(sext<VADDR_BITS>(vaddr));
451 
452  Addr shift = PageShift + LEVEL_BITS * 2;
453  Addr idx = (vaddr >> shift) & LEVEL_MASK;
454  Addr topAddr = (satp.ppn << PageShift) + (idx * sizeof(PTESv39));
455  level = 2;
456 
457  DPRINTF(PageTableWalker, "Performing table walk for address %#x\n", vaddr);
458  DPRINTF(PageTableWalker, "Loading level%d PTE from %#x\n", level, topAddr);
459 
460  state = Translate;
461  nextState = Ready;
462  entry.vaddr = vaddr;
463  entry.asid = satp.asid;
464 
466  RequestPtr request = std::make_shared<Request>(
467  topAddr, sizeof(PTESv39), flags, walker->requestorId);
468 
469  read = new Packet(request, MemCmd::ReadReq);
470  read->allocate();
471 }
472 
473 bool
475 {
476  assert(pkt->isResponse());
477  assert(inflight);
478  assert(state == Waiting);
479  inflight--;
480  if (squashed) {
481  // if were were squashed, return true once inflight is zero and
482  // this WalkerState will be freed there.
483  return (inflight == 0);
484  }
485  if (pkt->isRead()) {
486  // should not have a pending read it we also had one outstanding
487  assert(!read);
488 
489  // @todo someone should pay for this
490  pkt->headerDelay = pkt->payloadDelay = 0;
491 
492  state = nextState;
493  nextState = Ready;
494  PacketPtr write = NULL;
495  read = pkt;
496  timingFault = stepWalk(write);
497  state = Waiting;
498  assert(timingFault == NoFault || read == NULL);
499  if (write) {
500  writes.push_back(write);
501  }
502  sendPackets();
503  } else {
504  sendPackets();
505  }
506  if (inflight == 0 && read == NULL && writes.size() == 0) {
507  state = Ready;
508  nextState = Waiting;
509  if (timingFault == NoFault) {
510  /*
511  * Finish the translation. Now that we know the right entry is
512  * in the TLB, this should work with no memory accesses.
513  * There could be new faults unrelated to the table walk like
514  * permissions violations, so we'll need the return value as
515  * well.
516  */
517  Addr vaddr = req->getVaddr();
518  vaddr = Addr(sext<VADDR_BITS>(vaddr));
519  Addr paddr = walker->tlb->translateWithTLB(vaddr, satp.asid, mode);
520  req->setPaddr(paddr);
521  walker->pma->check(req);
522 
523  // do pmp check if any checking condition is met.
524  // timingFault will be NoFault if pmp checks are
525  // passed, otherwise an address fault will be returned.
526  timingFault = walker->pmp->pmpCheck(req, mode, pmode, tc);
527 
528  // Let the CPU continue.
529  translation->finish(timingFault, req, tc, mode);
530  } else {
531  // There was a fault during the walk. Let the CPU know.
532  translation->finish(timingFault, req, tc, mode);
533  }
534  return true;
535  }
536 
537  return false;
538 }
539 
540 void
542 {
543  //If we're already waiting for the port to become available, just return.
544  if (retrying)
545  return;
546 
547  //Reads always have priority
548  if (read) {
549  PacketPtr pkt = read;
550  read = NULL;
551  inflight++;
552  if (!walker->sendTiming(this, pkt)) {
553  retrying = true;
554  read = pkt;
555  inflight--;
556  return;
557  }
558  }
559  //Send off as many of the writes as we can.
560  while (writes.size()) {
561  PacketPtr write = writes.back();
562  writes.pop_back();
563  inflight++;
564  if (!walker->sendTiming(this, write)) {
565  retrying = true;
566  writes.push_back(write);
567  inflight--;
568  return;
569  }
570  }
571 }
572 
573 unsigned
575 {
576  return inflight;
577 }
578 
579 bool
581 {
582  return retrying;
583 }
584 
585 bool
587 {
588  return timing;
589 }
590 
591 bool
593 {
594  return started;
595 }
596 
597 void
599 {
600  squashed = true;
601 }
602 
603 void
605 {
606  retrying = false;
607  sendPackets();
608 }
609 
610 Fault
612 {
613  DPRINTF(PageTableWalker, "Raising page fault.\n");
614  return walker->tlb->createPagefault(entry.vaddr, mode);
615 }
616 
617 } // namespace RiscvISA
618 } // namespace gem5
gem5::X86ISA::level
Bitfield< 20 > level
Definition: intmessage.hh:51
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::BaseMMU::Translation::squashed
virtual bool squashed() const
This function is used by the page table walker to determine if it should translate the a pending requ...
Definition: mmu.hh:84
gem5::RiscvISA::PRV_S
@ PRV_S
Definition: isa.hh:56
gem5::SimObject::getPort
virtual Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a port with a given name and index.
Definition: sim_object.cc:126
gem5::RiscvISA::MISCREG_STATUS
@ MISCREG_STATUS
Definition: misc.hh:71
gem5::RiscvISA::Walker::startWalkWrapper
void startWalkWrapper()
Definition: pagetable_walker.cc:199
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::RequestPort::sendTimingReq
bool sendTimingReq(PacketPtr pkt)
Attempt to send a timing request to the responder port by calling its corresponding receive function.
Definition: port.hh:495
gem5::RiscvISA::Walker::WalkerPort::recvTimingResp
bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
Definition: pagetable_walker.cc:106
faults.hh
gem5::RiscvISA::Walker::WalkerState::req
RequestPtr req
Definition: pagetable_walker.hh:99
gem5::RiscvISA::Walker::WalkerState::wasStarted
bool wasStarted()
Definition: pagetable_walker.cc:592
gem5::RiscvISA::LEVEL_MASK
const Addr LEVEL_MASK
Definition: pagetable.hh:61
gem5::RiscvISA::Walker::WalkerState::setupWalk
void setupWalk(Addr vaddr)
Definition: pagetable_walker.cc:448
gem5::Packet::pushSenderState
void pushSenderState(SenderState *sender_state)
Push a new sender state to the packet and make the current sender state the predecessor of the new on...
Definition: packet.cc:316
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:56
gem5::Packet::req
RequestPtr req
A pointer to the original request.
Definition: packet.hh:366
gem5::BaseMMU::Write
@ Write
Definition: mmu.hh:56
gem5::RiscvISA::Walker::startFunctional
Fault startFunctional(ThreadContext *_tc, Addr &addr, unsigned &logBytes, BaseMMU::Mode mode)
Definition: pagetable_walker.cc:98
gem5::RiscvISA::Walker::WalkerSenderState
Definition: pagetable_walker.hh:156
gem5::RiscvISA::Walker::port
WalkerPort port
Definition: pagetable_walker.hh:82
gem5::RiscvISA::Walker::WalkerState::startWalk
Fault startWalk()
Definition: pagetable_walker.cc:236
gem5::RiscvISA::Walker::WalkerState::startFunctional
Fault startFunctional(Addr &addr, unsigned &logBytes)
Definition: pagetable_walker.cc:265
gem5::RiscvISA::Walker::recvReqRetry
void recvReqRetry()
Definition: pagetable_walker.cc:146
gem5::RiscvISA::Walker::WalkerState
Definition: pagetable_walker.hh:85
gem5::EventManager::schedule
void schedule(Event &event, Tick when)
Definition: eventq.hh:1019
gem5::RiscvISA::Walker::WalkerState::recvPacket
bool recvPacket(PacketPtr pkt)
Definition: pagetable_walker.cc:474
gem5::RiscvISA::Walker::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: pagetable_walker.cc:174
gem5::Packet::headerDelay
uint32_t headerDelay
The extra delay from seeing the packet until the header is transmitted.
Definition: packet.hh:420
gem5::RiscvISA::LEVEL_BITS
const Addr LEVEL_BITS
Definition: pagetable.hh:60
gem5::RiscvISA::PageShift
const Addr PageShift
Definition: page_size.hh:53
request.hh
gem5::RiscvISA::Walker::WalkerState::mode
BaseMMU::Mode mode
Definition: pagetable_walker.hh:109
gem5::RiscvISA::Walker::WalkerState::sendPackets
void sendPackets()
Definition: pagetable_walker.cc:541
gem5::RiscvISA::Walker::numSquashable
unsigned numSquashable
Definition: pagetable_walker.hh:181
gem5::RiscvISA::Walker::start
Fault start(ThreadContext *_tc, BaseMMU::Translation *translation, const RequestPtr &req, BaseMMU::Mode mode)
Definition: pagetable_walker.cc:73
gem5::ArmISA::shift
Bitfield< 6, 5 > shift
Definition: types.hh:117
gem5::Packet::payloadDelay
uint32_t payloadDelay
The extra pipelining delay from seeing the packet until the end of payload is transmitted by the comp...
Definition: packet.hh:438
gem5::RiscvISA::Walker::WalkerState::translation
BaseMMU::Translation * translation
Definition: pagetable_walker.hh:108
gem5::RiscvISA::Walker::WalkerState::pageFault
Fault pageFault(bool present)
Definition: pagetable_walker.cc:611
gem5::X86ISA::present
Bitfield< 7 > present
Definition: misc.hh:998
gem5::Flags< FlagsType >
gem5::Packet::isRead
bool isRead() const
Definition: packet.hh:582
bitfield.hh
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
tlb.hh
gem5::RiscvISA::Walker::funcState
WalkerState funcState
Definition: pagetable_walker.hh:154
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::RiscvISA::Walker::WalkerState
friend class WalkerState
Definition: pagetable_walker.hh:149
gem5::probing::Packet
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:109
gem5::RiscvISA::MISCREG_SATP
@ MISCREG_SATP
Definition: misc.hh:180
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::MemCmd::ReadReq
@ ReadReq
Definition: packet.hh:86
page_size.hh
gem5::RiscvISA::Walker::startWalkWrapperEvent
EventFunctionWrapper startWalkWrapperEvent
Event used to call startWalkWrapper.
Definition: pagetable_walker.hh:189
gem5::RiscvISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::System::isTimingMode
bool isTimingMode() const
Is the system in timing mode?
Definition: system.hh:274
gem5::RiscvISA::mask
mask
Definition: pra_constants.hh:73
gem5::Packet::cmd
MemCmd cmd
The command field of the packet.
Definition: packet.hh:361
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::RiscvISA::Walker::WalkerState::isRetrying
bool isRetrying()
Definition: pagetable_walker.cc:580
gem5::RiscvISA::Walker::WalkerState::numInflight
unsigned numInflight() const
Definition: pagetable_walker.cc:574
gem5::RiscvISA::Walker::WalkerPort::recvReqRetry
void recvReqRetry()
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
Definition: pagetable_walker.cc:140
gem5::RiscvISA::Walker::WalkerState::stepWalk
Fault stepWalk(PacketPtr &write)
Definition: pagetable_walker.cc:289
packet_access.hh
gem5::Clocked::clockEdge
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Definition: clocked_object.hh:177
gem5::Packet::popSenderState
SenderState * popSenderState()
Pop the top of the state stack and return a pointer to it.
Definition: packet.cc:324
gem5::BaseMMU::Translation
Definition: mmu.hh:58
gem5::RiscvISA::Walker::sys
System * sys
Definition: pagetable_walker.hh:175
gem5::RiscvISA::Walker::WalkerState::endWalk
void endWalk()
Definition: pagetable_walker.cc:440
base.hh
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::RiscvISA::Walker::WalkerState::squash
void squash()
Definition: pagetable_walker.cc:598
gem5::RiscvISA::Walker::recvTimingResp
bool recvTimingResp(PacketPtr pkt)
Definition: pagetable_walker.cc:112
gem5::RiscvISA::mode
mode
Definition: pagetable.hh:46
gem5::MemCmd::WriteReq
@ WriteReq
Definition: packet.hh:89
gem5::RiscvISA::Walker::sendTiming
bool sendTiming(WalkerState *sendingState, PacketPtr pkt)
Definition: pagetable_walker.cc:157
gem5::Packet::getLE
T getLE() const
Get the data in the packet byte swapped from little endian to host endian.
Definition: packet_access.hh:78
gem5::RiscvISA::Walker::WalkerState::retry
void retry()
Definition: pagetable_walker.cc:604
gem5::RiscvISA::Walker::WalkerState::isTiming
bool isTiming()
Definition: pagetable_walker.cc:586
gem5::Packet::setLE
void setLE(T v)
Set the value in the data pointer to v as little endian.
Definition: packet_access.hh:108
std::list
STL list class.
Definition: stl.hh:51
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:781
gem5::RiscvISA::Walker::currStates
std::list< WalkerState * > currStates
Definition: pagetable_walker.hh:152
gem5::RiscvISA::Walker::WalkerState::tc
ThreadContext * tc
Definition: pagetable_walker.hh:98
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::BaseMMU::Translation::finish
virtual void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode)=0
pagetable.hh
gem5::RiscvISA::Walker::WalkerState::initState
void initState(ThreadContext *_tc, BaseMMU::Mode _mode, bool _isTiming=false)
Definition: pagetable_walker.cc:183
gem5::RiscvISA::Walker::WalkerSenderState::senderWalk
WalkerState * senderWalk
Definition: pagetable_walker.hh:158
gem5::Packet::isResponse
bool isResponse() const
Definition: packet.hh:587
thread_context.hh
gem5::Packet::getSize
unsigned getSize() const
Definition: packet.hh:791
trie.hh
gem5::Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:465
gem5::RiscvISA::Walker::WalkerPort::walker
Walker * walker
Definition: pagetable_walker.hh:75
gem5::ArmISA::status
Bitfield< 5, 0 > status
Definition: misc_types.hh:423
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::Request::PHYSICAL
@ PHYSICAL
The virtual address is also the physical address.
Definition: request.hh:117
pagetable_walker.hh

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