gem5  v21.1.0.2
pagetable_walker.cc
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50 
52 
53 #include <memory>
54 
55 #include "arch/riscv/faults.hh"
56 #include "arch/riscv/pagetable.hh"
57 #include "arch/riscv/tlb.hh"
58 #include "base/bitfield.hh"
59 #include "base/trie.hh"
60 #include "cpu/base.hh"
61 #include "cpu/thread_context.hh"
62 #include "debug/PageTableWalker.hh"
63 #include "mem/packet_access.hh"
64 #include "mem/request.hh"
65 
66 namespace gem5
67 {
68 
69 namespace RiscvISA {
70 
71 Fault
73  const RequestPtr &_req, BaseMMU::Mode _mode)
74 {
75  // TODO: in timing mode, instead of blocking when there are other
76  // outstanding requests, see if this request can be coalesced with
77  // another one (i.e. either coalesce or start walk)
78  WalkerState * newState = new WalkerState(this, _translation, _req);
79  newState->initState(_tc, _mode, sys->isTimingMode());
80  if (currStates.size()) {
81  assert(newState->isTiming());
82  DPRINTF(PageTableWalker, "Walks in progress: %d\n", currStates.size());
83  currStates.push_back(newState);
84  return NoFault;
85  } else {
86  currStates.push_back(newState);
87  Fault fault = newState->startWalk();
88  if (!newState->isTiming()) {
89  currStates.pop_front();
90  delete newState;
91  }
92  return fault;
93  }
94 }
95 
96 Fault
97 Walker::startFunctional(ThreadContext * _tc, Addr &addr, unsigned &logBytes,
98  BaseMMU::Mode _mode)
99 {
100  funcState.initState(_tc, _mode);
101  return funcState.startFunctional(addr, logBytes);
102 }
103 
104 bool
106 {
107  return walker->recvTimingResp(pkt);
108 }
109 
110 bool
112 {
113  WalkerSenderState * senderState =
114  dynamic_cast<WalkerSenderState *>(pkt->popSenderState());
115  WalkerState * senderWalk = senderState->senderWalk;
116  bool walkComplete = senderWalk->recvPacket(pkt);
117  delete senderState;
118  if (walkComplete) {
120  for (iter = currStates.begin(); iter != currStates.end(); iter++) {
121  WalkerState * walkerState = *(iter);
122  if (walkerState == senderWalk) {
123  iter = currStates.erase(iter);
124  break;
125  }
126  }
127  delete senderWalk;
128  // Since we block requests when another is outstanding, we
129  // need to check if there is a waiting request to be serviced
130  if (currStates.size() && !startWalkWrapperEvent.scheduled())
131  // delay sending any new requests until we are finished
132  // with the responses
134  }
135  return true;
136 }
137 
138 void
140 {
141  walker->recvReqRetry();
142 }
143 
144 void
146 {
148  for (iter = currStates.begin(); iter != currStates.end(); iter++) {
149  WalkerState * walkerState = *(iter);
150  if (walkerState->isRetrying()) {
151  walkerState->retry();
152  }
153  }
154 }
155 
156 bool Walker::sendTiming(WalkerState* sendingState, PacketPtr pkt)
157 {
158  WalkerSenderState* walker_state = new WalkerSenderState(sendingState);
159  pkt->pushSenderState(walker_state);
160  if (port.sendTimingReq(pkt)) {
161  return true;
162  } else {
163  // undo the adding of the sender state and delete it, as we
164  // will do it again the next time we attempt to send it
165  pkt->popSenderState();
166  delete walker_state;
167  return false;
168  }
169 
170 }
171 
172 Port &
173 Walker::getPort(const std::string &if_name, PortID idx)
174 {
175  if (if_name == "port")
176  return port;
177  else
178  return ClockedObject::getPort(if_name, idx);
179 }
180 
181 void
183  BaseMMU::Mode _mode, bool _isTiming)
184 {
185  assert(state == Ready);
186  started = false;
187  tc = _tc;
188  mode = _mode;
189  timing = _isTiming;
190  // fetch these now in case they change during the walk
191  status = tc->readMiscReg(MISCREG_STATUS);
192  pmode = walker->tlb->getMemPriv(tc, mode);
193  satp = tc->readMiscReg(MISCREG_SATP);
194  assert(satp.mode == AddrXlateMode::SV39);
195 }
196 
197 void
199 {
200  unsigned num_squashed = 0;
201  WalkerState *currState = currStates.front();
202  while ((num_squashed < numSquashable) && currState &&
203  currState->translation->squashed()) {
204  currStates.pop_front();
205  num_squashed++;
206 
207  DPRINTF(PageTableWalker, "Squashing table walk for address %#x\n",
208  currState->req->getVaddr());
209 
210  // finish the translation which will delete the translation object
211  currState->translation->finish(
212  std::make_shared<UnimpFault>("Squashed Inst"),
213  currState->req, currState->tc, currState->mode);
214 
215  // delete the current request if there are no inflight packets.
216  // if there is something in flight, delete when the packets are
217  // received and inflight is zero.
218  if (currState->numInflight() == 0) {
219  delete currState;
220  } else {
221  currState->squash();
222  }
223 
224  // check the next translation request, if it exists
225  if (currStates.size())
226  currState = currStates.front();
227  else
228  currState = NULL;
229  }
230  if (currState && !currState->wasStarted())
231  currState->startWalk();
232 }
233 
234 Fault
236 {
237  Fault fault = NoFault;
238  assert(!started);
239  started = true;
240  setupWalk(req->getVaddr());
241  if (timing) {
242  nextState = state;
243  state = Waiting;
244  timingFault = NoFault;
245  sendPackets();
246  } else {
247  do {
248  walker->port.sendAtomic(read);
249  PacketPtr write = NULL;
250  fault = stepWalk(write);
251  assert(fault == NoFault || read == NULL);
252  state = nextState;
253  nextState = Ready;
254  if (write)
255  walker->port.sendAtomic(write);
256  } while (read);
257  state = Ready;
258  nextState = Waiting;
259  }
260  return fault;
261 }
262 
263 Fault
265 {
266  Fault fault = NoFault;
267  assert(!started);
268  started = true;
269  setupWalk(addr);
270 
271  do {
272  walker->port.sendFunctional(read);
273  // On a functional access (page table lookup), writes should
274  // not happen so this pointer is ignored after stepWalk
275  PacketPtr write = NULL;
276  fault = stepWalk(write);
277  assert(fault == NoFault || read == NULL);
278  state = nextState;
279  nextState = Ready;
280  } while (read);
281  logBytes = entry.logBytes;
282  addr = entry.paddr << PageShift;
283 
284  return fault;
285 }
286 
287 Fault
289 {
290  assert(state != Ready && state != Waiting);
291  Fault fault = NoFault;
292  write = NULL;
293  PTESv39 pte = read->getLE<uint64_t>();
294  Addr nextRead = 0;
295  bool doWrite = false;
296  bool doTLBInsert = false;
297  bool doEndWalk = false;
298 
299  DPRINTF(PageTableWalker, "Got level%d PTE: %#x\n", level, pte);
300 
301  // step 2:
302  // Performing PMA/PMP checks on physical address of PTE
303 
304  walker->pma->check(read->req);
305  // Effective privilege mode for pmp checks for page table
306  // walks is S mode according to specs
307  fault = walker->pmp->pmpCheck(read->req, mode,
308  RiscvISA::PrivilegeMode::PRV_S, tc, entry.vaddr);
309 
310  if (fault == NoFault) {
311  // step 3:
312  if (!pte.v || (!pte.r && pte.w)) {
313  doEndWalk = true;
314  DPRINTF(PageTableWalker, "PTE invalid, raising PF\n");
315  fault = pageFault(pte.v);
316  }
317  else {
318  // step 4:
319  if (pte.r || pte.x) {
320  // step 5: leaf PTE
321  doEndWalk = true;
322  fault = walker->tlb->checkPermissions(status, pmode,
323  entry.vaddr, mode, pte);
324 
325  // step 6
326  if (fault == NoFault) {
327  if (level >= 1 && pte.ppn0 != 0) {
328  DPRINTF(PageTableWalker,
329  "PTE has misaligned PPN, raising PF\n");
330  fault = pageFault(true);
331  }
332  else if (level == 2 && pte.ppn1 != 0) {
333  DPRINTF(PageTableWalker,
334  "PTE has misaligned PPN, raising PF\n");
335  fault = pageFault(true);
336  }
337  }
338 
339  if (fault == NoFault) {
340  // step 7
341  if (!pte.a) {
342  pte.a = 1;
343  doWrite = true;
344  }
345  if (!pte.d && mode == BaseMMU::Write) {
346  pte.d = 1;
347  doWrite = true;
348  }
349  // Performing PMA/PMP checks
350 
351  if (doWrite) {
352 
353  // this read will eventually become write
354  // if doWrite is True
355 
356  walker->pma->check(read->req);
357 
358  fault = walker->pmp->pmpCheck(read->req,
359  mode, pmode, tc, entry.vaddr);
360 
361  }
362  // perform step 8 only if pmp checks pass
363  if (fault == NoFault) {
364 
365  // step 8
366  entry.logBytes = PageShift + (level * LEVEL_BITS);
367  entry.paddr = pte.ppn;
368  entry.vaddr &= ~((1 << entry.logBytes) - 1);
369  entry.pte = pte;
370  // put it non-writable into the TLB to detect
371  // writes and redo the page table walk in order
372  // to update the dirty flag.
373  if (!pte.d && mode != BaseMMU::Write)
374  entry.pte.w = 0;
375  doTLBInsert = true;
376  }
377  }
378  } else {
379  level--;
380  if (level < 0) {
381  DPRINTF(PageTableWalker, "No leaf PTE found,"
382  "raising PF\n");
383  doEndWalk = true;
384  fault = pageFault(true);
385  } else {
387  Addr idx = (entry.vaddr >> shift) & LEVEL_MASK;
388  nextRead = (pte.ppn << PageShift) + (idx * sizeof(pte));
389  nextState = Translate;
390  }
391  }
392  }
393  } else {
394  doEndWalk = true;
395  }
396  PacketPtr oldRead = read;
397  Request::Flags flags = oldRead->req->getFlags();
398 
399  if (doEndWalk) {
400  // If we need to write, adjust the read packet to write the modified
401  // value back to memory.
402  if (!functional && doWrite) {
403  DPRINTF(PageTableWalker, "Writing level%d PTE to %#x: %#x\n",
404  level, oldRead->getAddr(), pte);
405  write = oldRead;
406  write->setLE<uint64_t>(pte);
407  write->cmd = MemCmd::WriteReq;
408  read = NULL;
409  } else {
410  write = NULL;
411  }
412 
413  if (doTLBInsert) {
414  if (!functional)
415  walker->tlb->insert(entry.vaddr, entry);
416  else {
417  DPRINTF(PageTableWalker, "Translated %#x -> %#x\n",
418  entry.vaddr, entry.paddr << PageShift |
419  (entry.vaddr & mask(entry.logBytes)));
420  }
421  }
422  endWalk();
423  }
424  else {
425  //If we didn't return, we're setting up another read.
426  RequestPtr request = std::make_shared<Request>(
427  nextRead, oldRead->getSize(), flags, walker->requestorId);
428  read = new Packet(request, MemCmd::ReadReq);
429  read->allocate();
430 
431  DPRINTF(PageTableWalker,
432  "Loading level%d PTE from %#x\n", level, nextRead);
433  }
434 
435  return fault;
436 }
437 
438 void
440 {
441  nextState = Ready;
442  delete read;
443  read = NULL;
444 }
445 
446 void
448 {
449  vaddr = Addr(sext<VADDR_BITS>(vaddr));
450 
451  Addr shift = PageShift + LEVEL_BITS * 2;
452  Addr idx = (vaddr >> shift) & LEVEL_MASK;
453  Addr topAddr = (satp.ppn << PageShift) + (idx * sizeof(PTESv39));
454  level = 2;
455 
456  DPRINTF(PageTableWalker, "Performing table walk for address %#x\n", vaddr);
457  DPRINTF(PageTableWalker, "Loading level%d PTE from %#x\n", level, topAddr);
458 
459  state = Translate;
460  nextState = Ready;
461  entry.vaddr = vaddr;
462  entry.asid = satp.asid;
463 
465  RequestPtr request = std::make_shared<Request>(
466  topAddr, sizeof(PTESv39), flags, walker->requestorId);
467 
468  read = new Packet(request, MemCmd::ReadReq);
469  read->allocate();
470 }
471 
472 bool
474 {
475  assert(pkt->isResponse());
476  assert(inflight);
477  assert(state == Waiting);
478  inflight--;
479  if (squashed) {
480  // if were were squashed, return true once inflight is zero and
481  // this WalkerState will be freed there.
482  return (inflight == 0);
483  }
484  if (pkt->isRead()) {
485  // should not have a pending read it we also had one outstanding
486  assert(!read);
487 
488  // @todo someone should pay for this
489  pkt->headerDelay = pkt->payloadDelay = 0;
490 
491  state = nextState;
492  nextState = Ready;
493  PacketPtr write = NULL;
494  read = pkt;
495  timingFault = stepWalk(write);
496  state = Waiting;
497  assert(timingFault == NoFault || read == NULL);
498  if (write) {
499  writes.push_back(write);
500  }
501  sendPackets();
502  } else {
503  sendPackets();
504  }
505  if (inflight == 0 && read == NULL && writes.size() == 0) {
506  state = Ready;
507  nextState = Waiting;
508  if (timingFault == NoFault) {
509  /*
510  * Finish the translation. Now that we know the right entry is
511  * in the TLB, this should work with no memory accesses.
512  * There could be new faults unrelated to the table walk like
513  * permissions violations, so we'll need the return value as
514  * well.
515  */
516  Addr vaddr = req->getVaddr();
517  vaddr = Addr(sext<VADDR_BITS>(vaddr));
518  Addr paddr = walker->tlb->translateWithTLB(vaddr, satp.asid, mode);
519  req->setPaddr(paddr);
520  walker->pma->check(req);
521 
522  // do pmp check if any checking condition is met.
523  // timingFault will be NoFault if pmp checks are
524  // passed, otherwise an address fault will be returned.
525  timingFault = walker->pmp->pmpCheck(req, mode, pmode, tc);
526 
527  // Let the CPU continue.
528  translation->finish(timingFault, req, tc, mode);
529  } else {
530  // There was a fault during the walk. Let the CPU know.
531  translation->finish(timingFault, req, tc, mode);
532  }
533  return true;
534  }
535 
536  return false;
537 }
538 
539 void
541 {
542  //If we're already waiting for the port to become available, just return.
543  if (retrying)
544  return;
545 
546  //Reads always have priority
547  if (read) {
548  PacketPtr pkt = read;
549  read = NULL;
550  inflight++;
551  if (!walker->sendTiming(this, pkt)) {
552  retrying = true;
553  read = pkt;
554  inflight--;
555  return;
556  }
557  }
558  //Send off as many of the writes as we can.
559  while (writes.size()) {
560  PacketPtr write = writes.back();
561  writes.pop_back();
562  inflight++;
563  if (!walker->sendTiming(this, write)) {
564  retrying = true;
565  writes.push_back(write);
566  inflight--;
567  return;
568  }
569  }
570 }
571 
572 unsigned
574 {
575  return inflight;
576 }
577 
578 bool
580 {
581  return retrying;
582 }
583 
584 bool
586 {
587  return timing;
588 }
589 
590 bool
592 {
593  return started;
594 }
595 
596 void
598 {
599  squashed = true;
600 }
601 
602 void
604 {
605  retrying = false;
606  sendPackets();
607 }
608 
609 Fault
611 {
612  DPRINTF(PageTableWalker, "Raising page fault.\n");
613  return walker->tlb->createPagefault(entry.vaddr, mode);
614 }
615 
616 } // namespace RiscvISA
617 } // namespace gem5
gem5::X86ISA::level
Bitfield< 20 > level
Definition: intmessage.hh:51
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::BaseMMU::Translation::squashed
virtual bool squashed() const
This function is used by the page table walker to determine if it should translate the a pending requ...
Definition: mmu.hh:81
gem5::RiscvISA::PRV_S
@ PRV_S
Definition: isa.hh:55
gem5::SimObject::getPort
virtual Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a port with a given name and index.
Definition: sim_object.cc:126
gem5::RiscvISA::MISCREG_STATUS
@ MISCREG_STATUS
Definition: misc.hh:71
gem5::RiscvISA::Walker::startWalkWrapper
void startWalkWrapper()
Definition: pagetable_walker.cc:198
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::RequestPort::sendTimingReq
bool sendTimingReq(PacketPtr pkt)
Attempt to send a timing request to the responder port by calling its corresponding receive function.
Definition: port.hh:495
gem5::RiscvISA::Walker::WalkerPort::recvTimingResp
bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
Definition: pagetable_walker.cc:105
faults.hh
gem5::RiscvISA::Walker::WalkerState::req
RequestPtr req
Definition: pagetable_walker.hh:99
gem5::RiscvISA::Walker::WalkerState::wasStarted
bool wasStarted()
Definition: pagetable_walker.cc:591
gem5::RiscvISA::LEVEL_MASK
const Addr LEVEL_MASK
Definition: pagetable.hh:61
gem5::RiscvISA::Walker::WalkerState::setupWalk
void setupWalk(Addr vaddr)
Definition: pagetable_walker.cc:447
gem5::Packet::pushSenderState
void pushSenderState(SenderState *sender_state)
Push a new sender state to the packet and make the current sender state the predecessor of the new on...
Definition: packet.cc:316
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:53
gem5::Packet::req
RequestPtr req
A pointer to the original request.
Definition: packet.hh:366
gem5::BaseMMU::Write
@ Write
Definition: mmu.hh:53
gem5::RiscvISA::Walker::startFunctional
Fault startFunctional(ThreadContext *_tc, Addr &addr, unsigned &logBytes, BaseMMU::Mode mode)
Definition: pagetable_walker.cc:97
gem5::RiscvISA::Walker::WalkerSenderState
Definition: pagetable_walker.hh:156
gem5::RiscvISA::Walker::port
WalkerPort port
Definition: pagetable_walker.hh:82
gem5::RiscvISA::Walker::WalkerState::startWalk
Fault startWalk()
Definition: pagetable_walker.cc:235
gem5::RiscvISA::Walker::WalkerState::startFunctional
Fault startFunctional(Addr &addr, unsigned &logBytes)
Definition: pagetable_walker.cc:264
gem5::Request::PHYSICAL
@ PHYSICAL
The virtual address is also the physical address.
Definition: request.hh:117
gem5::RiscvISA::Walker::recvReqRetry
void recvReqRetry()
Definition: pagetable_walker.cc:145
gem5::RiscvISA::Walker::WalkerState
Definition: pagetable_walker.hh:85
gem5::EventManager::schedule
void schedule(Event &event, Tick when)
Definition: eventq.hh:1019
gem5::RiscvISA::Walker::WalkerState::recvPacket
bool recvPacket(PacketPtr pkt)
Definition: pagetable_walker.cc:473
gem5::RiscvISA::Walker::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: pagetable_walker.cc:173
gem5::Packet::headerDelay
uint32_t headerDelay
The extra delay from seeing the packet until the header is transmitted.
Definition: packet.hh:420
gem5::RiscvISA::LEVEL_BITS
const Addr LEVEL_BITS
Definition: pagetable.hh:60
gem5::RiscvISA::PageShift
const Addr PageShift
Definition: page_size.hh:53
request.hh
gem5::RiscvISA::Walker::WalkerState::mode
BaseMMU::Mode mode
Definition: pagetable_walker.hh:109
gem5::RiscvISA::Walker::WalkerState::sendPackets
void sendPackets()
Definition: pagetable_walker.cc:540
gem5::RiscvISA::Walker::numSquashable
unsigned numSquashable
Definition: pagetable_walker.hh:181
gem5::RiscvISA::Walker::start
Fault start(ThreadContext *_tc, BaseMMU::Translation *translation, const RequestPtr &req, BaseMMU::Mode mode)
Definition: pagetable_walker.cc:72
gem5::ArmISA::shift
Bitfield< 6, 5 > shift
Definition: types.hh:117
gem5::Packet::payloadDelay
uint32_t payloadDelay
The extra pipelining delay from seeing the packet until the end of payload is transmitted by the comp...
Definition: packet.hh:438
gem5::RiscvISA::Walker::WalkerState::translation
BaseMMU::Translation * translation
Definition: pagetable_walker.hh:108
gem5::RiscvISA::Walker::WalkerState::pageFault
Fault pageFault(bool present)
Definition: pagetable_walker.cc:610
gem5::X86ISA::present
Bitfield< 7 > present
Definition: misc.hh:998
gem5::Flags< FlagsType >
gem5::Packet::isRead
bool isRead() const
Definition: packet.hh:582
bitfield.hh
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
tlb.hh
gem5::RiscvISA::Walker::funcState
WalkerState funcState
Definition: pagetable_walker.hh:154
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::RiscvISA::Walker::WalkerState
friend class WalkerState
Definition: pagetable_walker.hh:149
gem5::probing::Packet
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:109
gem5::RiscvISA::MISCREG_SATP
@ MISCREG_SATP
Definition: misc.hh:180
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::MemCmd::ReadReq
@ ReadReq
Definition: packet.hh:86
gem5::RiscvISA::Walker::startWalkWrapperEvent
EventFunctionWrapper startWalkWrapperEvent
Event used to call startWalkWrapper.
Definition: pagetable_walker.hh:189
gem5::RiscvISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::System::isTimingMode
bool isTimingMode() const
Is the system in timing mode?
Definition: system.hh:276
gem5::RiscvISA::mask
mask
Definition: pra_constants.hh:73
gem5::Packet::cmd
MemCmd cmd
The command field of the packet.
Definition: packet.hh:361
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::RiscvISA::Walker::WalkerState::isRetrying
bool isRetrying()
Definition: pagetable_walker.cc:579
gem5::RiscvISA::Walker::WalkerState::numInflight
unsigned numInflight() const
Definition: pagetable_walker.cc:573
gem5::RiscvISA::Walker::WalkerPort::recvReqRetry
void recvReqRetry()
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
Definition: pagetable_walker.cc:139
gem5::RiscvISA::Walker::WalkerState::stepWalk
Fault stepWalk(PacketPtr &write)
Definition: pagetable_walker.cc:288
packet_access.hh
gem5::Clocked::clockEdge
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Definition: clocked_object.hh:177
gem5::Packet::popSenderState
SenderState * popSenderState()
Pop the top of the state stack and return a pointer to it.
Definition: packet.cc:324
gem5::BaseMMU::Translation
Definition: mmu.hh:55
gem5::RiscvISA::Walker::sys
System * sys
Definition: pagetable_walker.hh:175
gem5::RiscvISA::Walker::WalkerState::endWalk
void endWalk()
Definition: pagetable_walker.cc:439
base.hh
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::RiscvISA::Walker::WalkerState::squash
void squash()
Definition: pagetable_walker.cc:597
gem5::RiscvISA::Walker::recvTimingResp
bool recvTimingResp(PacketPtr pkt)
Definition: pagetable_walker.cc:111
gem5::RiscvISA::mode
mode
Definition: pagetable.hh:46
gem5::MemCmd::WriteReq
@ WriteReq
Definition: packet.hh:89
gem5::RiscvISA::Walker::sendTiming
bool sendTiming(WalkerState *sendingState, PacketPtr pkt)
Definition: pagetable_walker.cc:156
gem5::Packet::getLE
T getLE() const
Get the data in the packet byte swapped from little endian to host endian.
Definition: packet_access.hh:78
gem5::RiscvISA::Walker::WalkerState::retry
void retry()
Definition: pagetable_walker.cc:603
gem5::RiscvISA::Walker::WalkerState::isTiming
bool isTiming()
Definition: pagetable_walker.cc:585
gem5::Packet::setLE
void setLE(T v)
Set the value in the data pointer to v as little endian.
Definition: packet_access.hh:108
std::list
STL list class.
Definition: stl.hh:51
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:781
gem5::RiscvISA::Walker::currStates
std::list< WalkerState * > currStates
Definition: pagetable_walker.hh:152
gem5::RiscvISA::Walker::WalkerState::tc
ThreadContext * tc
Definition: pagetable_walker.hh:98
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::BaseMMU::Translation::finish
virtual void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode)=0
pagetable.hh
gem5::RiscvISA::Walker::WalkerState::initState
void initState(ThreadContext *_tc, BaseMMU::Mode _mode, bool _isTiming=false)
Definition: pagetable_walker.cc:182
gem5::RiscvISA::Walker::WalkerSenderState::senderWalk
WalkerState * senderWalk
Definition: pagetable_walker.hh:158
gem5::Packet::isResponse
bool isResponse() const
Definition: packet.hh:587
thread_context.hh
gem5::Packet::getSize
unsigned getSize() const
Definition: packet.hh:791
trie.hh
gem5::Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:465
gem5::RiscvISA::Walker::WalkerPort::walker
Walker * walker
Definition: pagetable_walker.hh:75
gem5::ArmISA::status
Bitfield< 5, 0 > status
Definition: misc_types.hh:422
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
pagetable_walker.hh

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