gem5 v24.1.0.1
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pagetable_walker.cc
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1/*
2 * Copyright (c) 2012 ARM Limited
3 * Copyright (c) 2020 Barkhausen Institut
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2007 The Hewlett-Packard Development Company
16 * All rights reserved.
17 *
18 * The license below extends only to copyright in the software and shall
19 * not be construed as granting a license to any other intellectual
20 * property including but not limited to intellectual property relating
21 * to a hardware implementation of the functionality of the software
22 * licensed hereunder. You may use the software subject to the license
23 * terms below provided that you ensure that this notice is replicated
24 * unmodified and in its entirety in all distributions of the software,
25 * modified or unmodified, in source code or in binary form.
26 *
27 * Redistribution and use in source and binary forms, with or without
28 * modification, are permitted provided that the following conditions are
29 * met: redistributions of source code must retain the above copyright
30 * notice, this list of conditions and the following disclaimer;
31 * redistributions in binary form must reproduce the above copyright
32 * notice, this list of conditions and the following disclaimer in the
33 * documentation and/or other materials provided with the distribution;
34 * neither the name of the copyright holders nor the names of its
35 * contributors may be used to endorse or promote products derived from
36 * this software without specific prior written permission.
37 *
38 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
39 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
40 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
41 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
42 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
43 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
44 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
45 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
46 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
47 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
48 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
49 */
50
52
53#include <memory>
54
55#include "arch/riscv/faults.hh"
58#include "arch/riscv/tlb.hh"
59#include "base/bitfield.hh"
60#include "base/trie.hh"
61#include "cpu/base.hh"
62#include "cpu/thread_context.hh"
63#include "debug/PageTableWalker.hh"
64#include "mem/packet_access.hh"
65#include "mem/request.hh"
66
67namespace gem5
68{
69
70namespace RiscvISA {
71
74 const RequestPtr &_req, BaseMMU::Mode _mode)
75{
76 // TODO: in timing mode, instead of blocking when there are other
77 // outstanding requests, see if this request can be coalesced with
78 // another one (i.e. either coalesce or start walk)
79 WalkerState * newState = new WalkerState(this, _translation, _req);
80 newState->initState(_tc, _mode, sys->isTimingMode());
81 if (currStates.size()) {
82 assert(newState->isTiming());
83 DPRINTF(PageTableWalker, "Walks in progress: %d\n", currStates.size());
84 currStates.push_back(newState);
85 return NoFault;
86 } else {
87 currStates.push_back(newState);
88 Fault fault = newState->startWalk();
89 if (!newState->isTiming()) {
90 currStates.pop_front();
91 delete newState;
92 }
93 return fault;
94 }
95}
96
98Walker::startFunctional(ThreadContext * _tc, Addr &addr, unsigned &logBytes,
99 BaseMMU::Mode _mode)
100{
101 funcState.initState(_tc, _mode);
102 return funcState.startFunctional(addr, logBytes);
103}
104
105bool
110
111bool
113{
114 WalkerSenderState * senderState =
115 dynamic_cast<WalkerSenderState *>(pkt->popSenderState());
116 WalkerState * senderWalk = senderState->senderWalk;
117 bool walkComplete = senderWalk->recvPacket(pkt);
118 delete senderState;
119 if (walkComplete) {
121 for (iter = currStates.begin(); iter != currStates.end(); iter++) {
122 WalkerState * walkerState = *(iter);
123 if (walkerState == senderWalk) {
124 iter = currStates.erase(iter);
125 break;
126 }
127 }
128 delete senderWalk;
129 // Since we block requests when another is outstanding, we
130 // need to check if there is a waiting request to be serviced
132 // delay sending any new requests until we are finished
133 // with the responses
135 }
136 return true;
137}
138
139void
141{
142 walker->recvReqRetry();
143}
144
145void
147{
149 for (iter = currStates.begin(); iter != currStates.end(); iter++) {
150 WalkerState * walkerState = *(iter);
151 if (walkerState->isRetrying()) {
152 walkerState->retry();
153 }
154 }
155}
156
158{
159 WalkerSenderState* walker_state = new WalkerSenderState(sendingState);
160 pkt->pushSenderState(walker_state);
161 if (port.sendTimingReq(pkt)) {
162 return true;
163 } else {
164 // undo the adding of the sender state and delete it, as we
165 // will do it again the next time we attempt to send it
166 pkt->popSenderState();
167 delete walker_state;
168 return false;
169 }
170
171}
172
173Port &
174Walker::getPort(const std::string &if_name, PortID idx)
175{
176 if (if_name == "port")
177 return port;
178 else
179 return ClockedObject::getPort(if_name, idx);
180}
181
182void
184 BaseMMU::Mode _mode, bool _isTiming)
185{
186 assert(state == Ready);
187 started = false;
188 tc = _tc;
189 mode = _mode;
190 timing = _isTiming;
191 // fetch these now in case they change during the walk
193 pmode = walker->tlb->getMemPriv(tc, mode);
194 satp = tc->readMiscReg(MISCREG_SATP);
195 assert(satp.mode == AddrXlateMode::SV39);
196}
197
198void
200{
201 unsigned num_squashed = 0;
202 WalkerState *currState = currStates.front();
203
204 // check if we get a tlb hit to skip the walk
205 Addr vaddr = Addr(sext<VADDR_BITS>(currState->req->getVaddr()));
206 Addr vpn = getVPNFromVAddr(vaddr, currState->satp.mode);
207 TlbEntry *e = tlb->lookup(vpn, currState->satp.asid, currState->mode,
208 true);
209 Fault fault = NoFault;
210 if (e) {
211 fault = tlb->checkPermissions(currState->status, currState->pmode,
212 vaddr, currState->mode, e->pte);
213 }
214
215 while ((num_squashed < numSquashable) && currState &&
216 (currState->translation->squashed() || (e && fault == NoFault))) {
217 currStates.pop_front();
218 num_squashed++;
219
220 DPRINTF(PageTableWalker, "Squashing table walk for address %#x\n",
221 currState->req->getVaddr());
222
223 // finish the translation which will delete the translation object
224 if (currState->translation->squashed()) {
225 currState->translation->finish(
226 std::make_shared<UnimpFault>("Squashed Inst"),
227 currState->req, currState->tc, currState->mode);
228 } else {
229 tlb->translateTiming(currState->req, currState->tc,
230 currState->translation, currState->mode);
231 }
232
233 // delete the current request if there are no inflight packets.
234 // if there is something in flight, delete when the packets are
235 // received and inflight is zero.
236 if (currState->numInflight() == 0) {
237 delete currState;
238 } else {
239 currState->squash();
240 }
241
242 // check the next translation request, if it exists
243 if (currStates.size()) {
244 currState = currStates.front();
245 vaddr = Addr(sext<VADDR_BITS>(currState->req->getVaddr()));
246 Addr vpn = getVPNFromVAddr(vaddr, currState->satp.mode);
247 e = tlb->lookup(vpn, currState->satp.asid, currState->mode,
248 true);
249 if (e) {
250 fault = tlb->checkPermissions(currState->status,
251 currState->pmode, vaddr,
252 currState->mode, e->pte);
253 }
254 } else {
255 currState = NULL;
256 }
257 }
258 if (currState && !currState->wasStarted()) {
259 if (!e || fault != NoFault)
260 currState->startWalk();
261 else
263 }
264}
265
266Fault
268{
269 Fault fault = NoFault;
270 assert(!started);
271 started = true;
272 setupWalk(req->getVaddr());
273 if (timing) {
274 nextState = state;
275 state = Waiting;
276 timingFault = NoFault;
277 sendPackets();
278 } else {
279 do {
280 walker->port.sendAtomic(read);
281 PacketPtr write = NULL;
282 fault = stepWalk(write);
283 assert(fault == NoFault || read == NULL);
284 state = nextState;
285 nextState = Ready;
286 if (write)
287 walker->port.sendAtomic(write);
288 } while (read);
289 state = Ready;
290 nextState = Waiting;
291 }
292 return fault;
293}
294
295Fault
297{
298 Fault fault = NoFault;
299 assert(!started);
300 started = true;
301 setupWalk(addr);
302
303 do {
304 walker->port.sendFunctional(read);
305 // On a functional access (page table lookup), writes should
306 // not happen so this pointer is ignored after stepWalk
307 PacketPtr write = NULL;
308 fault = stepWalk(write);
309 assert(fault == NoFault || read == NULL);
310 state = nextState;
311 nextState = Ready;
312 } while (read);
313 logBytes = entry.logBytes;
314 addr = entry.paddr << PageShift;
315
316 return fault;
317}
318
319Fault
321{
322 assert(state != Ready && state != Waiting);
323 Fault fault = NoFault;
324 write = NULL;
325 PTESv39 pte = read->getLE<uint64_t>();
326 Addr nextRead = 0;
327 bool doWrite = false;
328 bool doTLBInsert = false;
329 bool doEndWalk = false;
330
331 DPRINTF(PageTableWalker, "Got level%d PTE: %#x\n", level, pte);
332
333 // step 2:
334 // Performing PMA/PMP checks on physical address of PTE
335
336 // Effective privilege mode for pmp checks for page table
337 // walks is S mode according to specs
338 fault = walker->pmp->pmpCheck(read->req, BaseMMU::Read,
339 RiscvISA::PrivilegeMode::PRV_S, tc, entry.vaddr);
340
341 if (fault == NoFault) {
342 fault = walker->pma->check(read->req, BaseMMU::Read, entry.vaddr);
343 }
344
345 if (fault == NoFault) {
346 // step 3:
347 if (!pte.v || (!pte.r && pte.w)) {
348 doEndWalk = true;
349 DPRINTF(PageTableWalker, "PTE invalid, raising PF\n");
350 fault = pageFault(pte.v);
351 }
352 else {
353 // step 4:
354 if (pte.r || pte.x) {
355 // step 5: leaf PTE
356 doEndWalk = true;
357 fault = walker->tlb->checkPermissions(status, pmode,
358 entry.vaddr, mode, pte);
359
360 // step 6
361 if (fault == NoFault) {
362 if (level >= 1 && pte.ppn0 != 0) {
363 DPRINTF(PageTableWalker,
364 "PTE has misaligned PPN, raising PF\n");
365 fault = pageFault(true);
366 }
367 else if (level == 2 && pte.ppn1 != 0) {
368 DPRINTF(PageTableWalker,
369 "PTE has misaligned PPN, raising PF\n");
370 fault = pageFault(true);
371 }
372 }
373
374 if (fault == NoFault) {
375 // step 7
376 if (!pte.a) {
377 pte.a = 1;
378 doWrite = true;
379 }
380 if (!pte.d && mode == BaseMMU::Write) {
381 pte.d = 1;
382 doWrite = true;
383 }
384 // Performing PMA/PMP checks
385
386 if (doWrite) {
387
388 // this read will eventually become write
389 // if doWrite is True
390
391 fault = walker->pmp->pmpCheck(read->req,
392 BaseMMU::Write, pmode, tc, entry.vaddr);
393
394 if (fault == NoFault) {
395 fault = walker->pma->check(read->req,
396 BaseMMU::Write, entry.vaddr);
397 }
398
399 }
400 // perform step 8 only if pmp checks pass
401 if (fault == NoFault) {
402 DPRINTF(PageTableWalker,
403 "#0 leaf node at level %d, with vpn %#x\n",
404 level, entry.vaddr);
405
406 // step 8
407 entry.logBytes = PageShift + (level * LEVEL_BITS);
408 entry.paddr = pte.ppn;
409 entry.vaddr &= ~((1 << entry.logBytes) - 1);
410 entry.pte = pte;
411 // put it non-writable into the TLB to detect
412 // writes and redo the page table walk in order
413 // to update the dirty flag.
414 if (!pte.d && mode != BaseMMU::Write)
415 entry.pte.w = 0;
416 doTLBInsert = true;
417
418 // Update statistics for completed page walks
419 if (level == 1) {
420 walker->pagewalkerstats.num_2mb_walks++;
421 }
422 if (level == 0) {
423 walker->pagewalkerstats.num_4kb_walks++;
424 }
425 DPRINTF(PageTableWalker,
426 "#1 leaf node at level %d, with vpn %#x\n",
427 level, entry.vaddr);
428 }
429 }
430 } else {
431 level--;
432 if (level < 0) {
433 DPRINTF(PageTableWalker, "No leaf PTE found,"
434 "raising PF\n");
435 doEndWalk = true;
436 fault = pageFault(true);
437 } else {
439 Addr idx = (entry.vaddr >> shift) & LEVEL_MASK;
440 nextRead = (pte.ppn << PageShift) + (idx * sizeof(pte));
441 nextState = Translate;
442 }
443 }
444 }
445 } else {
446 doEndWalk = true;
447 }
448 PacketPtr oldRead = read;
449 Request::Flags flags = oldRead->req->getFlags();
450
451 if (doEndWalk) {
452 // If we need to write, adjust the read packet to write the modified
453 // value back to memory.
454 if (!functional && doWrite) {
455 DPRINTF(PageTableWalker, "Writing level%d PTE to %#x: %#x\n",
456 level, oldRead->getAddr(), pte);
457 write = oldRead;
458 write->setLE<uint64_t>(pte);
459 write->cmd = MemCmd::WriteReq;
460 read = NULL;
461 } else {
462 write = NULL;
463 }
464
465 if (doTLBInsert) {
466 if (!functional) {
467 Addr vpn = getVPNFromVAddr(entry.vaddr, satp.mode);
468 walker->tlb->insert(vpn, entry);
469 } else {
470 DPRINTF(PageTableWalker, "Translated %#x -> %#x\n",
471 entry.vaddr, entry.paddr << PageShift |
472 (entry.vaddr & mask(entry.logBytes)));
473 }
474 }
475 endWalk();
476 }
477 else {
478 //If we didn't return, we're setting up another read.
479 RequestPtr request = std::make_shared<Request>(
480 nextRead, oldRead->getSize(), flags, walker->requestorId);
481
482 delete oldRead;
483 oldRead = nullptr;
484
485 read = new Packet(request, MemCmd::ReadReq);
486 read->allocate();
487
488 DPRINTF(PageTableWalker,
489 "Loading level%d PTE from %#x\n", level, nextRead);
490 }
491
492 return fault;
493}
494
495void
497{
498 nextState = Ready;
499 delete read;
500 read = NULL;
501}
502
503void
505{
506 vaddr = Addr(sext<VADDR_BITS>(vaddr));
507
509 Addr idx = (vaddr >> shift) & LEVEL_MASK;
510 Addr topAddr = (satp.ppn << PageShift) + (idx * sizeof(PTESv39));
511 level = 2;
512
513 DPRINTF(PageTableWalker, "Performing table walk for address %#x\n", vaddr);
514 DPRINTF(PageTableWalker, "Loading level%d PTE from %#x\n", level, topAddr);
515
516 state = Translate;
517 nextState = Ready;
518 entry.vaddr = vaddr;
519 entry.asid = satp.asid;
520
522 RequestPtr request = std::make_shared<Request>(
523 topAddr, sizeof(PTESv39), flags, walker->requestorId);
524
525 read = new Packet(request, MemCmd::ReadReq);
526 read->allocate();
527}
528
529bool
531{
532 assert(pkt->isResponse());
533 assert(inflight);
534 assert(state == Waiting);
535 inflight--;
536 if (squashed) {
537 // if were were squashed, return true once inflight is zero and
538 // this WalkerState will be freed there.
539 return (inflight == 0);
540 }
541 if (pkt->isRead()) {
542 // should not have a pending read it we also had one outstanding
543 assert(!read);
544
545 // @todo someone should pay for this
546 pkt->headerDelay = pkt->payloadDelay = 0;
547
548 state = nextState;
549 nextState = Ready;
550 PacketPtr write = NULL;
551 read = pkt;
552 timingFault = stepWalk(write);
553 state = Waiting;
554 assert(timingFault == NoFault || read == NULL);
555 if (write) {
556 writes.push_back(write);
557 }
558 sendPackets();
559 } else {
560 delete pkt;
561
562 sendPackets();
563 }
564 if (inflight == 0 && read == NULL && writes.size() == 0) {
565 state = Ready;
566 nextState = Waiting;
567 if (timingFault == NoFault) {
568 /*
569 * Finish the translation. Now that we know the right entry is
570 * in the TLB, this should work with no memory accesses.
571 * There could be new faults unrelated to the table walk like
572 * permissions violations, so we'll need the return value as
573 * well.
574 */
575 Addr vaddr = req->getVaddr();
576 vaddr = Addr(sext<VADDR_BITS>(vaddr));
577 Addr paddr = walker->tlb->hiddenTranslateWithTLB(vaddr, satp.asid,
578 satp.mode, mode);
579 req->setPaddr(paddr);
580
581 // do pmp check if any checking condition is met.
582 // timingFault will be NoFault if pmp checks are
583 // passed, otherwise an address fault will be returned.
584 timingFault = walker->pmp->pmpCheck(req, mode, pmode, tc);
585
586 if (timingFault == NoFault) {
587 timingFault = walker->pma->check(req, mode);
588 }
589
590 // Let the CPU continue.
591 translation->finish(timingFault, req, tc, mode);
592 } else {
593 // There was a fault during the walk. Let the CPU know.
594 translation->finish(timingFault, req, tc, mode);
595 }
596 return true;
597 }
598
599 return false;
600}
601
602void
604{
605 //If we're already waiting for the port to become available, just return.
606 if (retrying)
607 return;
608
609 //Reads always have priority
610 if (read) {
611 PacketPtr pkt = read;
612 read = NULL;
613 inflight++;
614 if (!walker->sendTiming(this, pkt)) {
615 retrying = true;
616 read = pkt;
617 inflight--;
618 return;
619 }
620 }
621 //Send off as many of the writes as we can.
622 while (writes.size()) {
623 PacketPtr write = writes.back();
624 writes.pop_back();
625 inflight++;
626 if (!walker->sendTiming(this, write)) {
627 retrying = true;
628 writes.push_back(write);
629 inflight--;
630 return;
631 }
632 }
633}
634
635unsigned
637{
638 return inflight;
639}
640
641bool
643{
644 return retrying;
645}
646
647bool
649{
650 return timing;
651}
652
653bool
655{
656 return started;
657}
658
659void
661{
662 squashed = true;
663}
664
665void
667{
668 retrying = false;
669 sendPackets();
670}
671
672Fault
674{
675 DPRINTF(PageTableWalker, "Raising page fault.\n");
676 return walker->tlb->createPagefault(entry.vaddr, mode);
677}
678
680 : statistics::Group(parent),
681 ADD_STAT(num_4kb_walks, statistics::units::Count::get(),
682 "Completed page walks with 4KB pages"),
683 ADD_STAT(num_2mb_walks, statistics::units::Count::get(),
684 "Completed page walks with 2MB pages")
685{
686}
687
688} // namespace RiscvISA
689} // namespace gem5
#define DPRINTF(x,...)
Definition trace.hh:209
virtual bool squashed() const
This function is used by the page table walker to determine if it should translate the a pending requ...
Definition mmu.hh:84
virtual void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode)=0
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Cycles is a wrapper class for representing cycle counts, i.e.
Definition types.hh:79
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition packet.hh:295
bool isRead() const
Definition packet.hh:593
Addr getAddr() const
Definition packet.hh:807
void setLE(T v)
Set the value in the data pointer to v as little endian.
bool isResponse() const
Definition packet.hh:598
uint32_t payloadDelay
The extra pipelining delay from seeing the packet until the end of payload is transmitted by the comp...
Definition packet.hh:449
uint32_t headerDelay
The extra delay from seeing the packet until the header is transmitted.
Definition packet.hh:431
void pushSenderState(SenderState *sender_state)
Push a new sender state to the packet and make the current sender state the predecessor of the new on...
Definition packet.cc:334
SenderState * popSenderState()
Pop the top of the state stack and return a pointer to it.
Definition packet.cc:342
RequestPtr req
A pointer to the original request.
Definition packet.hh:377
unsigned getSize() const
Definition packet.hh:817
MemCmd cmd
The command field of the packet.
Definition packet.hh:372
T getLE() const
Get the data in the packet byte swapped from little endian to host endian.
Ports are used to interface objects to each other.
Definition port.hh:62
bool sendTimingReq(PacketPtr pkt)
Attempt to send a timing request to the responder port by calling its corresponding receive function.
Definition port.hh:603
@ PHYSICAL
The virtual address is also the physical address.
Definition request.hh:117
void translateTiming(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode) override
TlbEntry * lookup(Addr vpn, uint16_t asid, BaseMMU::Mode mode, bool hidden)
Perform the tlb lookup.
Definition tlb.cc:115
Fault checkPermissions(STATUS status, PrivilegeMode pmode, Addr vaddr, BaseMMU::Mode mode, PTESv39 pte)
Definition tlb.cc:251
void recvReqRetry()
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
Fault startFunctional(Addr &addr, unsigned &logBytes)
void initState(ThreadContext *_tc, BaseMMU::Mode _mode, bool _isTiming=false)
Fault startFunctional(ThreadContext *_tc, Addr &addr, unsigned &logBytes, BaseMMU::Mode mode)
EventFunctionWrapper startWalkWrapperEvent
Event used to call startWalkWrapper.
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
bool sendTiming(WalkerState *sendingState, PacketPtr pkt)
bool recvTimingResp(PacketPtr pkt)
std::list< WalkerState * > currStates
Fault start(ThreadContext *_tc, BaseMMU::Translation *translation, const RequestPtr &req, BaseMMU::Mode mode)
bool isTimingMode() const
Is the system in timing mode?
Definition system.hh:270
ThreadContext is the external interface to all thread state for anything outside of the CPU.
virtual RegVal readMiscReg(RegIndex misc_reg)=0
Statistics container.
Definition group.hh:93
STL list class.
Definition stl.hh:51
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
Definition group.hh:75
bool scheduled() const
Determine if the current event is scheduled.
Definition eventq.hh:458
void schedule(Event &event, Tick when)
Definition eventq.hh:1012
virtual Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a port with a given name and index.
atomic_var_t state
Definition helpers.cc:211
uint8_t flags
Definition helpers.cc:87
Bitfield< 9 > e
Definition misc_types.hh:65
Bitfield< 5, 0 > status
Bitfield< 6, 5 > shift
Definition types.hh:117
const Addr LEVEL_BITS
Definition pagetable.hh:61
Addr getVPNFromVAddr(Addr vaddr, Addr mode)
Definition pagetable.cc:64
const Addr PageShift
Definition page_size.hh:53
const Addr LEVEL_MASK
Definition pagetable.hh:62
@ MISCREG_STATUS
Definition misc.hh:76
Bitfield< 20 > level
Definition intmessage.hh:51
Bitfield< 7 > present
Definition misc.hh:1027
Bitfield< 3 > addr
Definition types.hh:84
Copyright (c) 2024 Arm Limited All rights reserved.
Definition binary32.hh:36
std::shared_ptr< FaultBase > Fault
Definition types.hh:249
std::shared_ptr< Request > RequestPtr
Definition request.hh:94
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition types.hh:245
constexpr decltype(nullptr) NoFault
Definition types.hh:253
Declaration of a request, the overall memory request consisting of the parts of the request that are ...
PagewalkerStats(statistics::Group *parent)

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