gem5  v21.1.0.2
Public Member Functions | Static Public Member Functions | Protected Member Functions | Private Attributes | List of all members
gem5::ArmISA::SelfDebug Class Reference

#include <self_debug.hh>

Public Member Functions

 SelfDebug ()
 
 ~SelfDebug ()
 
Fault testDebug (ThreadContext *tc, const RequestPtr &req, BaseMMU::Mode mode)
 
Fault testVectorCatch (ThreadContext *tc, Addr addr, ArmFault *flt)
 
bool enabled () const
 
BrkPointgetBrkPoint (uint8_t index)
 
bool isDebugEnabledForEL64 (ThreadContext *tc, ExceptionLevel el, bool secure, bool mask)
 
bool isDebugEnabledForEL32 (ThreadContext *tc, ExceptionLevel el, bool secure, bool mask)
 
void activateDebug ()
 
bool isDebugEnabled (ThreadContext *tc)
 
void setbSDD (RegVal val)
 
void setMDSCRvals (RegVal val)
 
void setMDBGen (RegVal val)
 
void setenableTDETGE (HCR hcr, HDCR mdcr)
 
void updateOSLock (RegVal val)
 
void updateDBGBCR (int index, DBGBCR val)
 
void updateDBGWCR (int index, DBGWCR val)
 
void setDebugMask (bool mask)
 
bool isAArch32 () const
 
void setAArch32 (ThreadContext *tc)
 
SoftwareStepgetSstep ()
 
VectorCatchgetVectorCatch (ThreadContext *tc)
 
bool targetAArch32 (ThreadContext *tc)
 
void init (ThreadContext *tc)
 

Static Public Member Functions

static bool securityStateMatch (ThreadContext *tc, uint8_t ssc, bool hmc)
 

Protected Member Functions

Fault testBreakPoints (ThreadContext *tc, Addr vaddr)
 
Fault testWatchPoints (ThreadContext *tc, Addr vaddr, bool write, bool atomic, unsigned size, bool cm)
 
Fault triggerException (ThreadContext *tc, Addr vaddr)
 
Fault triggerWatchpointException (ThreadContext *tc, Addr vaddr, bool write, bool cm)
 

Private Attributes

std::vector< BrkPointarBrkPoints
 
std::vector< WatchPointarWatchPoints
 
SoftwareStepsoftStep
 
VectorCatchvcExcpt
 
bool initialized
 
bool enableTdeTge
 
bool mde
 
bool sdd
 
bool kde
 
bool oslk
 
bool aarch32
 
bool to32
 

Detailed Description

Definition at line 277 of file self_debug.hh.

Constructor & Destructor Documentation

◆ SelfDebug()

gem5::ArmISA::SelfDebug::SelfDebug ( )
inline

Definition at line 297 of file self_debug.hh.

References softStep.

◆ ~SelfDebug()

gem5::ArmISA::SelfDebug::~SelfDebug ( )
inline

Definition at line 304 of file self_debug.hh.

References softStep, and vcExcpt.

Member Function Documentation

◆ activateDebug()

void gem5::ArmISA::SelfDebug::activateDebug ( )
inline

Definition at line 355 of file self_debug.hh.

References arBrkPoints, and gem5::MipsISA::p.

◆ enabled()

bool gem5::ArmISA::SelfDebug::enabled ( ) const
inline

Definition at line 324 of file self_debug.hh.

References gem5::ArmISA::SoftwareStep::bSS, mde, and softStep.

Referenced by isDebugEnabledForEL32().

◆ getBrkPoint()

BrkPoint* gem5::ArmISA::SelfDebug::getBrkPoint ( uint8_t  index)
inline

◆ getSstep()

SoftwareStep* gem5::ArmISA::SelfDebug::getSstep ( )
inline

Definition at line 444 of file self_debug.hh.

References softStep.

◆ getVectorCatch()

VectorCatch* gem5::ArmISA::SelfDebug::getVectorCatch ( ThreadContext tc)
inline

Definition at line 450 of file self_debug.hh.

References init(), initialized, and vcExcpt.

◆ init()

void gem5::SelfDebug::init ( ThreadContext tc)

◆ isAArch32()

bool gem5::ArmISA::SelfDebug::isAArch32 ( ) const
inline

◆ isDebugEnabled()

bool gem5::ArmISA::SelfDebug::isDebugEnabled ( ThreadContext tc)
inline

◆ isDebugEnabledForEL32()

bool gem5::SelfDebug::isDebugEnabledForEL32 ( ThreadContext tc,
ExceptionLevel  el,
bool  secure,
bool  mask 
)

◆ isDebugEnabledForEL64()

bool gem5::SelfDebug::isDebugEnabledForEL64 ( ThreadContext tc,
ExceptionLevel  el,
bool  secure,
bool  mask 
)

◆ securityStateMatch()

static bool gem5::ArmISA::SelfDebug::securityStateMatch ( ThreadContext tc,
uint8_t  ssc,
bool  hmc 
)
inlinestatic

◆ setAArch32()

void gem5::ArmISA::SelfDebug::setAArch32 ( ThreadContext tc)
inline

◆ setbSDD()

void gem5::ArmISA::SelfDebug::setbSDD ( RegVal  val)
inline

Definition at line 377 of file self_debug.hh.

References gem5::bits(), sdd, and gem5::X86ISA::val.

Referenced by init(), and gem5::ArmISA::ISA::setMiscReg().

◆ setDebugMask()

void gem5::ArmISA::SelfDebug::setDebugMask ( bool  mask)
inline

◆ setenableTDETGE()

void gem5::ArmISA::SelfDebug::setenableTDETGE ( HCR  hcr,
HDCR  mdcr 
)
inline

Definition at line 397 of file self_debug.hh.

References enableTdeTge.

Referenced by init(), and gem5::ArmISA::ISA::setMiscReg().

◆ setMDBGen()

void gem5::ArmISA::SelfDebug::setMDBGen ( RegVal  val)
inline

Definition at line 391 of file self_debug.hh.

References gem5::bits(), mde, and gem5::X86ISA::val.

Referenced by gem5::ArmISA::ISA::setMiscReg().

◆ setMDSCRvals()

void gem5::ArmISA::SelfDebug::setMDSCRvals ( RegVal  val)
inline

◆ targetAArch32()

bool gem5::ArmISA::SelfDebug::targetAArch32 ( ThreadContext tc)
inline

◆ testBreakPoints()

Fault gem5::SelfDebug::testBreakPoints ( ThreadContext tc,
Addr  vaddr 
)
protected

◆ testDebug()

Fault gem5::SelfDebug::testDebug ( ThreadContext tc,
const RequestPtr req,
BaseMMU::Mode  mode 
)

◆ testVectorCatch()

Fault gem5::SelfDebug::testVectorCatch ( ThreadContext tc,
Addr  addr,
ArmFault flt 
)

◆ testWatchPoints()

Fault gem5::SelfDebug::testWatchPoints ( ThreadContext tc,
Addr  vaddr,
bool  write,
bool  atomic,
unsigned  size,
bool  cm 
)
protected

◆ triggerException()

Fault gem5::SelfDebug::triggerException ( ThreadContext tc,
Addr  vaddr 
)
protected

◆ triggerWatchpointException()

Fault gem5::SelfDebug::triggerWatchpointException ( ThreadContext tc,
Addr  vaddr,
bool  write,
bool  cm 
)
protected

◆ updateDBGBCR()

void gem5::ArmISA::SelfDebug::updateDBGBCR ( int  index,
DBGBCR  val 
)
inline

Definition at line 409 of file self_debug.hh.

References arBrkPoints, gem5::MipsISA::index, and gem5::X86ISA::val.

Referenced by gem5::ArmISA::ISA::setMiscReg().

◆ updateDBGWCR()

void gem5::ArmISA::SelfDebug::updateDBGWCR ( int  index,
DBGWCR  val 
)
inline

Definition at line 415 of file self_debug.hh.

References arWatchPoints, gem5::MipsISA::index, and gem5::X86ISA::val.

Referenced by gem5::ArmISA::ISA::setMiscReg().

◆ updateOSLock()

void gem5::ArmISA::SelfDebug::updateOSLock ( RegVal  val)
inline

Definition at line 403 of file self_debug.hh.

References gem5::bits(), oslk, and gem5::X86ISA::val.

Referenced by init(), and gem5::ArmISA::ISA::setMiscReg().

Member Data Documentation

◆ aarch32

bool gem5::ArmISA::SelfDebug::aarch32
private

◆ arBrkPoints

std::vector<BrkPoint> gem5::ArmISA::SelfDebug::arBrkPoints
private

Definition at line 280 of file self_debug.hh.

Referenced by activateDebug(), getBrkPoint(), init(), testBreakPoints(), and updateDBGBCR().

◆ arWatchPoints

std::vector<WatchPoint> gem5::ArmISA::SelfDebug::arWatchPoints
private

Definition at line 281 of file self_debug.hh.

Referenced by init(), testWatchPoints(), and updateDBGWCR().

◆ enableTdeTge

bool gem5::ArmISA::SelfDebug::enableTdeTge
private

Definition at line 286 of file self_debug.hh.

Referenced by isDebugEnabledForEL64(), setenableTDETGE(), and testVectorCatch().

◆ initialized

bool gem5::ArmISA::SelfDebug::initialized
private

Definition at line 285 of file self_debug.hh.

Referenced by getVectorCatch(), init(), testVectorCatch(), and testWatchPoints().

◆ kde

bool gem5::ArmISA::SelfDebug::kde
private

Definition at line 290 of file self_debug.hh.

Referenced by isDebugEnabledForEL64(), and setMDSCRvals().

◆ mde

bool gem5::ArmISA::SelfDebug::mde
private

◆ oslk

bool gem5::ArmISA::SelfDebug::oslk
private

Definition at line 291 of file self_debug.hh.

Referenced by isDebugEnabledForEL32(), isDebugEnabledForEL64(), and updateOSLock().

◆ sdd

bool gem5::ArmISA::SelfDebug::sdd
private

Definition at line 289 of file self_debug.hh.

Referenced by isDebugEnabledForEL64(), and setbSDD().

◆ softStep

SoftwareStep* gem5::ArmISA::SelfDebug::softStep
private

◆ to32

bool gem5::ArmISA::SelfDebug::to32
private

◆ vcExcpt

VectorCatch* gem5::ArmISA::SelfDebug::vcExcpt
private

Definition at line 283 of file self_debug.hh.

Referenced by getVectorCatch(), init(), testVectorCatch(), and ~SelfDebug().


The documentation for this class was generated from the following files:

Generated on Tue Sep 21 2021 12:28:37 for gem5 by doxygen 1.8.17