gem5  v22.0.0.2
self_debug.cc
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1 /*
2  * Copyright (c) 2021 Arm Limited
3  * Copyright (c) 2019 Metempsy Technology LSC
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38 
39 #include "arch/arm/self_debug.hh"
40 
41 #include "arch/arm/faults.hh"
43 #include "base/bitfield.hh"
44 
45 namespace gem5
46 {
47 
48 using namespace ArmISA;
49 
50 Fault
53 {
54  Fault fault = NoFault;
55 
56  if (mode == BaseMMU::Execute) {
57  const bool d_step = softStep->advanceSS(tc);
58  if (!d_step) {
59  fault = testVectorCatch(tc, req->getVaddr(), nullptr);
60  if (fault == NoFault)
61  fault = testBreakPoints(tc, req->getVaddr());
62  }
63  } else if (!req->isCacheMaintenance() ||
64  (req->isCacheInvalidate() && !req->isCacheClean())) {
65  bool md = mode == BaseMMU::Write ? true: false;
66  fault = testWatchPoints(tc, req->getVaddr(), md,
67  req->isAtomic(),
68  req->getSize(),
69  req->isCacheMaintenance());
70  }
71 
72  return fault;
73 }
74 
75 Fault
77 {
78  if (!mde)
79  return NoFault;
80 
81  setAArch32(tc);
82 
83  to32 = targetAArch32(tc);
84 
85  init(tc);
86 
87  if (!isDebugEnabled(tc))
88  return NoFault;
89 
91  for (auto &p: arBrkPoints){
92  PCState pcst = tc->pcState().as<PCState>();
93  Addr pc = vaddr;
94  if (pcst.itstate() != 0x0)
95  pc = pcst.pc();
96  if (p.enable && p.isActive(pc) &&(!to32 || !p.onUse)) {
97  const DBGBCR ctr = p.getControlReg(tc);
98  if (p.isEnabled(tc, el, ctr.hmc, ctr.ssc, ctr.pmc)) {
99  if (p.test(tc, pc, el, ctr, false)) {
100  if (to32)
101  p.onUse = true;
102  return triggerException(tc, pc);
103  }
104  }
105  }
106  }
107  return NoFault;
108 }
109 
110 
111 Fault
113 {
114  if (to32) {
115  return std::make_shared<PrefetchAbort>(vaddr,
116  ArmFault::DebugEvent, false,
119  } else {
120  return std::make_shared<HardwareBreakpoint>(vaddr, 0x22);
121  }
122 }
123 
124 Fault
126  bool atomic, unsigned size, bool cm)
127 {
128  setAArch32(tc);
129  to32 = targetAArch32(tc);
130  if (!initialized)
131  init(tc);
132  if (!isDebugEnabled(tc) || !mde)
133  return NoFault;
134 
136  int idxtmp = -1;
137  for (auto &p: arWatchPoints){
138  idxtmp ++;
139  if (p.enable) {
140  if (p.test(tc, vaddr, el, write, atomic, size)) {
141  return triggerWatchpointException(tc, vaddr, write, cm);
142  }
143  }
144  }
145  return NoFault;
146 }
147 
148 Fault
150  bool write, bool cm)
151 {
152  if (to32) {
155  return std::make_shared<DataAbort>(vaddr,
157  write, ArmFault::DebugEvent, cm,
159  } else {
160  return std::make_shared<Watchpoint>(0, vaddr, write, cm);
161  }
162 }
163 
164 bool
166  bool secure, bool mask)
167 {
168  bool route_to_el2 = ArmSystem::haveEL(tc, EL2) &&
169  (!secure || HaveExt(tc, ArmExtension::FEAT_SEL2)) &&
170  enableTdeTge;
171 
172  ExceptionLevel target_el = route_to_el2 ? EL2 : EL1;
173  if (oslk || (sdd && secure && ArmSystem::haveEL(tc, EL3))) {
174  return false;
175  }
176 
177  if (el == target_el) {
178  return kde && !mask;
179  } else {
180  return target_el > el;
181  }
182 }
183 
184 bool
186  bool secure, bool mask)
187 {
188  if (el == EL0 && !ELStateUsingAArch32(tc, EL1, secure)) {
189  return isDebugEnabledForEL64(tc, el, secure, mask);
190  }
191 
192  if (oslk) {
193  return false;
194  }
195 
196  bool enabled;
197  if (secure && ArmSystem::haveEL(tc, EL3)) {
198  // We ignore the check for invasive External debug checking SPIDEN
199  // and DBGEN signals. They are not implemented
200  bool spd32 = bits(tc->readMiscReg(MISCREG_MDCR_EL3), 14);
201  enabled = spd32;
202 
203  bool suiden = bits(tc->readMiscReg(MISCREG_SDER), 0);
204  enabled = el == EL0 ? (enabled || suiden) : enabled;
205  } else {
206  enabled = el != EL2;
207  }
208  return enabled;
209 }
210 
211 bool
213 {
214  const DBGBCR ctr = getControlReg(tc);
215  return ((ctr.bt & 0x1) && enable) && test(tc, vaddr, el, ctr, true);
216 }
217 
218 bool
220  bool from_link)
221 {
222  bool v = false;
223  switch (ctr.bt) {
224  case 0x0:
225  v = testAddrMatch(tc, pc, ctr.bas);
226  break;
227 
228  case 0x1:
229  v = testAddrMatch(tc, pc, ctr.bas); // linked
230  if (v) {
231  v = (conf->getBrkPoint(ctr.lbn))->testLinkedBk(tc, pc, el);
232  }
233  break;
234 
235  case 0x2:
236  {
237  bool host = ELIsInHost(tc, el);
238  v = testContextMatch(tc, !host, true);
239  }
240  break;
241 
242  case 0x3:
243  if (from_link){
244  bool host = ELIsInHost(tc, el);
245  v = testContextMatch(tc, !host, true);
246  }
247  break;
248 
249  case 0x4:
250  v = testAddrMissMatch(tc, pc, ctr.bas);
251  break;
252 
253  case 0x5:
254  v = testAddrMissMatch(tc, pc, ctr.bas); // linked
255  if (v && !from_link)
256  v = v && (conf->getBrkPoint(ctr.lbn))->testLinkedBk(tc, pc, el);
257  break;
258 
259  case 0x6:
260  if (HaveExt(tc, ArmExtension::FEAT_VHE) && !ELIsInHost(tc, el))
261  v = testContextMatch(tc, true);
262  break;
263 
264  case 0x7:
265  if (HaveExt(tc, ArmExtension::FEAT_VHE) && !ELIsInHost(tc, el) &&
266  from_link)
267  v = testContextMatch(tc, true);
268  break;
269 
270  case 0x8:
271  if (EL2Enabled(tc) && !ELIsInHost(tc, el)) {
272  v = testVMIDMatch(tc);
273  }
274  break;
275 
276  case 0x9:
277  if (from_link && EL2Enabled(tc) && !ELIsInHost(tc, el)) {
278  v = testVMIDMatch(tc);
279  }
280  break;
281 
282  case 0xa:
283  if (EL2Enabled(tc) && !ELIsInHost(tc, el)) {
284  v = testContextMatch(tc, true);
285  if (v && !from_link)
286  v = v && testVMIDMatch(tc);
287  }
288  break;
289  case 0xb:
290  if (from_link && EL2Enabled(tc) && !ELIsInHost(tc, el)) {
291  v = testContextMatch(tc, true);
292  v = v && testVMIDMatch(tc);
293  }
294  break;
295 
296  case 0xc:
297  if (HaveExt(tc, ArmExtension::FEAT_VHE) &&
298  (!isSecure(tc)|| HaveExt(tc, ArmExtension::FEAT_SEL2)))
299  v = testContextMatch(tc, false);
300  break;
301 
302  case 0xd:
303  if (HaveExt(tc, ArmExtension::FEAT_VHE) && from_link &&
304  (!isSecure(tc)|| HaveExt(tc, ArmExtension::FEAT_SEL2))) {
305  v = testContextMatch(tc, false);
306  }
307  break;
308 
309  case 0xe:
310  if (HaveExt(tc, ArmExtension::FEAT_VHE) && !ELIsInHost(tc, el) &&
311  (!isSecure(tc)|| HaveExt(tc, ArmExtension::FEAT_SEL2))) {
312  v = testContextMatch(tc, true); // CONTEXTIDR_EL1
313  v = v && testContextMatch(tc, false); // CONTEXTIDR_EL2
314  }
315  break;
316  case 0xf:
317  if (HaveExt(tc, ArmExtension::FEAT_VHE) && !ELIsInHost(tc, el) &&
318  from_link &&
319  (!isSecure(tc)|| HaveExt(tc, ArmExtension::FEAT_SEL2))) {
320  v = testContextMatch(tc, true); // CONTEXTIDR_EL1
321  v = v && testContextMatch(tc, false); // CONTEXTIDR_EL2
322  }
323  break;
324  default:
325  break;
326  }
327  return v;
328 }
329 
330 void
332 {
333  if (initialized)
334  return;
335  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
336  aarch32 = cpsr.width == 1;
337 
338  const AA64DFR0 dfr = tc->readMiscReg(MISCREG_ID_AA64DFR0_EL1);
339  const AA64MMFR2 mm_fr2 = tc->readMiscReg(MISCREG_ID_AA64MMFR2_EL1);
340  const AA64MMFR1 mm_fr1 = tc->readMiscReg(MISCREG_ID_AA64MMFR1_EL1);
341 
342  for (int i = 0; i <= dfr.brps; i++) {
343  const bool isctxaw = i >= (dfr.brps - dfr.ctx_cmps);
344 
347  this, isctxaw, (bool)mm_fr2.varange,
348  mm_fr1.vmidbits, aarch32);
349  const DBGBCR ctr = tc->readMiscReg(MISCREG_DBGBCR0_EL1 + i);
350 
351  bkp.updateControl(ctr);
352  arBrkPoints.push_back(bkp);
353  }
354 
355  for (int i = 0; i <= dfr.wrps; i++) {
358  this, (bool)mm_fr2.varange, aarch32);
359  const DBGWCR ctr = tc->readMiscReg(MISCREG_DBGWCR0 + i);
360 
361  wtp.updateControl(ctr);
362  arWatchPoints.push_back(wtp);
363  }
364 
365  initialized = true;
366 
367  RegVal oslar_el1 = tc->readMiscReg(MISCREG_OSLAR_EL1);
368  updateOSLock(oslar_el1);
369  // Initialize preloaded control booleans
370  uint64_t mdscr_el1 = tc->readMiscReg(MISCREG_MDSCR_EL1);
371  setMDSCRvals(mdscr_el1);
372 
373  const uint64_t mdcr_el3 = tc->readMiscReg(MISCREG_MDCR_EL3);
374  setbSDD(mdcr_el3);
375 
376  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
377  const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
378  setenableTDETGE(hcr, mdcr);
379 
380  // Enable Vector Catch Exceptions
381  const DEVID dvid = tc->readMiscReg(MISCREG_DBGDEVID0);
382  vcExcpt = new VectorCatch(dvid.vectorcatch==0x0, this);
383 }
384 
385 bool
387 {
388  Addr pc_tocmp = getAddrfromReg(tc);
389  Addr pc = bits(in_pc, maxAddrSize, 2);
390 
391  bool prs = true;
392  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
393  bool thumb = cpsr.t;
394 
395  if (thumb) {
396  if (bas == 0xc)
397  prs = bits(in_pc, 1, 0) == 0x2;
398  else if (bas == 0x3)
399  prs = bits(in_pc, 1, 0) == 0x0;
400  }
401  return (pc == pc_tocmp) && prs;
402 }
403 
404 bool
406 {
407  if (bas == 0x0)
408  return true;
409  Addr pc_tocmp = getAddrfromReg(tc);
410  Addr pc = bits(in_pc, maxAddrSize, 2);
411  bool prs = false;
412  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
413  bool thumb = cpsr.t;
414 
415  if (thumb) {
416  if (bas == 0xc)
417  prs = bits(in_pc, 1, 0) == 0x2;
418  else if (bas == 0x3)
419  prs = bits(in_pc, 1, 0) == 0x0;
420  }
421  return (pc != pc_tocmp) && !prs;
422 }
423 
424 bool
426 {
427  return testContextMatch(tc, ctx1, ctx1);
428 }
429 
430 bool
431 BrkPoint::testContextMatch(ThreadContext *tc, bool ctx1, bool low_ctx)
432 {
433  if (!isCntxtAware)
434  return false;
435  MiscRegIndex miscridx;
436  ExceptionLevel el = currEL(tc);
437  bool a32 = conf->isAArch32();
438 
439  if (ctx1) {
440  miscridx = a32? MISCREG_CONTEXTIDR : MISCREG_CONTEXTIDR_EL1;
441  if ((el == EL3 && !a32) || el == EL2)
442  return false;
443  } else {
444  miscridx = MISCREG_CONTEXTIDR_EL2;
445  if (el == EL2 && a32)
446  return false;
447  }
448 
449  RegVal ctxid = bits(tc->readMiscReg(miscridx), 31, 0);
450  RegVal v = getContextfromReg(tc, low_ctx);
451  return (v == ctxid);
452 }
453 
454 bool
456 {
457  const bool vs = ((VTCR_t)(tc->readMiscReg(MISCREG_VTCR_EL2))).vs;
458 
459  uint32_t vmid_index = 55;
460  if (VMID16enabled && vs)
461  vmid_index = 63;
462  ExceptionLevel el = currEL(tc);
463  if (el == EL2)
464  return false;
465 
466  vmid_t vmid = bits(tc->readMiscReg(MISCREG_VTTBR_EL2), vmid_index, 48);
467  vmid_t v = getVMIDfromReg(tc, vs);
468 
469  return (v == vmid);
470 }
471 
472 
473 bool
475  uint8_t hmc, uint8_t ssc, uint8_t pmc)
476 {
477  bool v;
478  bool aarch32 = conf->isAArch32();
479  bool no_el2 = !ArmSystem::haveEL(tc, EL2);
480  bool no_el3 = !ArmSystem::haveEL(tc, EL3);
481 
482  if (no_el3 && !no_el2 && (ssc == 0x1 || ssc == 0x2) &&
483  !(hmc && ssc == 0x1 && pmc == 0x0)) {
484  return false;
485  } else if (no_el3 && no_el2 && (hmc != 0x0 || ssc != 0x0) &&
486  !(!aarch32 && ((hmc && ssc == 0x1 && pmc == 0x0) || ssc == 0x3))) {
487  return false;
488  } else if (no_el2 && hmc && ssc == 0x3 && pmc == 0x0) {
489  return false;
490  } else if (ssc == 0x11 && pmc == 0x1 &&
491  !(!aarch32 && hmc && ssc == 0x3 && pmc == 0x0)) {
492  // AND secureEL2 not implemented
493  return false;
494  } else if (hmc && ssc == 0x1 && pmc == 0x0) {
495  //AND secureEL2 not implemented
496  return false;
497  }
498  switch (el) {
499  case EL0:
500  v = (pmc == 0x3) || (pmc == 0x2 && hmc == 0x0);
501  if (aarch32)
502  v = v || (pmc == 0x0 && ssc != 0x3 && hmc == 0x0);
503  if (v && ssc == 0x3)
504  panic("Unexpected EL in SelfDebug::isDebugEnabled.\n");
505  break;
506  case EL1:
507  v = (pmc == 0x3) || (pmc == 0x1);
508  if (aarch32)
509  v = v || (pmc == 0x0 && hmc == 0x0 && ssc !=0x3);
510  break;
511  case EL2:
512  v = (ssc == 0x3) ||
513  ((hmc == 0x1) && !((ssc == 0x2) && (pmc == 0x0)));
514  if (v && pmc == 0x2)
515  panic("Unexpected EL in SelfDebug::isDebugEnabled.\n");
516  break;
517  case EL3:
518  if (ssc == 0x1)
519  panic("Unexpected EL in SelfDebug::isDebugEnabled.\n");
520  v = (hmc == 0x1) & (ssc != 0x3);
521  break;
522  default:
523  panic("Unexpected EL %d in BrkPoint::isEnabled.\n", el);
524  }
525  return v && SelfDebug::securityStateMatch(tc, ssc, hmc || !aarch32);
526 }
527 
528 vmid_t
530 {
531  uint32_t vmid_index = 39;
532  if (VMID16enabled && vs)
533  vmid_index = 47;
534  return bits(tc->readMiscReg(valRegIndex), vmid_index, 32);
535 }
536 
537 
538 bool
540  bool hmc, uint8_t ssc, uint8_t pac)
541 {
542 
543  bool v;
544  bool aarch32 = conf->isAArch32();
545  bool no_el2 = !ArmSystem::haveEL(tc, EL2);
546  bool no_el3 = !ArmSystem::haveEL(tc, EL3);
547 
548  if (aarch32) {
549  // WatchPoint PL2 using aarch32 is disabled except for
550  // debug state. Check G2-5395 table G2-15.
551  if (el == EL2)
552  return false;
553  if (no_el3) {
554  if (ssc == 0x01 || ssc == 0x02 ){
555  return false;
556  } else if (no_el2 &&
557  ((!hmc && ssc == 0x3) || (hmc && ssc == 0x0))) {
558  return false;
559  }
560  }
561  if (no_el2 && hmc && ssc == 0x03 && pac == 0)
562  return false;
563  }
564  switch (el) {
565  case EL0:
566  v = (pac == 0x3 || (pac == 0x2 && !hmc && ssc != 0x3));
567  break;
568  case EL1:
569  v = (pac == 0x1 || pac == 0x3);
570  break;
571  case EL2:
572  v = (hmc && (ssc != 0x2 || pac != 0x0));
573  break;
574  case EL3:
575  v = (hmc && (ssc == 0x2 ||
576  (ssc == 0x1 && (pac == 0x1 || pac == 0x3))));
577  break;
578  default:
579  panic("Unexpected EL in WatchPoint::isEnabled.\n");
580  }
581  return v && SelfDebug::securityStateMatch(tc, ssc, hmc);
582 }
583 
584 bool
586  bool atomic, unsigned size)
587 {
588 
589  bool v = false;
590  const DBGWCR ctr = tc->readMiscReg(ctrlRegIndex);
591  if (isEnabled(tc, el, ctr.hmc, ctr.ssc, ctr.pac) &&
592  ((wrt && (ctr.lsv & 0x2)) || (!wrt && (ctr.lsv & 0x1)) || atomic)) {
593  v = compareAddress(tc, addr, ctr.bas, ctr.mask, size);
594  if (ctr.wt) {
595  v = v && (conf->getBrkPoint(ctr.lbn))->testLinkedBk(tc, addr, el);
596  }
597  }
598  if (atomic && (ctr.lsv & 0x1)) {
599  wrt = false;
600  }
601  return v;
602 }
603 
604 bool
606  uint8_t mask, unsigned size)
607 {
608  Addr addr_tocmp = getAddrfromReg(tc);
609  int maxbits = isDoubleAligned(addr_tocmp) ? 4: 8;
610  int bottom = isDoubleAligned(addr_tocmp) ? 2: 3;
611  Addr addr = bits(in_addr, maxAddrSize, 0);
612 
613  if (bas == 0x0)
614  return false;
615 
616  if (mask == 0x0) {
617  for (int i = 0; i < maxbits; i++) {
618  uint8_t bas_m = 0x1 << i;
619  uint8_t masked_bas = bas & bas_m;
620  if (masked_bas == bas_m) {
621  uint8_t off = log2(masked_bas);
622  Addr cmpaddr = addr_tocmp | off;
623  for (int j = 0; j < size; j++) {
624  if ((addr + j) == cmpaddr) {
625  return true;
626  }
627  }
628  }
629  }
630  return false;
631  } else {
632  bool v = false;
633  for (int j = 0; j < size; j++) {
634  Addr compaddr;
635  if (mask > bottom) {
636  addr = bits((in_addr+j), maxAddrSize, mask);
637  compaddr = bits(addr_tocmp, maxAddrSize, mask);
638  } else {
639  addr = bits((in_addr+j), maxAddrSize, bottom);
640  compaddr = bits(addr_tocmp, maxAddrSize, bottom);
641  }
642  v = v || (addr == compaddr);
643  }
644  return v;
645  }
646 }
647 
648 bool
650  ExceptionLevel dest)
651 {
652  bool SS_bit = false;
653  bool enabled_src = false;
654  if (bSS) {
655  enabled_src = conf->isDebugEnabled(tc);
656 
657  bool enabled_dst = false;
658  bool secure = isSecureBelowEL3(tc) || dest == EL3;
659  if (spsr.width) {
660  enabled_dst = conf->isDebugEnabledForEL32(tc, dest, secure,
661  spsr.d == 1);
662  } else {
663  enabled_dst = conf->isDebugEnabledForEL64(tc, dest, secure,
664  spsr.d == 1);
665  }
666  ExceptionLevel ELd = debugTargetFrom(tc, secure);
667 
668  if (!ELIs32(tc, ELd) && !enabled_src && enabled_dst) {
669  SS_bit = spsr.ss;
670  if (SS_bit == 0x0) {
672  } else {
674  }
675  }
676  }
677  return SS_bit;
678 }
679 
680 bool
682 {
683  PCState pc = tc->pcState().as<PCState>();
684  bool res = false;
685  switch (stateSS) {
686  case INACTIVE_STATE:
687  pc.debugStep(false);
688  break;
689 
691  pc.debugStep(false);
692  if (cpsrD == 1 || !bSS) {
694  } else {
695  pc.stepped(true);
697  tc->pcState(pc);
698  }
699  break;
700 
702  if (!cpsrD && bSS) {
703  pc.debugStep(true);
704  res = true;
705  tc->pcState(pc);
706  }
708  clearLdx();
709  break;
710 
711  default:
712  break;
713  }
714  return res;
715 }
716 
717 Fault
719  ArmFault *fault)
720 {
721 
722  setAArch32(tc);
723  to32 = targetAArch32(tc);
724  if (!initialized)
725  init(tc);
726  if (!isDebugEnabled(tc) || !mde || !aarch32)
727  return NoFault;
728 
730  bool do_debug;
731  if (fault == nullptr)
732  do_debug = vcExcpt->addressMatching(tc, addr, el);
733  else
734  do_debug = vcExcpt->exceptionTrapping(tc, el, fault);
735  if (do_debug) {
736  if (enableTdeTge) {
737  return std::make_shared<HypervisorTrap>(0, 0x22,
739  } else {
740  return std::make_shared<PrefetchAbort>(addr,
741  ArmFault::DebugEvent, false,
744  }
745  }
746 
747  return NoFault;
748 }
749 
750 bool
752 {
753  // Each bit position in this string corresponds to a bit in DBGVCR
754  // and an exception vector.
755  bool enabled;
756  if (conf->isAArch32() && ELIs32(tc, EL1) &&
757  (addr & 0x3) == 0 && el != EL2 ) {
758 
759  DBGVCR match_word = 0x0;
760 
761  Addr vbase = getVectorBase(tc, false);
762  Addr vaddress = addr & ~ 0x1f;
763  Addr low_addr = bits(addr, 5, 2);
764  if (vaddress == vbase) {
765  if (ArmSystem::haveEL(tc, EL3) && !isSecure(tc)) {
766  uint32_t bmask = 1UL << (low_addr + 24);
767  match_word = match_word | (DBGVCR) bmask;
768  // Non-secure vectors
769  } else {
770  uint32_t bmask = 1UL << (low_addr);
771  match_word = match_word | (DBGVCR) bmask;
772  // Secure vectors (or no EL3)
773  }
774  }
775  uint32_t mvbase = getVectorBase(tc, true);
776  if (ArmSystem::haveEL(tc, EL3) && ELIs32(tc, EL3) &&
777  isSecure(tc) && (vaddress == mvbase)) {
778  uint32_t bmask = 1UL << (low_addr + 8);
779  match_word = match_word | (DBGVCR) bmask;
780  // Monitor vectors
781  }
782 
783  DBGVCR mask;
784 
785  // Mask out bits not corresponding to vectors.
786  if (!ArmSystem::haveEL(tc, EL3)) {
787  mask = (DBGVCR) 0xDE;
788  } else if (!ELIs32(tc, EL3)) {
789  mask = (DBGVCR) 0xDE0000DE;
790  } else {
791  mask = (DBGVCR) 0xDE00DEDE;
792  }
793  DBGVCR dbgvcr = tc->readMiscReg(MISCREG_DBGVCR);
794  match_word = match_word & dbgvcr & mask;
795  enabled = match_word != 0x0;
796  // Check for UNPREDICTABLE case - match on Prefetch Abort and
797  // Data Abort vectors
798  ExceptionLevel ELd = debugTargetFrom(tc, isSecure(tc));
799  if (((match_word & 0x18001818) != 0x0) && ELd == el) {
800  enabled = false;
801  }
802  } else {
803  enabled = false;
804  }
805  return enabled;
806 }
807 
808 bool
810  ArmFault* fault)
811 {
812  if (conf->isAArch32() && ELIs32(tc, EL1) && el != EL2) {
813 
814  DBGVCR dbgvcr = tc->readMiscReg(MISCREG_DBGVCR);
815  DBGVCR match_type = fault->vectorCatchFlag();
816  DBGVCR mask;
817 
818  if (!ArmSystem::haveEL(tc, EL3)) {
819  mask = (DBGVCR) 0xDE;
820  } else if (ELIs32(tc, EL3) && fault->getToMode() == MODE_MON) {
821  mask = (DBGVCR) 0x0000DE00;
822  } else {
823  if (isSecure(tc))
824  mask = (DBGVCR) 0x000000DE;
825  else
826  mask = (DBGVCR) 0xDE000000;
827  }
828  match_type = match_type & mask & dbgvcr;
829 
830  if (match_type != 0x0) {
831  return true;
832  }
833  }
834  return false;
835 }
836 
837 } // namespace gem5
gem5::ArmISA::SelfDebug::testWatchPoints
Fault testWatchPoints(ThreadContext *tc, Addr vaddr, bool write, bool atomic, unsigned size, bool cm)
Definition: self_debug.cc:125
gem5::ArmISA::WatchPoint::updateControl
void updateControl(DBGWCR val)
Definition: self_debug.hh:184
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
gem5::GenericISA::PCStateWithNext::pc
Addr pc() const
Definition: pcstate.hh:263
gem5::ArmISA::pmc
Bitfield< 2, 1 > pmc
Definition: misc_types.hh:764
gem5::ArmISA::SelfDebug::setenableTDETGE
void setenableTDETGE(HCR hcr, HDCR mdcr)
Definition: self_debug.hh:397
gem5::ArmISA::SelfDebug::init
void init(ThreadContext *tc)
Definition: self_debug.cc:331
gem5::ArmISA::EC_PREFETCH_ABORT_TO_HYP
@ EC_PREFETCH_ABORT_TO_HYP
Definition: types.hh:326
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:253
gem5::ArmISA::MODE_MON
@ MODE_MON
Definition: types.hh:292
gem5::ArmISA::MISCREG_MDCR_EL3
@ MISCREG_MDCR_EL3
Definition: misc.hh:597
gem5::ArmISA::WatchPoint::isDoubleAligned
bool isDoubleAligned(Addr addr)
Definition: self_debug.hh:178
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::ArmISA::BrkPoint::test
bool test(ThreadContext *tc, Addr pc, ExceptionLevel el, DBGBCR ctr, bool from_link)
Definition: self_debug.cc:219
gem5::ArmISA::SoftwareStep::ACTIVE_PENDING_STATE
static const uint8_t ACTIVE_PENDING_STATE
Definition: self_debug.hh:199
gem5::ArmISA::ArmFault::BRKPOINT
@ BRKPOINT
Definition: faults.hh:160
gem5::ArmISA::el
Bitfield< 3, 2 > el
Definition: misc_types.hh:73
gem5::ArmISA::MISCREG_CONTEXTIDR
@ MISCREG_CONTEXTIDR
Definition: misc.hh:400
gem5::ArmISA::BrkPoint::getContextfromReg
RegVal getContextfromReg(ThreadContext *tc, bool ctxid1) const
Definition: self_debug.hh:101
gem5::ArmISA::BrkPoint::testVMIDMatch
bool testVMIDMatch(ThreadContext *tc)
Definition: self_debug.cc:455
gem5::ArmISA::WatchPoint::ctrlRegIndex
MiscRegIndex ctrlRegIndex
Definition: self_debug.hh:150
gem5::ArmISA::SoftwareStep::cpsrD
bool cpsrD
Definition: self_debug.hh:207
gem5::ArmISA::SelfDebug::to32
bool to32
Definition: self_debug.hh:294
gem5::ArmISA::MISCREG_MDCR_EL2
@ MISCREG_MDCR_EL2
Definition: misc.hh:588
gem5::ArmISA::SelfDebug::initialized
bool initialized
Definition: self_debug.hh:285
gem5::ArmISA::SelfDebug::arBrkPoints
std::vector< BrkPoint > arBrkPoints
Definition: self_debug.hh:280
gem5::ArmISA::SoftwareStep::clearLdx
void clearLdx()
Definition: self_debug.hh:229
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:56
gem5::PCStateBase::as
Target & as()
Definition: pcstate.hh:72
gem5::ArmISA::ArmFault::VECTORCATCH
@ VECTORCATCH
Definition: faults.hh:161
gem5::BaseMMU::Write
@ Write
Definition: mmu.hh:56
gem5::ArmISA::TlbEntry::DomainType::NoAccess
@ NoAccess
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::ArmISA::BrkPoint::testAddrMissMatch
bool testAddrMissMatch(ThreadContext *tc, Addr pc, uint8_t bas)
Definition: self_debug.cc:405
gem5::ArmISA::SelfDebug::isDebugEnabledForEL64
bool isDebugEnabledForEL64(ThreadContext *tc, ExceptionLevel el, bool secure, bool mask)
Definition: self_debug.cc:165
gem5::ArmISA::SoftwareStep::bSS
bool bSS
Definition: self_debug.hh:202
gem5::ArmISA::MISCREG_DBGVCR
@ MISCREG_DBGVCR
Definition: misc.hh:102
gem5::ArmISA::isSecureBelowEL3
bool isSecureBelowEL3(ThreadContext *tc)
Definition: utility.cc:85
gem5::ArmISA::SelfDebug::vcExcpt
VectorCatch * vcExcpt
Definition: self_debug.hh:283
gem5::ArmISA::vmid_t
uint16_t vmid_t
Definition: types.hh:57
gem5::ArmISA::SelfDebug::updateOSLock
void updateOSLock(RegVal val)
Definition: self_debug.hh:403
gem5::ArmISA::VectorCatch::conf
SelfDebug * conf
Definition: self_debug.hh:246
gem5::ArmISA::SelfDebug::targetAArch32
bool targetAArch32(ThreadContext *tc)
Definition: self_debug.hh:458
gem5::ArmISA::MISCREG_CONTEXTIDR_EL1
@ MISCREG_CONTEXTIDR_EL1
Definition: misc.hh:746
gem5::ArmISA::bas
Bitfield< 8, 5 > bas
Definition: misc_types.hh:762
gem5::ArmISA::EL1
@ EL1
Definition: types.hh:274
gem5::ArmISA::ArmFault::DebugEvent
@ DebugEvent
Definition: faults.hh:105
gem5::ArmISA::SoftwareStep::debugExceptionReturnSS
bool debugExceptionReturnSS(ThreadContext *tc, CPSR spsr, ExceptionLevel dest)
Definition: self_debug.cc:649
gem5::ArmISA::SelfDebug::aarch32
bool aarch32
Definition: self_debug.hh:293
gem5::ArmISA::ELIsInHost
bool ELIsInHost(ThreadContext *tc, ExceptionLevel el)
Returns true if the current exception level el is executing a Host OS or an application of a Host OS ...
Definition: utility.cc:287
gem5::ArmISA::SelfDebug::sdd
bool sdd
Definition: self_debug.hh:289
gem5::ArmISA::SoftwareStep::advanceSS
bool advanceSS(ThreadContext *tc)
Definition: self_debug.cc:681
gem5::ArmISA::ArmFault::getToMode
OperatingMode getToMode() const
Definition: faults.hh:259
gem5::ArmISA::SelfDebug::testBreakPoints
Fault testBreakPoints(ThreadContext *tc, Addr vaddr)
Definition: self_debug.cc:76
gem5::ArmISA::SelfDebug::isDebugEnabledForEL32
bool isDebugEnabledForEL32(ThreadContext *tc, ExceptionLevel el, bool secure, bool mask)
Definition: self_debug.cc:185
gem5::ArmISA::BrkPoint::testAddrMatch
bool testAddrMatch(ThreadContext *tc, Addr pc, uint8_t bas)
Definition: self_debug.cc:386
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::PowerISA::PCState
Definition: pcstate.hh:42
gem5::ArmISA::SelfDebug::isAArch32
bool isAArch32() const
Definition: self_debug.hh:427
gem5::ArmISA::BrkPoint::valRegIndex
MiscRegIndex valRegIndex
Definition: self_debug.hh:65
gem5::ArmISA::SelfDebug::mde
bool mde
Definition: self_debug.hh:288
gem5::ArmISA::SelfDebug::testDebug
Fault testDebug(ThreadContext *tc, const RequestPtr &req, BaseMMU::Mode mode)
Definition: self_debug.cc:51
gem5::ArmISA::md
Bitfield< 12 > md
Definition: misc_types.hh:820
gem5::ArmISA::MISCREG_VTCR_EL2
@ MISCREG_VTCR_EL2
Definition: misc.hh:607
gem5::BaseMMU::Execute
@ Execute
Definition: mmu.hh:56
gem5::ArmISA::WatchPoint
Definition: self_debug.hh:147
gem5::ArmISA::atomic
Bitfield< 23, 20 > atomic
Definition: misc_types.hh:100
gem5::ArmISA::MISCREG_DBGBVR0_EL1
@ MISCREG_DBGBVR0_EL1
Definition: misc.hh:459
gem5::ArmISA::SelfDebug::setbSDD
void setbSDD(RegVal val)
Definition: self_debug.hh:377
gem5::ArmISA::BrkPoint::testContextMatch
bool testContextMatch(ThreadContext *tc, bool ctx1, bool low_ctx)
Definition: self_debug.cc:431
gem5::ArmISA::j
Bitfield< 24 > j
Definition: misc_types.hh:57
gem5::ArmISA::BrkPoint::getAddrfromReg
Addr getAddrfromReg(ThreadContext *tc) const
Definition: self_debug.hh:95
gem5::ArmISA::BrkPoint::isCntxtAware
bool isCntxtAware
Definition: self_debug.hh:67
gem5::ArmISA::SelfDebug::triggerException
Fault triggerException(ThreadContext *tc, Addr vaddr)
Definition: self_debug.cc:112
gem5::ArmISA::MISCREG_DBGWCR0
@ MISCREG_DBGWCR0
Definition: misc.hh:155
bitfield.hh
gem5::ArmISA::SelfDebug::setMDSCRvals
void setMDSCRvals(RegVal val)
Definition: self_debug.hh:383
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::ArmISA::WatchPoint::getAddrfromReg
Addr getAddrfromReg(ThreadContext *tc)
Definition: self_debug.hh:172
gem5::ArmISA::MISCREG_ID_AA64MMFR2_EL1
@ MISCREG_ID_AA64MMFR2_EL1
Definition: misc.hh:823
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
gem5::ArmISA::SoftwareStep::INACTIVE_STATE
static const uint8_t INACTIVE_STATE
Definition: self_debug.hh:198
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::ArmISA::BrkPoint::getControlReg
const DBGBCR getControlReg(ThreadContext *tc)
Definition: self_debug.hh:120
gem5::ArmISA::BrkPoint::testLinkedBk
bool testLinkedBk(ThreadContext *tc, Addr vaddr, ExceptionLevel el)
Definition: self_debug.cc:212
gem5::ArmISA::WatchPoint::test
bool test(ThreadContext *tc, Addr addr, ExceptionLevel el, bool &wrt, bool atomic, unsigned size)
Definition: self_debug.cc:585
gem5::ArmISA::VectorCatch::exceptionTrapping
bool exceptionTrapping(ThreadContext *tc, ExceptionLevel el, ArmFault *fault)
Definition: self_debug.cc:809
gem5::ArmISA::d
Bitfield< 9 > d
Definition: misc_types.hh:64
gem5::ArmISA::hmc
Bitfield< 13 > hmc
Definition: misc_types.hh:760
gem5::ArmISA::EL2
@ EL2
Definition: types.hh:275
gem5::ArmISA::ArmFault::vectorCatchFlag
virtual uint32_t vectorCatchFlag() const
Definition: faults.hh:254
misc_types.hh
gem5::ArmISA::ELIs32
bool ELIs32(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:279
gem5::ArmISA::v
Bitfield< 28 > v
Definition: misc_types.hh:54
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::ArmISA::SoftwareStep::ACTIVE_NOT_PENDING_STATE
static const uint8_t ACTIVE_NOT_PENDING_STATE
Definition: self_debug.hh:200
gem5::ArmISA::SelfDebug::securityStateMatch
static bool securityStateMatch(ThreadContext *tc, uint8_t ssc, bool hmc)
Definition: self_debug.hh:333
gem5::ArmISA::EL2Enabled
bool EL2Enabled(ThreadContext *tc)
Definition: utility.cc:264
gem5::ArmISA::ArmFault::WPOINT_NOCM
@ WPOINT_NOCM
Definition: faults.hh:163
gem5::ArmISA::mask
Bitfield< 3, 0 > mask
Definition: pcstate.hh:63
gem5::ArmISA::SelfDebug::softStep
SoftwareStep * softStep
Definition: self_debug.hh:282
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::ArmISA::BrkPoint::VMID16enabled
bool VMID16enabled
Definition: self_debug.hh:68
gem5::ArmISA::EL3
@ EL3
Definition: types.hh:276
gem5::ArmISA::SoftwareStep::stateSS
int stateSS
Definition: self_debug.hh:203
gem5::ArmISA::SoftwareStep::conf
SelfDebug * conf
Definition: self_debug.hh:204
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gem5::ArmISA::MISCREG_ID_AA64DFR0_EL1
@ MISCREG_ID_AA64DFR0_EL1
Definition: misc.hh:564
faults.hh
gem5::ArmISA::WatchPoint::isEnabled
bool isEnabled(ThreadContext *tc, ExceptionLevel el, bool hmc, uint8_t ssc, uint8_t pac)
Definition: self_debug.cc:539
gem5::ArmISA::MISCREG_ID_AA64MMFR1_EL1
@ MISCREG_ID_AA64MMFR1_EL1
Definition: misc.hh:571
gem5::ArmISA::debugTargetFrom
ExceptionLevel debugTargetFrom(ThreadContext *tc, bool secure)
Definition: utility.cc:92
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::MISCREG_DBGBCR0_EL1
@ MISCREG_DBGBCR0_EL1
Definition: misc.hh:475
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:59
gem5::ArmISA::WatchPoint::conf
SelfDebug * conf
Definition: self_debug.hh:152
gem5::ArmISA::isSecure
bool isSecure(ThreadContext *tc)
Definition: utility.cc:73
gem5::ArmISA::SelfDebug::enableTdeTge
bool enableTdeTge
Definition: self_debug.hh:286
gem5::statistics::enabled
bool enabled()
Definition: statistics.cc:286
gem5::ArmISA::pac
Bitfield< 2, 1 > pac
Definition: misc_types.hh:778
gem5::ArmISA::MISCREG_SDER
@ MISCREG_SDER
Definition: misc.hh:245
gem5::ArmISA::currEL
ExceptionLevel currEL(const ThreadContext *tc)
Returns the current Exception Level (EL) of the provided ThreadContext.
Definition: utility.cc:129
gem5::ArmISA::ArmFault
Definition: faults.hh:64
gem5::ArmISA::BrkPoint::enable
bool enable
Definition: self_debug.hh:70
gem5::ArmISA::BrkPoint
Definition: self_debug.hh:61
gem5::ArmISA::BrkPoint::getVMIDfromReg
vmid_t getVMIDfromReg(ThreadContext *tc, bool vs)
Definition: self_debug.cc:529
gem5::ArmISA::EL0
@ EL0
Definition: types.hh:273
gem5::ArmISA::WatchPoint::maxAddrSize
int maxAddrSize
Definition: self_debug.hh:154
gem5::ArmISA::SelfDebug::isDebugEnabled
bool isDebugEnabled(ThreadContext *tc)
Definition: self_debug.hh:363
gem5::ArmISA::VectorCatch
Definition: self_debug.hh:242
gem5::ArmISA::SelfDebug::testVectorCatch
Fault testVectorCatch(ThreadContext *tc, Addr addr, ArmFault *flt)
Definition: self_debug.cc:718
gem5::ArmISA::SelfDebug::getBrkPoint
BrkPoint * getBrkPoint(uint8_t index)
Definition: self_debug.hh:327
gem5::ArmISA::MISCREG_VTTBR_EL2
@ MISCREG_VTTBR_EL2
Definition: misc.hh:606
gem5::ArmISA::SelfDebug::arWatchPoints
std::vector< WatchPoint > arWatchPoints
Definition: self_debug.hh:281
gem5::ArmISA::ArmFault::WPOINT_CM
@ WPOINT_CM
Definition: faults.hh:162
gem5::ArmISA::ELStateUsingAArch32
bool ELStateUsingAArch32(ThreadContext *tc, ExceptionLevel el, bool secure)
Definition: utility.cc:371
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::ArmFault::DebugType
DebugType
Definition: faults.hh:157
gem5::ArmISA::vs
Bitfield< 19 > vs
Definition: misc_types.hh:570
gem5::ArmISA::SelfDebug::oslk
bool oslk
Definition: self_debug.hh:291
gem5::ArmISA::cm
Bitfield< 13 > cm
Definition: misc_types.hh:429
gem5::ArmISA::SelfDebug::kde
bool kde
Definition: self_debug.hh:290
gem5::ArmISA::MISCREG_DBGDEVID0
@ MISCREG_DBGDEVID0
Definition: misc.hh:198
gem5::ArmISA::MISCREG_CONTEXTIDR_EL2
@ MISCREG_CONTEXTIDR_EL2
Definition: misc.hh:818
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::ArmISA::SelfDebug::enabled
bool enabled() const
Definition: self_debug.hh:324
gem5::ArmISA::thumb
Bitfield< 36 > thumb
Definition: types.hh:79
gem5::ArmISA::ssc
Bitfield< 15, 14 > ssc
Definition: misc_types.hh:759
gem5::ArmISA::BrkPoint::conf
SelfDebug * conf
Definition: self_debug.hh:66
self_debug.hh
gem5::ArmISA::BrkPoint::updateControl
void updateControl(DBGBCR val)
Definition: self_debug.hh:141
gem5::ArmISA::BrkPoint::isEnabled
bool isEnabled(ThreadContext *tc, ExceptionLevel el, uint8_t hmc, uint8_t ssc, uint8_t pmc)
Definition: self_debug.cc:474
gem5::ArmSystem::haveEL
static bool haveEL(ThreadContext *tc, ArmISA::ExceptionLevel el)
Return true if the system implements a specific exception level.
Definition: system.cc:131
gem5::ArmISA::MISCREG_HCR_EL2
@ MISCREG_HCR_EL2
Definition: misc.hh:587
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::ArmISA::BrkPoint::maxAddrSize
int maxAddrSize
Definition: self_debug.hh:71
gem5::ArmISA::MISCREG_MDSCR_EL1
@ MISCREG_MDSCR_EL1
Definition: misc.hh:456
gem5::ArmISA::SelfDebug::triggerWatchpointException
Fault triggerWatchpointException(ThreadContext *tc, Addr vaddr, bool write, bool cm)
Definition: self_debug.cc:149
gem5::ArmISA::HaveExt
bool HaveExt(ThreadContext *tc, ArmExtension ext)
Returns true if the provided ThreadContext supports the ArmExtension passed as a second argument.
Definition: utility.cc:229
gem5::ArmISA::VectorCatch::addressMatching
bool addressMatching(ThreadContext *tc, Addr addr, ExceptionLevel el)
Definition: self_debug.cc:751
gem5::ArmISA::WatchPoint::compareAddress
bool compareAddress(ThreadContext *tc, Addr in_addr, uint8_t bas, uint8_t mask, unsigned size)
Definition: self_debug.cc:605
gem5::ArmISA::ArmFault::UnknownTran
@ UnknownTran
Definition: faults.hh:154
gem5::ArmISA::MISCREG_OSLAR_EL1
@ MISCREG_OSLAR_EL1
Definition: misc.hh:529
gem5::ArmISA::SelfDebug::setAArch32
void setAArch32(ThreadContext *tc)
Definition: self_debug.hh:433
gem5::ArmISA::VectorCatch::getVectorBase
Addr getVectorBase(ThreadContext *tc, bool monitor)
Definition: self_debug.hh:261
gem5::ArmISA::MISCREG_DBGWVR0
@ MISCREG_DBGWVR0
Definition: misc.hh:139
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:271
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:74
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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