gem5  v21.1.0.2
self_debug.cc
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1 /*
2  * Copyright (c) 2021 Arm Limited
3  * Copyright (c) 2019 Metempsy Technology LSC
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38 
39 #include "arch/arm/self_debug.hh"
40 
41 #include "arch/arm/faults.hh"
43 #include "base/bitfield.hh"
44 
45 namespace gem5
46 {
47 
48 using namespace ArmISA;
49 
50 Fault
53 {
54  Fault fault = NoFault;
55 
56  if (mode == BaseMMU::Execute) {
57  const bool d_step = softStep->advanceSS(tc);
58  if (!d_step) {
59  fault = testVectorCatch(tc, req->getVaddr(), nullptr);
60  if (fault == NoFault)
61  fault = testBreakPoints(tc, req->getVaddr());
62  }
63  } else if (!req->isCacheMaintenance() ||
64  (req->isCacheInvalidate() && !req->isCacheClean())) {
65  bool md = mode == BaseMMU::Write ? true: false;
66  fault = testWatchPoints(tc, req->getVaddr(), md,
67  req->isAtomic(),
68  req->getSize(),
69  req->isCacheMaintenance());
70  }
71 
72  return fault;
73 }
74 
75 Fault
77 {
78  if (!mde)
79  return NoFault;
80 
81  setAArch32(tc);
82 
83  to32 = targetAArch32(tc);
84 
85  init(tc);
86 
87  if (!isDebugEnabled(tc))
88  return NoFault;
89 
91  for (auto &p: arBrkPoints){
92  PCState pcst = tc->pcState();
93  Addr pc = vaddr;
94  if (pcst.itstate() != 0x0)
95  pc = pcst.pc();
96  if (p.enable && p.isActive(pc) &&(!to32 || !p.onUse)) {
97  const DBGBCR ctr = p.getControlReg(tc);
98  if (p.isEnabled(tc, el, ctr.hmc, ctr.ssc, ctr.pmc)) {
99  if (p.test(tc, pc, el, ctr, false)) {
100  if (to32)
101  p.onUse = true;
102  return triggerException(tc, pc);
103  }
104  }
105  }
106  }
107  return NoFault;
108 }
109 
110 
111 Fault
113 {
114  if (to32) {
115  return std::make_shared<PrefetchAbort>(vaddr,
116  ArmFault::DebugEvent, false,
119  } else {
120  return std::make_shared<HardwareBreakpoint>(vaddr, 0x22);
121  }
122 }
123 
124 Fault
126  bool atomic, unsigned size, bool cm)
127 {
128  setAArch32(tc);
129  to32 = targetAArch32(tc);
130  if (!initialized)
131  init(tc);
132  if (!isDebugEnabled(tc) || !mde)
133  return NoFault;
134 
136  int idxtmp = -1;
137  for (auto &p: arWatchPoints){
138  idxtmp ++;
139  if (p.enable) {
140  if (p.test(tc, vaddr, el, write, atomic, size)) {
141  return triggerWatchpointException(tc, vaddr, write, cm);
142  }
143  }
144  }
145  return NoFault;
146 }
147 
148 Fault
150  bool write, bool cm)
151 {
152  if (to32) {
155  return std::make_shared<DataAbort>(vaddr,
157  write, ArmFault::DebugEvent, cm,
159  } else {
160  return std::make_shared<Watchpoint>(0, vaddr, write, cm);
161  }
162 }
163 
164 bool
166  bool secure, bool mask)
167 {
168  bool route_to_el2 = ArmSystem::haveEL(tc, EL2) &&
169  (!secure || HaveSecureEL2Ext(tc)) && enableTdeTge;
170 
171  ExceptionLevel target_el = route_to_el2 ? EL2 : EL1;
172  if (oslk || (sdd && secure && ArmSystem::haveEL(tc, EL3))) {
173  return false;
174  }
175 
176  if (el == target_el) {
177  return kde && !mask;
178  } else {
179  return target_el > el;
180  }
181 }
182 
183 bool
185  bool secure, bool mask)
186 {
187  if (el == EL0 && !ELStateUsingAArch32(tc, EL1, secure)) {
188  return isDebugEnabledForEL64(tc, el, secure, mask);
189  }
190 
191  if (oslk) {
192  return false;
193  }
194 
195  bool enabled;
196  if (secure && ArmSystem::haveEL(tc, EL3)) {
197  // We ignore the check for invasive External debug checking SPIDEN
198  // and DBGEN signals. They are not implemented
199  bool spd32 = bits(tc->readMiscReg(MISCREG_MDCR_EL3), 14);
200  enabled = spd32;
201 
202  bool suiden = bits(tc->readMiscReg(MISCREG_SDER), 0);
203  enabled = el == EL0 ? (enabled || suiden) : enabled;
204  } else {
205  enabled = el != EL2;
206  }
207  return enabled;
208 }
209 
210 bool
212 {
213  const DBGBCR ctr = getControlReg(tc);
214  return ((ctr.bt & 0x1) && enable) && test(tc, vaddr, el, ctr, true);
215 }
216 
217 bool
219  bool from_link)
220 {
221  bool v = false;
222  switch (ctr.bt) {
223  case 0x0:
224  v = testAddrMatch(tc, pc, ctr.bas);
225  break;
226 
227  case 0x1:
228  v = testAddrMatch(tc, pc, ctr.bas); // linked
229  if (v) {
230  v = (conf->getBrkPoint(ctr.lbn))->testLinkedBk(tc, pc, el);
231  }
232  break;
233 
234  case 0x2:
235  {
236  bool host = ELIsInHost(tc, el);
237  v = testContextMatch(tc, !host, true);
238  }
239  break;
240 
241  case 0x3:
242  if (from_link){
243  bool host = ELIsInHost(tc, el);
244  v = testContextMatch(tc, !host, true);
245  }
246  break;
247 
248  case 0x4:
249  v = testAddrMissMatch(tc, pc, ctr.bas);
250  break;
251 
252  case 0x5:
253  v = testAddrMissMatch(tc, pc, ctr.bas); // linked
254  if (v && !from_link)
255  v = v && (conf->getBrkPoint(ctr.lbn))->testLinkedBk(tc, pc, el);
256  break;
257 
258  case 0x6:
259  if (HaveVirtHostExt(tc) && !ELIsInHost(tc, el))
260  v = testContextMatch(tc, true);
261  break;
262 
263  case 0x7:
264  if (HaveVirtHostExt(tc) && !ELIsInHost(tc, el) && from_link)
265  v = testContextMatch(tc, true);
266  break;
267 
268  case 0x8:
269  if (EL2Enabled(tc) && !ELIsInHost(tc, el)) {
270  v = testVMIDMatch(tc);
271  }
272  break;
273 
274  case 0x9:
275  if (from_link && EL2Enabled(tc) && !ELIsInHost(tc, el)) {
276  v = testVMIDMatch(tc);
277  }
278  break;
279 
280  case 0xa:
281  if (EL2Enabled(tc) && !ELIsInHost(tc, el)) {
282  v = testContextMatch(tc, true);
283  if (v && !from_link)
284  v = v && testVMIDMatch(tc);
285  }
286  break;
287  case 0xb:
288  if (from_link && EL2Enabled(tc) && !ELIsInHost(tc, el)) {
289  v = testContextMatch(tc, true);
290  v = v && testVMIDMatch(tc);
291  }
292  break;
293 
294  case 0xc:
295  if (HaveVirtHostExt(tc) && (!isSecure(tc)|| HaveSecureEL2Ext(tc)))
296  v = testContextMatch(tc, false);
297  break;
298 
299  case 0xd:
300  if (HaveVirtHostExt(tc) && from_link &&
301  (!isSecure(tc)|| HaveSecureEL2Ext(tc))) {
302  v = testContextMatch(tc, false);
303  }
304  break;
305 
306  case 0xe:
307  if (HaveVirtHostExt(tc) && !ELIsInHost(tc, el) &&
308  (!isSecure(tc)|| HaveSecureEL2Ext(tc))) {
309  v = testContextMatch(tc, true); // CONTEXTIDR_EL1
310  v = v && testContextMatch(tc, false); // CONTEXTIDR_EL2
311  }
312  break;
313  case 0xf:
314  if (HaveVirtHostExt(tc) && !ELIsInHost(tc, el) && from_link &&
315  (!isSecure(tc)|| HaveSecureEL2Ext(tc))) {
316  v = testContextMatch(tc, true); // CONTEXTIDR_EL1
317  v = v && testContextMatch(tc, false); // CONTEXTIDR_EL2
318  }
319  break;
320  default:
321  break;
322  }
323  return v;
324 }
325 
326 void
328 {
329  if (initialized)
330  return;
331  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
332  aarch32 = cpsr.width == 1;
333 
334  const AA64DFR0 dfr = tc->readMiscReg(MISCREG_ID_AA64DFR0_EL1);
335  const AA64MMFR2 mm_fr2 = tc->readMiscReg(MISCREG_ID_AA64MMFR2_EL1);
336  const AA64MMFR1 mm_fr1 = tc->readMiscReg(MISCREG_ID_AA64MMFR1_EL1);
337 
338  for (int i = 0; i <= dfr.brps; i++) {
339  const bool isctxaw = i >= (dfr.brps - dfr.ctx_cmps);
340 
343  this, isctxaw, (bool)mm_fr2.varange,
344  mm_fr1.vmidbits, aarch32);
345  const DBGBCR ctr = tc->readMiscReg(MISCREG_DBGBCR0_EL1 + i);
346 
347  bkp.updateControl(ctr);
348  arBrkPoints.push_back(bkp);
349  }
350 
351  for (int i = 0; i <= dfr.wrps; i++) {
354  this, (bool)mm_fr2.varange, aarch32);
355  const DBGWCR ctr = tc->readMiscReg(MISCREG_DBGWCR0 + i);
356 
357  wtp.updateControl(ctr);
358  arWatchPoints.push_back(wtp);
359  }
360 
361  initialized = true;
362 
363  RegVal oslar_el1 = tc->readMiscReg(MISCREG_OSLAR_EL1);
364  updateOSLock(oslar_el1);
365  // Initialize preloaded control booleans
366  uint64_t mdscr_el1 = tc->readMiscReg(MISCREG_MDSCR_EL1);
367  setMDSCRvals(mdscr_el1);
368 
369  const uint64_t mdcr_el3 = tc->readMiscReg(MISCREG_MDCR_EL3);
370  setbSDD(mdcr_el3);
371 
372  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
373  const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
374  setenableTDETGE(hcr, mdcr);
375 
376  // Enable Vector Catch Exceptions
377  const DEVID dvid = tc->readMiscReg(MISCREG_DBGDEVID0);
378  vcExcpt = new VectorCatch(dvid.vectorcatch==0x0, this);
379 }
380 
381 bool
383 {
384  Addr pc_tocmp = getAddrfromReg(tc);
385  Addr pc = bits(in_pc, maxAddrSize, 2);
386 
387  bool prs = true;
388  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
389  bool thumb = cpsr.t;
390 
391  if (thumb) {
392  if (bas == 0xc)
393  prs = bits(in_pc, 1, 0) == 0x2;
394  else if (bas == 0x3)
395  prs = bits(in_pc, 1, 0) == 0x0;
396  }
397  return (pc == pc_tocmp) && prs;
398 }
399 
400 bool
402 {
403  if (bas == 0x0)
404  return true;
405  Addr pc_tocmp = getAddrfromReg(tc);
406  Addr pc = bits(in_pc, maxAddrSize, 2);
407  bool prs = false;
408  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
409  bool thumb = cpsr.t;
410 
411  if (thumb) {
412  if (bas == 0xc)
413  prs = bits(in_pc, 1, 0) == 0x2;
414  else if (bas == 0x3)
415  prs = bits(in_pc, 1, 0) == 0x0;
416  }
417  return (pc != pc_tocmp) && !prs;
418 }
419 
420 bool
422 {
423  return testContextMatch(tc, ctx1, ctx1);
424 }
425 
426 bool
427 BrkPoint::testContextMatch(ThreadContext *tc, bool ctx1, bool low_ctx)
428 {
429  if (!isCntxtAware)
430  return false;
431  MiscRegIndex miscridx;
432  ExceptionLevel el = currEL(tc);
433  bool a32 = conf->isAArch32();
434 
435  if (ctx1) {
436  miscridx = a32? MISCREG_CONTEXTIDR : MISCREG_CONTEXTIDR_EL1;
437  if ((el == EL3 && !a32) || el == EL2)
438  return false;
439  } else {
440  miscridx = MISCREG_CONTEXTIDR_EL2;
441  if (el == EL2 && a32)
442  return false;
443  }
444 
445  RegVal ctxid = bits(tc->readMiscReg(miscridx), 31, 0);
446  RegVal v = getContextfromReg(tc, low_ctx);
447  return (v == ctxid);
448 }
449 
450 bool
452 {
453  const bool vs = ((VTCR_t)(tc->readMiscReg(MISCREG_VTCR_EL2))).vs;
454 
455  uint32_t vmid_index = 55;
456  if (VMID16enabled && vs)
457  vmid_index = 63;
458  ExceptionLevel el = currEL(tc);
459  if (el == EL2)
460  return false;
461 
462  vmid_t vmid = bits(tc->readMiscReg(MISCREG_VTTBR_EL2), vmid_index, 48);
463  vmid_t v = getVMIDfromReg(tc, vs);
464 
465  return (v == vmid);
466 }
467 
468 
469 bool
471  uint8_t hmc, uint8_t ssc, uint8_t pmc)
472 {
473  bool v;
474  bool aarch32 = conf->isAArch32();
475  bool no_el2 = !ArmSystem::haveEL(tc, EL2);
476  bool no_el3 = !ArmSystem::haveEL(tc, EL3);
477 
478  if (no_el3 && !no_el2 && (ssc == 0x1 || ssc == 0x2) &&
479  !(hmc && ssc == 0x1 && pmc == 0x0)) {
480  return false;
481  } else if (no_el3 && no_el2 && (hmc != 0x0 || ssc != 0x0) &&
482  !(!aarch32 && ((hmc && ssc == 0x1 && pmc == 0x0) || ssc == 0x3))) {
483  return false;
484  } else if (no_el2 && hmc && ssc == 0x3 && pmc == 0x0) {
485  return false;
486  } else if (ssc == 0x11 && pmc == 0x1 &&
487  !(!aarch32 && hmc && ssc == 0x3 && pmc == 0x0)) {
488  // AND secureEL2 not implemented
489  return false;
490  } else if (hmc && ssc == 0x1 && pmc == 0x0) {
491  //AND secureEL2 not implemented
492  return false;
493  }
494  switch (el) {
495  case EL0:
496  v = (pmc == 0x3) || (pmc == 0x2 && hmc == 0x0);
497  if (aarch32)
498  v = v || (pmc == 0x0 && ssc != 0x3 && hmc == 0x0);
499  if (v && ssc == 0x3)
500  panic("Unexpected EL in SelfDebug::isDebugEnabled.\n");
501  break;
502  case EL1:
503  v = (pmc == 0x3) || (pmc == 0x1);
504  if (aarch32)
505  v = v || (pmc == 0x0 && hmc == 0x0 && ssc !=0x3);
506  break;
507  case EL2:
508  v = (ssc == 0x3) ||
509  ((hmc == 0x1) && !((ssc == 0x2) && (pmc == 0x0)));
510  if (v && pmc == 0x2)
511  panic("Unexpected EL in SelfDebug::isDebugEnabled.\n");
512  break;
513  case EL3:
514  if (ssc == 0x1)
515  panic("Unexpected EL in SelfDebug::isDebugEnabled.\n");
516  v = (hmc == 0x1) & (ssc != 0x3);
517  break;
518  default:
519  panic("Unexpected EL %d in BrkPoint::isEnabled.\n", el);
520  }
521  return v && SelfDebug::securityStateMatch(tc, ssc, hmc || !aarch32);
522 }
523 
524 vmid_t
526 {
527  uint32_t vmid_index = 39;
528  if (VMID16enabled && vs)
529  vmid_index = 47;
530  return bits(tc->readMiscReg(valRegIndex), vmid_index, 32);
531 }
532 
533 
534 bool
536  bool hmc, uint8_t ssc, uint8_t pac)
537 {
538 
539  bool v;
540  bool aarch32 = conf->isAArch32();
541  bool no_el2 = !ArmSystem::haveEL(tc, EL2);
542  bool no_el3 = !ArmSystem::haveEL(tc, EL3);
543 
544  if (aarch32) {
545  // WatchPoint PL2 using aarch32 is disabled except for
546  // debug state. Check G2-5395 table G2-15.
547  if (el == EL2)
548  return false;
549  if (no_el3) {
550  if (ssc == 0x01 || ssc == 0x02 ){
551  return false;
552  } else if (no_el2 &&
553  ((!hmc && ssc == 0x3) || (hmc && ssc == 0x0))) {
554  return false;
555  }
556  }
557  if (no_el2 && hmc && ssc == 0x03 && pac == 0)
558  return false;
559  }
560  switch (el) {
561  case EL0:
562  v = (pac == 0x3 || (pac == 0x2 && !hmc && ssc != 0x3));
563  break;
564  case EL1:
565  v = (pac == 0x1 || pac == 0x3);
566  break;
567  case EL2:
568  v = (hmc && (ssc != 0x2 || pac != 0x0));
569  break;
570  case EL3:
571  v = (hmc && (ssc == 0x2 ||
572  (ssc == 0x1 && (pac == 0x1 || pac == 0x3))));
573  break;
574  default:
575  panic("Unexpected EL in WatchPoint::isEnabled.\n");
576  }
577  return v && SelfDebug::securityStateMatch(tc, ssc, hmc);
578 }
579 
580 bool
582  bool atomic, unsigned size)
583 {
584 
585  bool v = false;
586  const DBGWCR ctr = tc->readMiscReg(ctrlRegIndex);
587  if (isEnabled(tc, el, ctr.hmc, ctr.ssc, ctr.pac) &&
588  ((wrt && (ctr.lsv & 0x2)) || (!wrt && (ctr.lsv & 0x1)) || atomic)) {
589  v = compareAddress(tc, addr, ctr.bas, ctr.mask, size);
590  if (ctr.wt) {
591  v = v && (conf->getBrkPoint(ctr.lbn))->testLinkedBk(tc, addr, el);
592  }
593  }
594  if (atomic && (ctr.lsv & 0x1)) {
595  wrt = false;
596  }
597  return v;
598 }
599 
600 bool
602  uint8_t mask, unsigned size)
603 {
604  Addr addr_tocmp = getAddrfromReg(tc);
605  int maxbits = isDoubleAligned(addr_tocmp) ? 4: 8;
606  int bottom = isDoubleAligned(addr_tocmp) ? 2: 3;
607  Addr addr = bits(in_addr, maxAddrSize, 0);
608 
609  if (bas == 0x0)
610  return false;
611 
612  if (mask == 0x0) {
613  for (int i = 0; i < maxbits; i++) {
614  uint8_t bas_m = 0x1 << i;
615  uint8_t masked_bas = bas & bas_m;
616  if (masked_bas == bas_m) {
617  uint8_t off = log2(masked_bas);
618  Addr cmpaddr = addr_tocmp | off;
619  for (int j = 0; j < size; j++) {
620  if ((addr + j) == cmpaddr) {
621  return true;
622  }
623  }
624  }
625  }
626  return false;
627  } else {
628  bool v = false;
629  for (int j = 0; j < size; j++) {
630  Addr compaddr;
631  if (mask > bottom) {
632  addr = bits((in_addr+j), maxAddrSize, mask);
633  compaddr = bits(addr_tocmp, maxAddrSize, mask);
634  } else {
635  addr = bits((in_addr+j), maxAddrSize, bottom);
636  compaddr = bits(addr_tocmp, maxAddrSize, bottom);
637  }
638  v = v || (addr == compaddr);
639  }
640  return v;
641  }
642 }
643 
644 bool
646  ExceptionLevel dest)
647 {
648  bool SS_bit = false;
649  bool enabled_src = false;
650  if (bSS) {
651  enabled_src = conf->isDebugEnabled(tc);
652 
653  bool enabled_dst = false;
654  bool secure = isSecureBelowEL3(tc) || dest == EL3;
655  if (spsr.width) {
656  enabled_dst = conf->isDebugEnabledForEL32(tc, dest, secure,
657  spsr.d == 1);
658  } else {
659  enabled_dst = conf->isDebugEnabledForEL64(tc, dest, secure,
660  spsr.d == 1);
661  }
662  ExceptionLevel ELd = debugTargetFrom(tc, secure);
663 
664  if (!ELIs32(tc, ELd) && !enabled_src && enabled_dst) {
665  SS_bit = spsr.ss;
666  if (SS_bit == 0x0) {
668  } else {
670  }
671  }
672  }
673  return SS_bit;
674 }
675 
676 bool
678 {
679 
680  PCState pc = tc->pcState();
681  bool res = false;
682  switch (stateSS) {
683  case INACTIVE_STATE:
684  pc.debugStep(false);
685  break;
686 
688  pc.debugStep(false);
689  if (cpsrD == 1 || !bSS) {
691  } else {
692  pc.stepped(true);
694  tc->pcState(pc);
695  }
696  break;
697 
699  if (!cpsrD && bSS) {
700  pc.debugStep(true);
701  res = true;
702  tc->pcState(pc);
703  }
705  clearLdx();
706  break;
707 
708  default:
709  break;
710  }
711  return res;
712 }
713 
714 Fault
716  ArmFault *fault)
717 {
718 
719  setAArch32(tc);
720  to32 = targetAArch32(tc);
721  if (!initialized)
722  init(tc);
723  if (!isDebugEnabled(tc) || !mde || !aarch32)
724  return NoFault;
725 
727  bool do_debug;
728  if (fault == nullptr)
729  do_debug = vcExcpt->addressMatching(tc, addr, el);
730  else
731  do_debug = vcExcpt->exceptionTrapping(tc, el, fault);
732  if (do_debug) {
733  if (enableTdeTge) {
734  return std::make_shared<HypervisorTrap>(0, 0x22,
736  } else {
737  return std::make_shared<PrefetchAbort>(addr,
738  ArmFault::DebugEvent, false,
741  }
742  }
743 
744  return NoFault;
745 }
746 
747 bool
749 {
750  // Each bit position in this string corresponds to a bit in DBGVCR
751  // and an exception vector.
752  bool enabled;
753  if (conf->isAArch32() && ELIs32(tc, EL1) &&
754  (addr & 0x3) == 0 && el != EL2 ) {
755 
756  DBGVCR match_word = 0x0;
757 
758  Addr vbase = getVectorBase(tc, false);
759  Addr vaddress = addr & ~ 0x1f;
760  Addr low_addr = bits(addr, 5, 2);
761  if (vaddress == vbase) {
762  if (ArmSystem::haveEL(tc, EL3) && !isSecure(tc)) {
763  uint32_t bmask = 1UL << (low_addr + 24);
764  match_word = match_word | (DBGVCR) bmask;
765  // Non-secure vectors
766  } else {
767  uint32_t bmask = 1UL << (low_addr);
768  match_word = match_word | (DBGVCR) bmask;
769  // Secure vectors (or no EL3)
770  }
771  }
772  uint32_t mvbase = getVectorBase(tc, true);
773  if (ArmSystem::haveEL(tc, EL3) && ELIs32(tc, EL3) &&
774  isSecure(tc) && (vaddress == mvbase)) {
775  uint32_t bmask = 1UL << (low_addr + 8);
776  match_word = match_word | (DBGVCR) bmask;
777  // Monitor vectors
778  }
779 
780  DBGVCR mask;
781 
782  // Mask out bits not corresponding to vectors.
783  if (!ArmSystem::haveEL(tc, EL3)) {
784  mask = (DBGVCR) 0xDE;
785  } else if (!ELIs32(tc, EL3)) {
786  mask = (DBGVCR) 0xDE0000DE;
787  } else {
788  mask = (DBGVCR) 0xDE00DEDE;
789  }
790  DBGVCR dbgvcr = tc->readMiscReg(MISCREG_DBGVCR);
791  match_word = match_word & dbgvcr & mask;
792  enabled = match_word != 0x0;
793  // Check for UNPREDICTABLE case - match on Prefetch Abort and
794  // Data Abort vectors
795  ExceptionLevel ELd = debugTargetFrom(tc, isSecure(tc));
796  if (((match_word & 0x18001818) != 0x0) && ELd == el) {
797  enabled = false;
798  }
799  } else {
800  enabled = false;
801  }
802  return enabled;
803 }
804 
805 bool
807  ArmFault* fault)
808 {
809  if (conf->isAArch32() && ELIs32(tc, EL1) && el != EL2) {
810 
811  DBGVCR dbgvcr = tc->readMiscReg(MISCREG_DBGVCR);
812  DBGVCR match_type = fault->vectorCatchFlag();
813  DBGVCR mask;
814 
815  if (!ArmSystem::haveEL(tc, EL3)) {
816  mask = (DBGVCR) 0xDE;
817  } else if (ELIs32(tc, EL3) && fault->getToMode() == MODE_MON) {
818  mask = (DBGVCR) 0x0000DE00;
819  } else {
820  if (isSecure(tc))
821  mask = (DBGVCR) 0x000000DE;
822  else
823  mask = (DBGVCR) 0xDE000000;
824  }
825  match_type = match_type & mask & dbgvcr;
826 
827  if (match_type != 0x0) {
828  return true;
829  }
830  }
831  return false;
832 }
833 
834 } // namespace gem5
gem5::ArmISA::SelfDebug::testWatchPoints
Fault testWatchPoints(ThreadContext *tc, Addr vaddr, bool write, bool atomic, unsigned size, bool cm)
Definition: self_debug.cc:125
gem5::ArmISA::WatchPoint::updateControl
void updateControl(DBGWCR val)
Definition: self_debug.hh:184
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
gem5::ArmISA::pmc
Bitfield< 2, 1 > pmc
Definition: misc_types.hh:711
gem5::ArmISA::SelfDebug::setenableTDETGE
void setenableTDETGE(HCR hcr, HDCR mdcr)
Definition: self_debug.hh:397
gem5::ArmISA::SelfDebug::init
void init(ThreadContext *tc)
Definition: self_debug.cc:327
gem5::ArmISA::EC_PREFETCH_ABORT_TO_HYP
@ EC_PREFETCH_ABORT_TO_HYP
Definition: types.hh:319
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::ArmISA::MODE_MON
@ MODE_MON
Definition: types.hh:285
gem5::ArmISA::MISCREG_MDCR_EL3
@ MISCREG_MDCR_EL3
Definition: misc.hh:596
gem5::ArmISA::WatchPoint::isDoubleAligned
bool isDoubleAligned(Addr addr)
Definition: self_debug.hh:178
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::ArmISA::BrkPoint::test
bool test(ThreadContext *tc, Addr pc, ExceptionLevel el, DBGBCR ctr, bool from_link)
Definition: self_debug.cc:218
gem5::ArmISA::cm
Bitfield< 13 > cm
Definition: misc_types.hh:428
gem5::ArmISA::SoftwareStep::ACTIVE_PENDING_STATE
static const uint8_t ACTIVE_PENDING_STATE
Definition: self_debug.hh:199
gem5::ArmISA::ArmFault::BRKPOINT
@ BRKPOINT
Definition: faults.hh:160
gem5::ArmISA::el
Bitfield< 3, 2 > el
Definition: misc_types.hh:72
gem5::ArmISA::MISCREG_CONTEXTIDR
@ MISCREG_CONTEXTIDR
Definition: misc.hh:399
gem5::ArmISA::BrkPoint::getContextfromReg
RegVal getContextfromReg(ThreadContext *tc, bool ctxid1) const
Definition: self_debug.hh:101
gem5::ArmISA::BrkPoint::testVMIDMatch
bool testVMIDMatch(ThreadContext *tc)
Definition: self_debug.cc:451
gem5::ArmISA::WatchPoint::ctrlRegIndex
MiscRegIndex ctrlRegIndex
Definition: self_debug.hh:150
gem5::ArmISA::SoftwareStep::cpsrD
bool cpsrD
Definition: self_debug.hh:207
gem5::ArmISA::SelfDebug::to32
bool to32
Definition: self_debug.hh:294
gem5::ArmISA::MISCREG_MDCR_EL2
@ MISCREG_MDCR_EL2
Definition: misc.hh:587
gem5::ArmISA::SelfDebug::initialized
bool initialized
Definition: self_debug.hh:285
gem5::ArmISA::SelfDebug::arBrkPoints
std::vector< BrkPoint > arBrkPoints
Definition: self_debug.hh:280
gem5::ArmISA::SoftwareStep::clearLdx
void clearLdx()
Definition: self_debug.hh:229
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:53
gem5::ArmISA::ArmFault::VECTORCATCH
@ VECTORCATCH
Definition: faults.hh:161
gem5::BaseMMU::Write
@ Write
Definition: mmu.hh:53
gem5::ArmISA::TlbEntry::DomainType::NoAccess
@ NoAccess
gem5::ArmISA::BrkPoint::testAddrMissMatch
bool testAddrMissMatch(ThreadContext *tc, Addr pc, uint8_t bas)
Definition: self_debug.cc:401
gem5::ArmISA::SelfDebug::isDebugEnabledForEL64
bool isDebugEnabledForEL64(ThreadContext *tc, ExceptionLevel el, bool secure, bool mask)
Definition: self_debug.cc:165
gem5::ArmISA::SoftwareStep::bSS
bool bSS
Definition: self_debug.hh:202
gem5::ArmISA::MISCREG_DBGVCR
@ MISCREG_DBGVCR
Definition: misc.hh:101
gem5::ArmISA::isSecureBelowEL3
bool isSecureBelowEL3(ThreadContext *tc)
Definition: utility.cc:84
gem5::ArmISA::SelfDebug::vcExcpt
VectorCatch * vcExcpt
Definition: self_debug.hh:283
gem5::ArmISA::vmid_t
uint16_t vmid_t
Definition: types.hh:57
gem5::ArmISA::currEL
static ExceptionLevel currEL(const ThreadContext *tc)
Definition: utility.hh:119
gem5::ArmISA::SelfDebug::updateOSLock
void updateOSLock(RegVal val)
Definition: self_debug.hh:403
gem5::ArmISA::VectorCatch::conf
SelfDebug * conf
Definition: self_debug.hh:246
gem5::ArmISA::SelfDebug::targetAArch32
bool targetAArch32(ThreadContext *tc)
Definition: self_debug.hh:458
gem5::ArmISA::MISCREG_CONTEXTIDR_EL1
@ MISCREG_CONTEXTIDR_EL1
Definition: misc.hh:745
gem5::ArmISA::bas
Bitfield< 8, 5 > bas
Definition: misc_types.hh:709
gem5::ArmISA::EL1
@ EL1
Definition: types.hh:267
gem5::ArmISA::ArmFault::DebugEvent
@ DebugEvent
Definition: faults.hh:105
gem5::ArmISA::SoftwareStep::debugExceptionReturnSS
bool debugExceptionReturnSS(ThreadContext *tc, CPSR spsr, ExceptionLevel dest)
Definition: self_debug.cc:645
gem5::ArmISA::SelfDebug::aarch32
bool aarch32
Definition: self_debug.hh:293
gem5::ArmISA::ELIsInHost
bool ELIsInHost(ThreadContext *tc, ExceptionLevel el)
Returns true if the current exception level el is executing a Host OS or an application of a Host OS ...
Definition: utility.cc:297
gem5::ArmISA::SelfDebug::sdd
bool sdd
Definition: self_debug.hh:289
gem5::ArmISA::SoftwareStep::advanceSS
bool advanceSS(ThreadContext *tc)
Definition: self_debug.cc:677
gem5::ArmISA::ArmFault::getToMode
OperatingMode getToMode() const
Definition: faults.hh:257
gem5::ArmISA::SelfDebug::testBreakPoints
Fault testBreakPoints(ThreadContext *tc, Addr vaddr)
Definition: self_debug.cc:76
gem5::ArmISA::SelfDebug::isDebugEnabledForEL32
bool isDebugEnabledForEL32(ThreadContext *tc, ExceptionLevel el, bool secure, bool mask)
Definition: self_debug.cc:184
gem5::ArmISA::BrkPoint::testAddrMatch
bool testAddrMatch(ThreadContext *tc, Addr pc, uint8_t bas)
Definition: self_debug.cc:382
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::PowerISA::PCState
Definition: pcstate.hh:42
gem5::ArmISA::SelfDebug::isAArch32
bool isAArch32() const
Definition: self_debug.hh:427
gem5::ArmISA::BrkPoint::valRegIndex
MiscRegIndex valRegIndex
Definition: self_debug.hh:65
gem5::ArmISA::SelfDebug::mde
bool mde
Definition: self_debug.hh:288
gem5::ArmISA::SelfDebug::testDebug
Fault testDebug(ThreadContext *tc, const RequestPtr &req, BaseMMU::Mode mode)
Definition: self_debug.cc:51
gem5::ArmISA::md
Bitfield< 12 > md
Definition: misc_types.hh:767
gem5::ArmISA::MISCREG_VTCR_EL2
@ MISCREG_VTCR_EL2
Definition: misc.hh:606
gem5::BaseMMU::Execute
@ Execute
Definition: mmu.hh:53
gem5::ArmISA::WatchPoint
Definition: self_debug.hh:147
gem5::ArmISA::atomic
Bitfield< 23, 20 > atomic
Definition: misc_types.hh:99
gem5::ArmISA::MISCREG_DBGBVR0_EL1
@ MISCREG_DBGBVR0_EL1
Definition: misc.hh:458
gem5::ArmISA::SelfDebug::setbSDD
void setbSDD(RegVal val)
Definition: self_debug.hh:377
gem5::ArmISA::BrkPoint::testContextMatch
bool testContextMatch(ThreadContext *tc, bool ctx1, bool low_ctx)
Definition: self_debug.cc:427
gem5::ArmISA::j
Bitfield< 24 > j
Definition: misc_types.hh:57
gem5::ArmISA::BrkPoint::getAddrfromReg
Addr getAddrfromReg(ThreadContext *tc) const
Definition: self_debug.hh:95
gem5::ArmISA::BrkPoint::isCntxtAware
bool isCntxtAware
Definition: self_debug.hh:67
gem5::ArmISA::SelfDebug::triggerException
Fault triggerException(ThreadContext *tc, Addr vaddr)
Definition: self_debug.cc:112
gem5::ArmISA::MISCREG_DBGWCR0
@ MISCREG_DBGWCR0
Definition: misc.hh:154
bitfield.hh
gem5::ArmISA::SelfDebug::setMDSCRvals
void setMDSCRvals(RegVal val)
Definition: self_debug.hh:383
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::ArmISA::WatchPoint::getAddrfromReg
Addr getAddrfromReg(ThreadContext *tc)
Definition: self_debug.hh:172
gem5::ArmISA::MISCREG_ID_AA64MMFR2_EL1
@ MISCREG_ID_AA64MMFR2_EL1
Definition: misc.hh:822
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::ArmISA::SoftwareStep::INACTIVE_STATE
static const uint8_t INACTIVE_STATE
Definition: self_debug.hh:198
gem5::ArmISA::HaveVirtHostExt
bool HaveVirtHostExt(ThreadContext *tc)
Definition: utility.cc:224
gem5::ArmISA::BrkPoint::getControlReg
const DBGBCR getControlReg(ThreadContext *tc)
Definition: self_debug.hh:120
gem5::ArmISA::BrkPoint::testLinkedBk
bool testLinkedBk(ThreadContext *tc, Addr vaddr, ExceptionLevel el)
Definition: self_debug.cc:211
gem5::ArmISA::WatchPoint::test
bool test(ThreadContext *tc, Addr addr, ExceptionLevel el, bool &wrt, bool atomic, unsigned size)
Definition: self_debug.cc:581
gem5::ArmISA::VectorCatch::exceptionTrapping
bool exceptionTrapping(ThreadContext *tc, ExceptionLevel el, ArmFault *fault)
Definition: self_debug.cc:806
gem5::ArmISA::d
Bitfield< 9 > d
Definition: misc_types.hh:63
gem5::ArmISA::hmc
Bitfield< 13 > hmc
Definition: misc_types.hh:707
gem5::ArmISA::EL2
@ EL2
Definition: types.hh:268
gem5::ArmISA::ArmFault::vectorCatchFlag
virtual uint32_t vectorCatchFlag() const
Definition: faults.hh:251
misc_types.hh
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::ArmISA::ELIs32
bool ELIs32(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:288
gem5::ArmISA::v
Bitfield< 28 > v
Definition: misc_types.hh:54
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::ArmISA::SoftwareStep::ACTIVE_NOT_PENDING_STATE
static const uint8_t ACTIVE_NOT_PENDING_STATE
Definition: self_debug.hh:200
gem5::ArmISA::SelfDebug::securityStateMatch
static bool securityStateMatch(ThreadContext *tc, uint8_t ssc, bool hmc)
Definition: self_debug.hh:333
gem5::ArmISA::EL2Enabled
bool EL2Enabled(ThreadContext *tc)
Definition: utility.cc:274
gem5::ArmISA::ArmFault::WPOINT_NOCM
@ WPOINT_NOCM
Definition: faults.hh:163
gem5::ArmISA::mask
Bitfield< 3, 0 > mask
Definition: pcstate.hh:63
gem5::ArmISA::SelfDebug::softStep
SoftwareStep * softStep
Definition: self_debug.hh:282
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::ArmISA::BrkPoint::VMID16enabled
bool VMID16enabled
Definition: self_debug.hh:68
gem5::ArmISA::EL3
@ EL3
Definition: types.hh:269
gem5::ArmISA::SoftwareStep::stateSS
int stateSS
Definition: self_debug.hh:203
gem5::ArmISA::SoftwareStep::conf
SelfDebug * conf
Definition: self_debug.hh:204
gem5::ThreadContext::pcState
virtual TheISA::PCState pcState() const =0
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gem5::ArmISA::MISCREG_ID_AA64DFR0_EL1
@ MISCREG_ID_AA64DFR0_EL1
Definition: misc.hh:563
faults.hh
gem5::ArmISA::WatchPoint::isEnabled
bool isEnabled(ThreadContext *tc, ExceptionLevel el, bool hmc, uint8_t ssc, uint8_t pac)
Definition: self_debug.cc:535
gem5::ArmISA::MISCREG_ID_AA64MMFR1_EL1
@ MISCREG_ID_AA64MMFR1_EL1
Definition: misc.hh:570
gem5::ArmISA::debugTargetFrom
ExceptionLevel debugTargetFrom(ThreadContext *tc, bool secure)
Definition: utility.cc:91
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::MISCREG_DBGBCR0_EL1
@ MISCREG_DBGBCR0_EL1
Definition: misc.hh:474
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:59
gem5::ArmISA::WatchPoint::conf
SelfDebug * conf
Definition: self_debug.hh:152
gem5::ArmISA::isSecure
bool isSecure(ThreadContext *tc)
Definition: utility.cc:72
gem5::ArmISA::SelfDebug::enableTdeTge
bool enableTdeTge
Definition: self_debug.hh:286
gem5::statistics::enabled
bool enabled()
Definition: statistics.cc:280
gem5::ArmISA::pac
Bitfield< 2, 1 > pac
Definition: misc_types.hh:725
gem5::ArmISA::MISCREG_SDER
@ MISCREG_SDER
Definition: misc.hh:244
gem5::ArmISA::ArmFault
Definition: faults.hh:64
gem5::ArmISA::BrkPoint::enable
bool enable
Definition: self_debug.hh:70
gem5::ArmISA::BrkPoint
Definition: self_debug.hh:61
gem5::ArmISA::BrkPoint::getVMIDfromReg
vmid_t getVMIDfromReg(ThreadContext *tc, bool vs)
Definition: self_debug.cc:525
gem5::ArmISA::EL0
@ EL0
Definition: types.hh:266
gem5::ArmISA::WatchPoint::maxAddrSize
int maxAddrSize
Definition: self_debug.hh:154
gem5::ArmISA::SelfDebug::isDebugEnabled
bool isDebugEnabled(ThreadContext *tc)
Definition: self_debug.hh:363
gem5::ArmISA::VectorCatch
Definition: self_debug.hh:242
gem5::ArmISA::SelfDebug::testVectorCatch
Fault testVectorCatch(ThreadContext *tc, Addr addr, ArmFault *flt)
Definition: self_debug.cc:715
gem5::ArmISA::SelfDebug::getBrkPoint
BrkPoint * getBrkPoint(uint8_t index)
Definition: self_debug.hh:327
gem5::ArmISA::MISCREG_VTTBR_EL2
@ MISCREG_VTTBR_EL2
Definition: misc.hh:605
gem5::ArmISA::SelfDebug::arWatchPoints
std::vector< WatchPoint > arWatchPoints
Definition: self_debug.hh:281
gem5::ArmISA::ArmFault::WPOINT_CM
@ WPOINT_CM
Definition: faults.hh:162
gem5::ArmISA::ELStateUsingAArch32
bool ELStateUsingAArch32(ThreadContext *tc, ExceptionLevel el, bool secure)
Definition: utility.cc:378
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::ArmFault::DebugType
DebugType
Definition: faults.hh:157
gem5::ArmISA::HaveSecureEL2Ext
bool HaveSecureEL2Ext(ThreadContext *tc)
Definition: utility.cc:253
gem5::ArmISA::vs
Bitfield< 19 > vs
Definition: misc_types.hh:569
gem5::ArmISA::SelfDebug::oslk
bool oslk
Definition: self_debug.hh:291
gem5::ArmISA::SelfDebug::kde
bool kde
Definition: self_debug.hh:290
gem5::ArmISA::MISCREG_DBGDEVID0
@ MISCREG_DBGDEVID0
Definition: misc.hh:197
gem5::ArmISA::MISCREG_CONTEXTIDR_EL2
@ MISCREG_CONTEXTIDR_EL2
Definition: misc.hh:817
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::ArmISA::SelfDebug::enabled
bool enabled() const
Definition: self_debug.hh:324
gem5::ArmISA::thumb
Bitfield< 36 > thumb
Definition: types.hh:79
gem5::ArmISA::ssc
Bitfield< 15, 14 > ssc
Definition: misc_types.hh:706
gem5::ArmISA::BrkPoint::conf
SelfDebug * conf
Definition: self_debug.hh:66
self_debug.hh
gem5::ArmISA::BrkPoint::updateControl
void updateControl(DBGBCR val)
Definition: self_debug.hh:141
gem5::ArmISA::BrkPoint::isEnabled
bool isEnabled(ThreadContext *tc, ExceptionLevel el, uint8_t hmc, uint8_t ssc, uint8_t pmc)
Definition: self_debug.cc:470
gem5::ArmSystem::haveEL
static bool haveEL(ThreadContext *tc, ArmISA::ExceptionLevel el)
Return true if the system implements a specific exception level.
Definition: system.cc:138
gem5::ArmISA::MISCREG_HCR_EL2
@ MISCREG_HCR_EL2
Definition: misc.hh:586
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::BrkPoint::maxAddrSize
int maxAddrSize
Definition: self_debug.hh:71
gem5::ArmISA::MISCREG_MDSCR_EL1
@ MISCREG_MDSCR_EL1
Definition: misc.hh:455
gem5::GenericISA::SimplePCState::pc
Addr pc() const
Definition: types.hh:151
gem5::ArmISA::SelfDebug::triggerWatchpointException
Fault triggerWatchpointException(ThreadContext *tc, Addr vaddr, bool write, bool cm)
Definition: self_debug.cc:149
gem5::ArmISA::VectorCatch::addressMatching
bool addressMatching(ThreadContext *tc, Addr addr, ExceptionLevel el)
Definition: self_debug.cc:748
gem5::ArmISA::WatchPoint::compareAddress
bool compareAddress(ThreadContext *tc, Addr in_addr, uint8_t bas, uint8_t mask, unsigned size)
Definition: self_debug.cc:601
gem5::ArmISA::ArmFault::UnknownTran
@ UnknownTran
Definition: faults.hh:154
gem5::ArmISA::MISCREG_OSLAR_EL1
@ MISCREG_OSLAR_EL1
Definition: misc.hh:528
gem5::ArmISA::SelfDebug::setAArch32
void setAArch32(ThreadContext *tc)
Definition: self_debug.hh:433
gem5::ArmISA::VectorCatch::getVectorBase
Addr getVectorBase(ThreadContext *tc, bool monitor)
Definition: self_debug.hh:261
gem5::ArmISA::MISCREG_DBGWVR0
@ MISCREG_DBGWVR0
Definition: misc.hh:138
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:264
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:73
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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