gem5  v21.1.0.2
self_debug.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2021 Arm Limited
3  * Copyright (c) 2019 Metempsy Technology LSC
4  * All rights reserved
5  *
6  * The license below extends only to copyright in the software and shall
7  * not be construed as granting a license to any other intellectual
8  * property including but not limited to intellectual property relating
9  * to a hardware implementation of the functionality of the software
10  * licensed hereunder. You may use the software subject to the license
11  * terms below provided that you ensure that this notice is replicated
12  * unmodified and in its entirety in all distributions of the software,
13  * modified or unmodified, in source code or in binary form.
14  *
15  * Redistribution and use in source and binary forms, with or without
16  * modification, are permitted provided that the following conditions are
17  * met: redistributions of source code must retain the above copyright
18  * notice, this list of conditions and the following disclaimer;
19  * redistributions in binary form must reproduce the above copyright
20  * notice, this list of conditions and the following disclaimer in the
21  * documentation and/or other materials provided with the distribution;
22  * neither the name of the copyright holders nor the names of its
23  * contributors may be used to endorse or promote products derived from
24  * this software without specific prior written permission.
25  *
26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37  */
38 
39 #ifndef __ARCH_ARM_SELF_DEBUG_HH__
40 #define __ARCH_ARM_SELF_DEBUG_HH__
41 
42 
43 #include "arch/arm/faults.hh"
44 #include "arch/arm/regs/misc.hh"
45 #include "arch/arm/system.hh"
46 #include "arch/arm/types.hh"
47 #include "arch/arm/utility.hh"
48 #include "arch/generic/tlb.hh"
49 #include "cpu/thread_context.hh"
50 
51 namespace gem5
52 {
53 
54 class ThreadContext;
55 
56 namespace ArmISA
57 {
58 
59 class SelfDebug;
60 
61 class BrkPoint
62 {
63  private:
70  bool enable;
72  bool onUse;
73 
74  public:
75  friend class SelfDebug;
76 
77  BrkPoint(MiscRegIndex ctrl_index, MiscRegIndex val_index,
78  SelfDebug* _conf, bool ctx_aw, bool lva,
79  bool vmid16, bool aarch32):
80  ctrlRegIndex(ctrl_index), valRegIndex(val_index),
81  conf(_conf), isCntxtAware(ctx_aw),
82  VMID16enabled(vmid16), activePc(0x0), enable(false)
83  {
84  maxAddrSize = lva ? 52: 48 ;
85  maxAddrSize = aarch32 ? 31 : maxAddrSize;
86  onUse = false;
87  }
88 
90  bool test(ThreadContext *tc, Addr pc, ExceptionLevel el, DBGBCR ctr,
91  bool from_link);
92 
93  protected:
94  inline Addr
96  {
97  return bits(tc->readMiscReg(valRegIndex), maxAddrSize, 2);
98  }
99 
100  inline RegVal
101  getContextfromReg(ThreadContext *tc, bool ctxid1) const
102  {
103  if (ctxid1)
104  return bits(tc->readMiscReg(valRegIndex), 31, 0);
105  else
106  return bits(tc->readMiscReg(valRegIndex), 63, 32);
107  }
108 
109 
111 
112  public:
113  bool testAddrMatch(ThreadContext *tc, Addr pc, uint8_t bas);
114  bool testAddrMissMatch(ThreadContext *tc, Addr pc, uint8_t bas);
115  bool testContextMatch(ThreadContext *tc, bool ctx1, bool low_ctx);
116  bool testContextMatch(ThreadContext *tc, bool ctx1);
117  bool testVMIDMatch(ThreadContext *tc);
118 
119  const DBGBCR
121  {
122  return tc->readMiscReg(ctrlRegIndex);
123  }
124 
126  uint8_t hmc, uint8_t ssc, uint8_t pmc);
127 
128  bool
130  {
131  if (vaddr == activePc) {
132  activePc = 0x0;
133  return false;
134  } else {
135  activePc = vaddr;
136  return true;
137  }
138  }
139 
140  inline void
142  {
143  enable = val.e == 0x1;
144  }
145 };
146 
148 {
149  private:
153  bool enable;
155 
156  public:
157  friend class SelfDebug;
158 
159  WatchPoint(MiscRegIndex ctrl_index, MiscRegIndex val_index,
160  SelfDebug* _conf, bool lva, bool aarch32) :
161  ctrlRegIndex(ctrl_index),
162  valRegIndex(val_index), conf(_conf), enable(false)
163  {
164  maxAddrSize = lva ? 52: 48 ;
165  maxAddrSize = aarch32 ? 31 : maxAddrSize;
166  }
167 
168  bool compareAddress(ThreadContext *tc, Addr in_addr,
169  uint8_t bas, uint8_t mask, unsigned size);
170 
171  inline Addr
173  {
174  return bits(tc->readMiscReg(valRegIndex), maxAddrSize, 0);
175  }
176 
177  inline bool
179  {
180  return addr & 0x4;
181  }
182 
183  inline void
185  {
186  enable = val.e == 0x1;
187  }
188 
189  bool isEnabled(ThreadContext* tc, ExceptionLevel el, bool hmc,
190  uint8_t ssc, uint8_t pac);
191  bool test(ThreadContext *tc, Addr addr, ExceptionLevel el, bool& wrt,
192  bool atomic, unsigned size);
193 };
194 
196 {
197  private:
198  static const uint8_t INACTIVE_STATE = 0;
199  static const uint8_t ACTIVE_PENDING_STATE = 1;
200  static const uint8_t ACTIVE_NOT_PENDING_STATE = 2;
201 
202  bool bSS;
203  int stateSS;
207  bool cpsrD;
208 
209  public:
210  friend class SelfDebug;
211 
213  : bSS(false), stateSS(INACTIVE_STATE),
214  conf(s), steppedLdx(false)
215  {}
216 
217  bool debugExceptionReturnSS(ThreadContext *tc, CPSR spsr,
218  ExceptionLevel dest);
219  bool advanceSS(ThreadContext *tc);
220 
221  void
223  {
225  steppedLdx = true;
226  }
227 
228  void
230  {
232  steppedLdx = false;
233  }
234 
235  bool
236  getLdx() const
237  {
238  return prevSteppedLdx;
239  }
240 };
241 
243 {
244  private:
245  bool vcmatch;
248 
249  public:
250  VectorCatch(bool _vcmatch, SelfDebug* s) : vcmatch(_vcmatch), conf(s)
251  {}
252 
255  ArmFault* fault);
256 
257  bool isVCMatch() const { return vcmatch; }
258 
259  private:
260  Addr
261  getVectorBase(ThreadContext *tc, bool monitor)
262  {
263  if (monitor) {
264  return tc->readMiscReg(MISCREG_MVBAR) & ~0x1F;
265  }
266  SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
267  if (sctlr.v) {
268  return (Addr) 0xFFFF0000;
269  } else {
270  Addr vbar = tc->readMiscReg(MISCREG_VBAR) & ~0x1F;
271  return vbar;
272  }
273  }
274 
275 };
276 
278 {
279  private:
284 
286  bool enableTdeTge; // MDCR_EL2.TDE || HCR_EL2.TGE
287 
288  bool mde; // MDSCR_EL1.MDE, DBGDSCRext.MDBGen
289  bool sdd; // MDCR_EL3.SDD
290  bool kde; // MDSCR_EL1.KDE
291  bool oslk; // OS lock flag
292 
293  bool aarch32; // updates with stage1 aarch64/32
294  bool to32;
295 
296  public:
298  : initialized(false), enableTdeTge(false),
299  mde(false), sdd(false), kde(false), oslk(false)
300  {
301  softStep = new SoftwareStep(this);
302  }
303 
305  {
306  delete softStep;
307  delete vcExcpt;
308  }
309 
310  Fault testDebug(ThreadContext *tc, const RequestPtr &req,
312 
313  protected:
315  Fault testWatchPoints(ThreadContext *tc, Addr vaddr, bool write,
316  bool atomic, unsigned size, bool cm);
317 
320  bool write, bool cm);
321  public:
323 
324  bool enabled() const { return mde || softStep->bSS; };
325 
326  inline BrkPoint*
328  {
329  return &arBrkPoints[index];
330  }
331 
332  static inline bool
334  {
335  switch (ssc) {
336  case 0x0: return true;
337  case 0x1: return !isSecure(tc);
338  case 0x2: return isSecure(tc);
339  case 0x3:
340  {
341  bool b = hmc? true: isSecure(tc);
342  return b;
343  }
344  default: panic("Unreachable value");
345  }
346  return false;
347  }
348 
350  bool secure, bool mask);
352  bool secure, bool mask);
353 
354  void
356  {
357  for (auto &p: arBrkPoints){
358  p.onUse = false;
359  }
360  }
361 
362  inline bool
364  {
365  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
367  if (aarch32) {
368  return isDebugEnabledForEL32(tc, el, isSecure(tc),
369  (bool)cpsr.d == 1);
370  } else {
371  return isDebugEnabledForEL64(tc, el, isSecure(tc),
372  (bool)cpsr.d == 1 );
373  }
374  }
375 
376  inline void
378  {
379  sdd = bits(val, 16);
380  }
381 
382  inline void
384  {
385  mde = bits(val, 15);
386  kde = bits(val, 13);
387  softStep->bSS = bits(val, 0);
388  }
389 
390  inline void
392  {
393  mde = bits(val, 15);
394  }
395 
396  inline void
397  setenableTDETGE(HCR hcr, HDCR mdcr)
398  {
399  enableTdeTge = (mdcr.tde == 0x1 || hcr.tge == 0x1);
400  }
401 
402  inline void
404  {
405  oslk = bool(bits(val, 0));
406  }
407 
408  inline void
409  updateDBGBCR(int index, DBGBCR val)
410  {
411  arBrkPoints[index].updateControl(val);
412  }
413 
414  inline void
415  updateDBGWCR(int index, DBGWCR val)
416  {
417  arWatchPoints[index].updateControl(val);
418  }
419 
420  inline void
422  {
423  softStep->cpsrD = mask;
424  }
425 
426  inline bool
427  isAArch32() const
428  {
429  return aarch32;
430  }
431 
432  inline void
434  {
435  ExceptionLevel from_el = (ExceptionLevel) currEL(tc);
436  if (from_el == EL0)
437  aarch32 = ELIs32(tc, EL0) && ELIs32(tc, EL1);
438  else
439  aarch32 = ELIs32(tc, from_el);
440  return;
441  }
442 
443  SoftwareStep *
445  {
446  return softStep;
447  }
448 
449  VectorCatch*
451  {
452  if (!initialized)
453  init(tc);
454  return vcExcpt;
455  }
456 
457  bool
459  {
460  ExceptionLevel ELd = debugTargetFrom(tc, isSecure(tc));
461  return ELIs32(tc, ELd) && aarch32;
462  }
463 
464  void init(ThreadContext *tc);
465 };
466 
467 } // namespace ArmISA
468 } // namespace gem5
469 
470 #endif
gem5::ArmISA::SelfDebug::testWatchPoints
Fault testWatchPoints(ThreadContext *tc, Addr vaddr, bool write, bool atomic, unsigned size, bool cm)
Definition: self_debug.cc:125
gem5::ArmISA::WatchPoint::updateControl
void updateControl(DBGWCR val)
Definition: self_debug.hh:184
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
gem5::ArmISA::pmc
Bitfield< 2, 1 > pmc
Definition: misc_types.hh:711
gem5::ArmISA::SelfDebug::setenableTDETGE
void setenableTDETGE(HCR hcr, HDCR mdcr)
Definition: self_debug.hh:397
gem5::ArmISA::SelfDebug::init
void init(ThreadContext *tc)
Definition: self_debug.cc:327
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::ArmISA::WatchPoint::isDoubleAligned
bool isDoubleAligned(Addr addr)
Definition: self_debug.hh:178
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::ArmISA::BrkPoint::test
bool test(ThreadContext *tc, Addr pc, ExceptionLevel el, DBGBCR ctr, bool from_link)
Definition: self_debug.cc:218
gem5::ArmISA::SelfDebug
Definition: self_debug.hh:277
gem5::ArmISA::cm
Bitfield< 13 > cm
Definition: misc_types.hh:428
gem5::ArmISA::SoftwareStep::ACTIVE_PENDING_STATE
static const uint8_t ACTIVE_PENDING_STATE
Definition: self_debug.hh:199
gem5::ArmISA::el
Bitfield< 3, 2 > el
Definition: misc_types.hh:72
gem5::ArmISA::BrkPoint::BrkPoint
BrkPoint(MiscRegIndex ctrl_index, MiscRegIndex val_index, SelfDebug *_conf, bool ctx_aw, bool lva, bool vmid16, bool aarch32)
Definition: self_debug.hh:77
gem5::ArmISA::WatchPoint::valRegIndex
MiscRegIndex valRegIndex
Definition: self_debug.hh:151
gem5::ArmISA::BrkPoint::getContextfromReg
RegVal getContextfromReg(ThreadContext *tc, bool ctxid1) const
Definition: self_debug.hh:101
gem5::ArmISA::BrkPoint::testVMIDMatch
bool testVMIDMatch(ThreadContext *tc)
Definition: self_debug.cc:451
gem5::ArmISA::WatchPoint::ctrlRegIndex
MiscRegIndex ctrlRegIndex
Definition: self_debug.hh:150
gem5::ArmISA::SoftwareStep::cpsrD
bool cpsrD
Definition: self_debug.hh:207
gem5::ArmISA::WatchPoint::enable
bool enable
Definition: self_debug.hh:153
gem5::ArmISA::SelfDebug::to32
bool to32
Definition: self_debug.hh:294
gem5::MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:47
gem5::ArmISA::SelfDebug::initialized
bool initialized
Definition: self_debug.hh:285
gem5::ArmISA::SelfDebug::arBrkPoints
std::vector< BrkPoint > arBrkPoints
Definition: self_debug.hh:280
gem5::ArmISA::SoftwareStep::clearLdx
void clearLdx()
Definition: self_debug.hh:229
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:53
gem5::ArmISA::BrkPoint::testAddrMissMatch
bool testAddrMissMatch(ThreadContext *tc, Addr pc, uint8_t bas)
Definition: self_debug.cc:401
gem5::ArmISA::SelfDebug::isDebugEnabledForEL64
bool isDebugEnabledForEL64(ThreadContext *tc, ExceptionLevel el, bool secure, bool mask)
Definition: self_debug.cc:165
gem5::ArmISA::BrkPoint::ctrlRegIndex
MiscRegIndex ctrlRegIndex
Definition: self_debug.hh:64
gem5::ArmISA::SoftwareStep::bSS
bool bSS
Definition: self_debug.hh:202
gem5::ArmISA::SelfDebug::vcExcpt
VectorCatch * vcExcpt
Definition: self_debug.hh:283
gem5::ArmISA::vmid_t
uint16_t vmid_t
Definition: types.hh:57
tlb.hh
gem5::ArmISA::currEL
static ExceptionLevel currEL(const ThreadContext *tc)
Definition: utility.hh:119
gem5::ArmISA::SelfDebug::updateOSLock
void updateOSLock(RegVal val)
Definition: self_debug.hh:403
gem5::ArmISA::VectorCatch::conf
SelfDebug * conf
Definition: self_debug.hh:246
gem5::ArmISA::SelfDebug::targetAArch32
bool targetAArch32(ThreadContext *tc)
Definition: self_debug.hh:458
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::ArmISA::SelfDebug::activateDebug
void activateDebug()
Definition: self_debug.hh:355
gem5::ArmISA::bas
Bitfield< 8, 5 > bas
Definition: misc_types.hh:709
gem5::ArmISA::EL1
@ EL1
Definition: types.hh:267
gem5::ArmISA::SoftwareStep::setLdx
void setLdx()
Definition: self_debug.hh:222
gem5::ArmISA::SoftwareStep::debugExceptionReturnSS
bool debugExceptionReturnSS(ThreadContext *tc, CPSR spsr, ExceptionLevel dest)
Definition: self_debug.cc:645
gem5::ArmISA::SelfDebug::aarch32
bool aarch32
Definition: self_debug.hh:293
std::vector
STL vector class.
Definition: stl.hh:37
gem5::ArmISA::SelfDebug::sdd
bool sdd
Definition: self_debug.hh:289
gem5::ArmISA::SelfDebug::~SelfDebug
~SelfDebug()
Definition: self_debug.hh:304
gem5::ArmISA::SoftwareStep::advanceSS
bool advanceSS(ThreadContext *tc)
Definition: self_debug.cc:677
gem5::ArmISA::SelfDebug::getSstep
SoftwareStep * getSstep()
Definition: self_debug.hh:444
gem5::ArmISA::SelfDebug::testBreakPoints
Fault testBreakPoints(ThreadContext *tc, Addr vaddr)
Definition: self_debug.cc:76
gem5::ArmISA::SelfDebug::isDebugEnabledForEL32
bool isDebugEnabledForEL32(ThreadContext *tc, ExceptionLevel el, bool secure, bool mask)
Definition: self_debug.cc:184
system.hh
gem5::ArmISA::BrkPoint::testAddrMatch
bool testAddrMatch(ThreadContext *tc, Addr pc, uint8_t bas)
Definition: self_debug.cc:382
types.hh
gem5::ArmISA::SoftwareStep::prevSteppedLdx
bool prevSteppedLdx
Definition: self_debug.hh:206
gem5::ArmISA::SelfDebug::updateDBGBCR
void updateDBGBCR(int index, DBGBCR val)
Definition: self_debug.hh:409
gem5::ArmISA::SoftwareStep::getLdx
bool getLdx() const
Definition: self_debug.hh:236
gem5::ArmISA::SelfDebug::isAArch32
bool isAArch32() const
Definition: self_debug.hh:427
gem5::ArmISA::BrkPoint::valRegIndex
MiscRegIndex valRegIndex
Definition: self_debug.hh:65
gem5::ArmISA::SelfDebug::mde
bool mde
Definition: self_debug.hh:288
gem5::ArmISA::SelfDebug::testDebug
Fault testDebug(ThreadContext *tc, const RequestPtr &req, BaseMMU::Mode mode)
Definition: self_debug.cc:51
gem5::ArmISA::BrkPoint::isActive
bool isActive(Addr vaddr)
Definition: self_debug.hh:129
gem5::ArmISA::WatchPoint
Definition: self_debug.hh:147
gem5::ArmISA::atomic
Bitfield< 23, 20 > atomic
Definition: misc_types.hh:99
gem5::ArmISA::SelfDebug::setbSDD
void setbSDD(RegVal val)
Definition: self_debug.hh:377
gem5::ArmISA::BrkPoint::testContextMatch
bool testContextMatch(ThreadContext *tc, bool ctx1, bool low_ctx)
Definition: self_debug.cc:427
gem5::ArmISA::BrkPoint::getAddrfromReg
Addr getAddrfromReg(ThreadContext *tc) const
Definition: self_debug.hh:95
gem5::ArmISA::SelfDebug::setMDBGen
void setMDBGen(RegVal val)
Definition: self_debug.hh:391
gem5::ArmISA::BrkPoint::isCntxtAware
bool isCntxtAware
Definition: self_debug.hh:67
gem5::ArmISA::SelfDebug::triggerException
Fault triggerException(ThreadContext *tc, Addr vaddr)
Definition: self_debug.cc:112
gem5::ArmISA::b
Bitfield< 7 > b
Definition: misc_types.hh:381
gem5::ArmISA::VectorCatch::vcmatch
bool vcmatch
Definition: self_debug.hh:245
gem5::ArmISA::SelfDebug::setMDSCRvals
void setMDSCRvals(RegVal val)
Definition: self_debug.hh:383
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::ArmISA::WatchPoint::getAddrfromReg
Addr getAddrfromReg(ThreadContext *tc)
Definition: self_debug.hh:172
gem5::ArmISA::MISCREG_SCTLR_EL1
@ MISCREG_SCTLR_EL1
Definition: misc.hh:579
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::ArmISA::SoftwareStep::INACTIVE_STATE
static const uint8_t INACTIVE_STATE
Definition: self_debug.hh:198
gem5::ArmISA::BrkPoint::getControlReg
const DBGBCR getControlReg(ThreadContext *tc)
Definition: self_debug.hh:120
gem5::ArmISA::BrkPoint::testLinkedBk
bool testLinkedBk(ThreadContext *tc, Addr vaddr, ExceptionLevel el)
Definition: self_debug.cc:211
gem5::ArmISA::MISCREG_MVBAR
@ MISCREG_MVBAR
Definition: misc.hh:394
gem5::ArmISA::WatchPoint::test
bool test(ThreadContext *tc, Addr addr, ExceptionLevel el, bool &wrt, bool atomic, unsigned size)
Definition: self_debug.cc:581
gem5::ArmISA::VectorCatch::exceptionTrapping
bool exceptionTrapping(ThreadContext *tc, ExceptionLevel el, ArmFault *fault)
Definition: self_debug.cc:806
gem5::ArmISA::hmc
Bitfield< 13 > hmc
Definition: misc_types.hh:707
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::ArmISA::ELIs32
bool ELIs32(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:288
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::ArmISA::s
Bitfield< 4 > s
Definition: misc_types.hh:561
gem5::ArmISA::SoftwareStep
Definition: self_debug.hh:195
gem5::ArmISA::SoftwareStep::ACTIVE_NOT_PENDING_STATE
static const uint8_t ACTIVE_NOT_PENDING_STATE
Definition: self_debug.hh:200
gem5::ArmISA::SelfDebug::securityStateMatch
static bool securityStateMatch(ThreadContext *tc, uint8_t ssc, bool hmc)
Definition: self_debug.hh:333
gem5::ArmISA::BrkPoint::activePc
Addr activePc
Definition: self_debug.hh:69
gem5::ArmISA::mask
Bitfield< 3, 0 > mask
Definition: pcstate.hh:63
gem5::ArmISA::SelfDebug::softStep
SoftwareStep * softStep
Definition: self_debug.hh:282
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::ArmISA::BrkPoint::VMID16enabled
bool VMID16enabled
Definition: self_debug.hh:68
gem5::ArmISA::SoftwareStep::stateSS
int stateSS
Definition: self_debug.hh:203
gem5::ArmISA::SoftwareStep::conf
SelfDebug * conf
Definition: self_debug.hh:204
faults.hh
gem5::ArmISA::WatchPoint::isEnabled
bool isEnabled(ThreadContext *tc, ExceptionLevel el, bool hmc, uint8_t ssc, uint8_t pac)
Definition: self_debug.cc:535
gem5::ArmISA::debugTargetFrom
ExceptionLevel debugTargetFrom(ThreadContext *tc, bool secure)
Definition: utility.cc:91
gem5::ArmISA::WatchPoint::WatchPoint
WatchPoint(MiscRegIndex ctrl_index, MiscRegIndex val_index, SelfDebug *_conf, bool lva, bool aarch32)
Definition: self_debug.hh:159
gem5::ArmISA::SoftwareStep::steppedLdx
bool steppedLdx
Definition: self_debug.hh:205
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:59
gem5::ArmISA::isSecure
bool isSecure(ThreadContext *tc)
Definition: utility.cc:72
gem5::ArmISA::WatchPoint::conf
SelfDebug * conf
Definition: self_debug.hh:152
utility.hh
gem5::ArmISA::SelfDebug::enableTdeTge
bool enableTdeTge
Definition: self_debug.hh:286
gem5::ArmISA::pac
Bitfield< 2, 1 > pac
Definition: misc_types.hh:725
gem5::ArmISA::ArmFault
Definition: faults.hh:64
gem5::ArmISA::BrkPoint::enable
bool enable
Definition: self_debug.hh:70
gem5::ArmISA::BrkPoint
Definition: self_debug.hh:61
gem5::ArmISA::BrkPoint::getVMIDfromReg
vmid_t getVMIDfromReg(ThreadContext *tc, bool vs)
Definition: self_debug.cc:525
gem5::ArmISA::SelfDebug::getVectorCatch
VectorCatch * getVectorCatch(ThreadContext *tc)
Definition: self_debug.hh:450
gem5::ArmISA::EL0
@ EL0
Definition: types.hh:266
gem5::ArmISA::WatchPoint::maxAddrSize
int maxAddrSize
Definition: self_debug.hh:154
gem5::ArmISA::SelfDebug::isDebugEnabled
bool isDebugEnabled(ThreadContext *tc)
Definition: self_debug.hh:363
gem5::ArmISA::VectorCatch::isVCMatch
bool isVCMatch() const
Definition: self_debug.hh:257
gem5::ArmISA::VectorCatch
Definition: self_debug.hh:242
gem5::ArmISA::SelfDebug::testVectorCatch
Fault testVectorCatch(ThreadContext *tc, Addr addr, ArmFault *flt)
Definition: self_debug.cc:715
gem5::ArmISA::SelfDebug::getBrkPoint
BrkPoint * getBrkPoint(uint8_t index)
Definition: self_debug.hh:327
gem5::ArmISA::VectorCatch::vectorTypes
std::vector< Fault * > vectorTypes()
misc.hh
gem5::ArmISA::SelfDebug::arWatchPoints
std::vector< WatchPoint > arWatchPoints
Definition: self_debug.hh:281
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::SelfDebug::SelfDebug
SelfDebug()
Definition: self_debug.hh:297
gem5::ArmISA::vs
Bitfield< 19 > vs
Definition: misc_types.hh:569
gem5::ArmISA::BrkPoint::onUse
bool onUse
Definition: self_debug.hh:72
gem5::ArmISA::SelfDebug::oslk
bool oslk
Definition: self_debug.hh:291
gem5::ArmISA::MISCREG_VBAR
@ MISCREG_VBAR
Definition: misc.hh:391
gem5::ArmISA::SelfDebug::kde
bool kde
Definition: self_debug.hh:290
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::ArmISA::SelfDebug::enabled
bool enabled() const
Definition: self_debug.hh:324
gem5::ArmISA::ssc
Bitfield< 15, 14 > ssc
Definition: misc_types.hh:706
gem5::ArmISA::SelfDebug::updateDBGWCR
void updateDBGWCR(int index, DBGWCR val)
Definition: self_debug.hh:415
gem5::ArmISA::BrkPoint::conf
SelfDebug * conf
Definition: self_debug.hh:66
gem5::ArmISA::BrkPoint::updateControl
void updateControl(DBGBCR val)
Definition: self_debug.hh:141
gem5::ArmISA::BrkPoint::isEnabled
bool isEnabled(ThreadContext *tc, ExceptionLevel el, uint8_t hmc, uint8_t ssc, uint8_t pmc)
Definition: self_debug.cc:470
gem5::ArmISA::VectorCatch::VectorCatch
VectorCatch(bool _vcmatch, SelfDebug *s)
Definition: self_debug.hh:250
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::SelfDebug::setDebugMask
void setDebugMask(bool mask)
Definition: self_debug.hh:421
gem5::ArmISA::BrkPoint::maxAddrSize
int maxAddrSize
Definition: self_debug.hh:71
gem5::ArmISA::SelfDebug::triggerWatchpointException
Fault triggerWatchpointException(ThreadContext *tc, Addr vaddr, bool write, bool cm)
Definition: self_debug.cc:149
gem5::ArmISA::VectorCatch::addressMatching
bool addressMatching(ThreadContext *tc, Addr addr, ExceptionLevel el)
Definition: self_debug.cc:748
thread_context.hh
gem5::ArmISA::WatchPoint::compareAddress
bool compareAddress(ThreadContext *tc, Addr in_addr, uint8_t bas, uint8_t mask, unsigned size)
Definition: self_debug.cc:601
gem5::ArmISA::SelfDebug::setAArch32
void setAArch32(ThreadContext *tc)
Definition: self_debug.hh:433
gem5::ArmISA::VectorCatch::getVectorBase
Addr getVectorBase(ThreadContext *tc, bool monitor)
Definition: self_debug.hh:261
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:264
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:73
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::ArmISA::SoftwareStep::SoftwareStep
SoftwareStep(SelfDebug *s)
Definition: self_debug.hh:212

Generated on Tue Sep 21 2021 12:24:46 for gem5 by doxygen 1.8.17