gem5  v21.1.0.2
fetch.hh
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40 
41 #ifndef __CPU_O3_FETCH_HH__
42 #define __CPU_O3_FETCH_HH__
43 
44 #include "arch/decoder.hh"
45 #include "arch/generic/mmu.hh"
46 #include "base/statistics.hh"
47 #include "config/the_isa.hh"
48 #include "cpu/o3/comm.hh"
49 #include "cpu/o3/dyn_inst_ptr.hh"
50 #include "cpu/o3/limits.hh"
51 #include "cpu/pc_event.hh"
52 #include "cpu/pred/bpred_unit.hh"
53 #include "cpu/timebuf.hh"
54 #include "cpu/translation.hh"
55 #include "enums/SMTFetchPolicy.hh"
56 #include "mem/packet.hh"
57 #include "mem/port.hh"
58 #include "sim/eventq.hh"
59 #include "sim/probe/probe.hh"
60 
61 namespace gem5
62 {
63 
64 struct O3CPUParams;
65 
66 namespace o3
67 {
68 
69 class CPU;
70 
79 class Fetch
80 {
81  public:
85  class IcachePort : public RequestPort
86  {
87  protected:
90 
91  public:
93  IcachePort(Fetch *_fetch, CPU *_cpu);
94 
95  protected:
96 
99  virtual bool recvTimingResp(PacketPtr pkt);
100 
102  virtual void recvReqRetry();
103  };
104 
106  {
107  protected:
109 
110  public:
111  FetchTranslation(Fetch *_fetch) : fetch(_fetch) {}
112 
113  void markDelayed() {}
114 
115  void
116  finish(const Fault &fault, const RequestPtr &req,
118  {
119  assert(mode == BaseMMU::Execute);
120  fetch->finishTranslation(fault, req);
121  delete this;
122  }
123  };
124 
125  private:
126  /* Event to delay delivery of a fetch translation result in case of
127  * a fault and the nop to carry the fault cannot be generated
128  * immediately */
130  {
131  private:
135 
136  public:
138  : fetch(_fetch), req(nullptr)
139  {}
140 
141  void setFault(Fault _fault) { fault = _fault; }
142  void setReq(const RequestPtr &_req) { req = _req; }
143 
145  void
147  {
148  assert(fetch->numInst < fetch->fetchWidth);
150  }
151 
152  const char *
153  description() const
154  {
155  return "CPU FetchFinishTranslation";
156  }
157  };
158 
159  public:
164  {
167  };
168 
171  {
184  };
185 
186  private:
189 
192 
194  SMTFetchPolicy fetchPolicy;
195 
198 
203 
204  public:
206  Fetch(CPU *_cpu, const O3CPUParams &params);
207 
209  std::string name() const;
210 
211 
213  void regProbePoints();
214 
216  void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
217 
220 
223 
225  void startupStage();
226 
228  void clearStates(ThreadID tid);
229 
231  void recvReqRetry();
232 
235 
237  void drainResume();
238 
240  void drainSanityCheck() const;
241 
243  bool isDrained() const;
244 
246  void takeOverFrom();
247 
257  void drainStall(ThreadID tid);
258 
260  void wakeFromQuiesce();
261 
263  void deactivateThread(ThreadID tid);
264  private:
266  void resetStage();
267 
271  void switchToActive();
272 
276  void switchToInactive();
277 
288 
300  bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc);
301  void finishTranslation(const Fault &fault, const RequestPtr &mem_req);
302 
303 
307 
309  void doSquash(const TheISA::PCState &newPC,
310  const DynInstPtr squashInst, ThreadID tid);
311 
316  void squashFromDecode(const TheISA::PCState &newPC,
317  const DynInstPtr squashInst,
318  const InstSeqNum seq_num, ThreadID tid);
319 
321  bool checkStall(ThreadID tid) const;
322 
326 
327  public:
332  void squash(const TheISA::PCState &newPC, const InstSeqNum seq_num,
333  DynInstPtr squashInst, ThreadID tid);
334 
338  void tick();
339 
344 
350  void fetch(bool &status_change);
351 
354  {
355  return (addr & ~(fetchBufferMask));
356  }
357 
359  TheISA::Decoder *decoder[MaxThreads];
360 
362 
363  private:
364  DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst,
365  StaticInstPtr curMacroop, TheISA::PCState thisPC,
366  TheISA::PCState nextPC, bool trace);
367 
370 
373 
375  ThreadID iqCount();
376 
378  ThreadID lsqCount();
379 
383 
386 
388  void profileStall(ThreadID tid);
389 
390  private:
393 
396 
399 
402 
405 
408 
409  //Might be annoying how this name is different than the queue.
412 
415 
417 
419 
421 
424 
427 
432 
434  int numInst;
435 
437  struct Stalls
438  {
439  bool decode;
440  bool drain;
441  };
442 
445 
448 
451 
454 
457 
459  unsigned fetchWidth;
460 
462  unsigned decodeWidth;
463 
466 
469 
472 
474  unsigned int cacheBlkSize;
475 
479  unsigned fetchBufferSize;
480 
483 
486 
489 
491  unsigned fetchQueueSize;
492 
495 
498 
500  int instSize;
501 
504 
507 
510 
513 
516 
521 
524 
527 
530 
531  protected:
533  {
535  // @todo: Consider making these
536  // vectors and tracking on a per thread basis.
589  } fetchStats;
590 };
591 
592 } // namespace o3
593 } // namespace gem5
594 
595 #endif //__CPU_O3_FETCH_HH__
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1927
gem5::o3::Fetch::FetchStatGroup::pendingQuiesceStallCycles
statistics::Scalar pendingQuiesceStallCycles
Total number of stall cycles caused by pending quiesce instructions.
Definition: fetch.hh:568
gem5::o3::Fetch::FetchStatus
FetchStatus
Overall fetch status.
Definition: fetch.hh:163
gem5::o3::Fetch::numFetchingThreads
ThreadID numFetchingThreads
Number of threads that are actively fetching.
Definition: fetch.hh:512
gem5::o3::Fetch::_status
FetchStatus _status
Fetch status.
Definition: fetch.hh:188
gem5::o3::Fetch::fetchCacheLine
bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc)
Fetches the cache line that contains the fetch PC.
Definition: fetch.cc:555
gem5::o3::Fetch::switchToInactive
void switchToInactive()
Changes the status of this stage to inactive, and indicates this to the CPU.
Definition: fetch.cc:489
gem5::o3::Fetch::FetchStatGroup::insts
statistics::Scalar insts
Stat for total number of fetched instructions.
Definition: fetch.hh:540
gem5::o3::Fetch::FetchStatGroup::blockedCycles
statistics::Scalar blockedCycles
Total number of cycles spent blocked.
Definition: fetch.hh:557
gem5::statistics::Distribution
A simple distribution stat.
Definition: statistics.hh:2081
gem5::o3::Fetch::fetchBuffer
uint8_t * fetchBuffer[MaxThreads]
The fetch data that is being fetched and buffered.
Definition: fetch.hh:485
gem5::o3::Fetch::FetchStatGroup::pendingDrainCycles
statistics::Scalar pendingDrainCycles
Total number of cycles spent in waiting for drains.
Definition: fetch.hh:561
gem5::o3::Fetch::FetchStatGroup::miscStallCycles
statistics::Scalar miscStallCycles
Total number of cycles spent in any other state.
Definition: fetch.hh:559
gem5::o3::Fetch::profileStall
void profileStall(ThreadID tid)
Profile the reasons of fetch stall.
Definition: fetch.cc:1560
gem5::o3::Fetch::getInstPort
RequestPort & getInstPort()
Definition: fetch.hh:361
gem5::o3::Fetch::lookupAndUpdateNextPC
bool lookupAndUpdateNextPC(const DynInstPtr &inst, TheISA::PCState &pc)
Looks up in the branch predictor to see if the next PC should be either next PC+=MachInst or a branch...
Definition: fetch.cc:511
gem5::o3::Fetch::pipelineIcacheAccesses
void pipelineIcacheAccesses(ThreadID tid)
Pipeline the next I-cache access to the current one.
Definition: fetch.cc:1531
gem5::o3::Fetch::IcachePort::recvReqRetry
virtual void recvReqRetry()
Handles doing a retry of a failed fetch.
Definition: fetch.cc:1621
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:53
gem5::o3::Fetch::branchPred
branch_prediction::BPredUnit * branchPred
BPredUnit.
Definition: fetch.hh:414
gem5::o3::Fetch::drainStall
void drainStall(ThreadID tid)
Stall the fetch stage after reaching a safe drain point.
Definition: fetch.cc:459
gem5::o3::Fetch::checkInterrupt
bool checkInterrupt(Addr pc)
Check if an interrupt is pending and that we need to handle.
Definition: fetch.hh:306
gem5::o3::Fetch::retryPkt
PacketPtr retryPkt
The packet that is waiting to be retried.
Definition: fetch.hh:468
gem5::o3::Fetch::iewToFetchDelay
Cycles iewToFetchDelay
IEW to fetch delay.
Definition: fetch.hh:453
gem5::o3::Fetch::wakeFromQuiesce
void wakeFromQuiesce()
Tells fetch to wake up from a quiesce instruction.
Definition: fetch.cc:468
gem5::o3::Fetch::name
std::string name() const
Returns the name of fetch.
Definition: fetch.cc:150
gem5::o3::Fetch::processCacheCompletion
void processCacheCompletion(PacketPtr pkt)
Processes cache completion event.
Definition: fetch.cc:352
gem5::o3::Fetch::setActiveThreads
void setActiveThreads(std::list< ThreadID > *at_ptr)
Sets pointer to list of active threads.
Definition: fetch.cc:275
gem5::o3::Fetch::squashFromDecode
void squashFromDecode(const TheISA::PCState &newPC, const DynInstPtr squashInst, const InstSeqNum seq_num, ThreadID tid)
Squashes a specific thread and resets the PC.
Definition: fetch.cc:762
gem5::o3::Fetch::FetchTranslation::FetchTranslation
FetchTranslation(Fetch *_fetch)
Definition: fetch.hh:111
gem5::o3::Fetch::FetchStatGroup::nisnDist
statistics::Distribution nisnDist
Distribution of number of instructions fetched each cycle.
Definition: fetch.hh:582
gem5::o3::Fetch::Fetch
Fetch(CPU *_cpu, const O3CPUParams &params)
Fetch constructor.
Definition: fetch.cc:84
gem5::o3::Fetch::delayedCommit
bool delayedCommit[MaxThreads]
Can the fetch stage redirect from an interrupt on this instruction?
Definition: fetch.hh:423
gem5::o3::Fetch::FetchStatGroup::cacheLines
statistics::Scalar cacheLines
Stat for total number of fetched cache lines.
Definition: fetch.hh:572
gem5::o3::Fetch::Idle
@ Idle
Definition: fetch.hh:173
gem5::statistics::Formula
A formula for statistics that is calculated when printed.
Definition: statistics.hh:2536
gem5::o3::Fetch::FetchTranslation
Definition: fetch.hh:105
gem5::o3::Fetch::Stalls
Source of possible stalls.
Definition: fetch.hh:437
gem5::o3::Fetch::fetchWidth
unsigned fetchWidth
The width of fetch in instructions.
Definition: fetch.hh:459
gem5::o3::Fetch::clearStates
void clearStates(ThreadID tid)
Clear all thread-specific states.
Definition: fetch.cc:299
gem5::o3::Fetch
Fetch class handles both single threaded and SMT fetch.
Definition: fetch.hh:79
gem5::o3::Fetch::numInst
int numInst
Tracks how many instructions has been fetched this cycle.
Definition: fetch.hh:434
gem5::o3::Fetch::retryTid
ThreadID retryTid
The thread that is waiting on the cache to tell fetch to retry.
Definition: fetch.hh:471
gem5::o3::Fetch::isDrained
bool isDrained() const
Has the stage drained?
Definition: fetch.cc:421
gem5::o3::Fetch::macroop
StaticInstPtr macroop[MaxThreads]
Definition: fetch.hh:420
gem5::o3::Fetch::getFetchingThread
ThreadID getFetchingThread()
Returns the appropriate thread to fetch, given the fetch policy.
Definition: fetch.cc:1389
gem5::o3::Fetch::FinishTranslationEvent::description
const char * description() const
Return a C string describing the event.
Definition: fetch.hh:153
gem5::o3::Fetch::FinishTranslationEvent::req
RequestPtr req
Definition: fetch.hh:134
gem5::o3::Fetch::fetchStats
gem5::o3::Fetch::FetchStatGroup fetchStats
gem5::o3::Fetch::Blocked
@ Blocked
Definition: fetch.hh:175
gem5::o3::Fetch::Active
@ Active
Definition: fetch.hh:165
gem5::o3::Fetch::FetchStatGroup::idleCycles
statistics::Scalar idleCycles
Stat for total number of cycles spent blocked due to other stages in the pipeline.
Definition: fetch.hh:555
gem5::BaseMMU::Execute
@ Execute
Definition: mmu.hh:53
gem5::o3::Fetch::Squashing
@ Squashing
Definition: fetch.hh:174
gem5::o3::Fetch::IcacheWaitRetry
@ IcacheWaitRetry
Definition: fetch.hh:181
gem5::o3::Fetch::FetchStatGroup::pendingTrapStallCycles
statistics::Scalar pendingTrapStallCycles
Total number of stall cycles caused by pending traps.
Definition: fetch.hh:565
gem5::RefCountingPtr< DynInst >
gem5::o3::Fetch::ppFetchRequestSent
ProbePointArg< RequestPtr > * ppFetchRequestSent
To probe when a fetch request is successfully sent.
Definition: fetch.hh:202
gem5::TimeBuffer
Definition: timebuf.hh:40
packet.hh
gem5::o3::Fetch::Fetching
@ Fetching
Definition: fetch.hh:176
gem5::RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:77
gem5::o3::Fetch::FinishTranslationEvent::setFault
void setFault(Fault _fault)
Definition: fetch.hh:141
gem5::o3::Fetch::FetchStatGroup::tlbCycles
statistics::Scalar tlbCycles
Stat for total number of cycles spent waiting for translation.
Definition: fetch.hh:550
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::o3::Fetch::FetchStatGroup::icacheStallCycles
statistics::Scalar icacheStallCycles
Stat for total number of cycles stalled due to an icache miss.
Definition: fetch.hh:538
gem5::o3::Fetch::IcachePort::fetch
Fetch * fetch
Pointer to fetch.
Definition: fetch.hh:89
gem5::o3::Fetch::QuiescePending
@ QuiescePending
Definition: fetch.hh:178
gem5::o3::Fetch::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: fetch.cc:404
timebuf.hh
gem5::o3::Fetch::lastIcacheStall
Counter lastIcacheStall[MaxThreads]
Icache stall statistics.
Definition: fetch.hh:503
gem5::o3::Fetch::drainResume
void drainResume()
Resume after a drain.
Definition: fetch.cc:395
comm.hh
gem5::o3::Fetch::fromDecode
TimeBuffer< TimeStruct >::wire fromDecode
Wire to get decode's information from backwards time buffer.
Definition: fetch.hh:398
gem5::o3::Fetch::fetchBufferSize
unsigned fetchBufferSize
The size of the fetch buffer in bytes.
Definition: fetch.hh:479
gem5::o3::Fetch::FetchStatGroup::tlbSquashes
statistics::Scalar tlbSquashes
Total number of outstanding tlb accesses that were dropped due to a squash.
Definition: fetch.hh:580
gem5::o3::Fetch::pc
TheISA::PCState pc[MaxThreads]
Definition: fetch.hh:416
gem5::o3::Fetch::priorityList
std::list< ThreadID > priorityList
List that has the threads organized by priority.
Definition: fetch.hh:197
gem5::o3::Fetch::fromIEW
TimeBuffer< TimeStruct >::wire fromIEW
Wire to get iew's information from backwards time buffer.
Definition: fetch.hh:404
gem5::o3::Fetch::IcacheAccessComplete
@ IcacheAccessComplete
Definition: fetch.hh:182
gem5::o3::Fetch::commitToFetchDelay
Cycles commitToFetchDelay
Commit to fetch delay.
Definition: fetch.hh:456
gem5::o3::CPU
O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buff...
Definition: cpu.hh:95
gem5::o3::Fetch::fetch
void fetch(bool &status_change)
Does the actual fetching of instructions and passing them on to the next stage.
Definition: fetch.cc:1097
translation.hh
gem5::o3::Fetch::FetchStatGroup::branches
statistics::Scalar branches
Total number of fetched branches.
Definition: fetch.hh:542
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::o3::Fetch::checkStall
bool checkStall(ThreadID tid) const
Checks if a thread is stalled.
Definition: fetch.cc:775
gem5::o3::Fetch::finishTranslationEvent
FinishTranslationEvent finishTranslationEvent
Event used to delay fault generation of translation faults.
Definition: fetch.hh:529
gem5::o3::Fetch::stalls
Stalls stalls[MaxThreads]
Tracks which stages are telling fetch to stall.
Definition: fetch.hh:444
gem5::o3::Fetch::wroteToTimeBuffer
bool wroteToTimeBuffer
Variable that tracks if fetch has written to the time buffer this cycle.
Definition: fetch.hh:431
gem5::o3::Fetch::recvReqRetry
void recvReqRetry()
Handles retrying the fetch access.
Definition: fetch.cc:1359
gem5::o3::Fetch::roundRobin
ThreadID roundRobin()
Returns the appropriate thread to fetch using a round robin policy.
Definition: fetch.cc:1424
gem5::Event
Definition: eventq.hh:251
gem5::o3::Fetch::fetchBufferAlignPC
Addr fetchBufferAlignPC(Addr addr)
Align a PC to the start of a fetch buffer block.
Definition: fetch.hh:353
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::o3::Fetch::lsqCount
ThreadID lsqCount()
Returns the appropriate thread to fetch using the LSQ count policy.
Definition: fetch.cc:1489
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
statistics.hh
gem5::o3::Fetch::setTimeBuffer
void setTimeBuffer(TimeBuffer< TimeStruct > *time_buffer)
Sets the main backwards communication time buffer pointer.
Definition: fetch.cc:263
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::o3::Fetch::FinishTranslationEvent::setReq
void setReq(const RequestPtr &_req)
Definition: fetch.hh:142
mmu.hh
gem5::o3::Fetch::fetchBufferValid
bool fetchBufferValid[MaxThreads]
Whether or not the fetch buffer data is valid.
Definition: fetch.hh:497
gem5::o3::Fetch::threadFetched
ThreadID threadFetched
Thread ID being fetched.
Definition: fetch.hh:515
port.hh
gem5::o3::Fetch::deactivateThread
void deactivateThread(ThreadID tid)
For priority-based fetch policies, need to keep update priorityList.
Definition: fetch.cc:501
gem5::o3::Fetch::ItlbWait
@ ItlbWait
Definition: fetch.hh:179
gem5::o3::Fetch::FinishTranslationEvent::process
void process()
Process the delayed finish translation.
Definition: fetch.hh:146
gem5::o3::Fetch::cpu
CPU * cpu
Pointer to the O3CPU.
Definition: fetch.hh:392
gem5::o3::Fetch::FetchStatGroup::cycles
statistics::Scalar cycles
Stat for total number of cycles spent fetching.
Definition: fetch.hh:546
gem5::o3::Fetch::FetchStatGroup::squashCycles
statistics::Scalar squashCycles
Stat for total number of cycles spent squashing.
Definition: fetch.hh:548
gem5::o3::Fetch::switchToActive
void switchToActive()
Changes the status of this stage to active, and indicates this to the CPU.
Definition: fetch.cc:477
gem5::o3::Fetch::Running
@ Running
Definition: fetch.hh:172
gem5::o3::Fetch::FetchStatGroup::rate
statistics::Formula rate
Number of instruction fetched per cycle.
Definition: fetch.hh:588
gem5::o3::Fetch::instSize
int instSize
Size of instructions.
Definition: fetch.hh:500
gem5::o3::Fetch::timeBuffer
TimeBuffer< TimeStruct > * timeBuffer
Time buffer interface.
Definition: fetch.hh:395
gem5::o3::Fetch::fetchQueue
std::deque< DynInstPtr > fetchQueue[MaxThreads]
Queue of fetched instructions.
Definition: fetch.hh:494
gem5::o3::Fetch::tick
void tick()
Ticks the fetch stage, processing all inputs signals and fetching as many instructions as possible.
Definition: fetch.cc:840
gem5::o3::Fetch::interruptPending
bool interruptPending
Checks if there is an interrupt pending.
Definition: fetch.hh:520
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::o3::Fetch::FetchStatGroup::icacheSquashes
statistics::Scalar icacheSquashes
Total number of outstanding icache accesses that were dropped due to a squash.
Definition: fetch.hh:576
dyn_inst_ptr.hh
gem5::o3::Fetch::FetchStatGroup::branchRate
statistics::Formula branchRate
Number of branch fetches per cycle.
Definition: fetch.hh:586
gem5::o3::Fetch::resetStage
void resetStage()
Reset this pipeline stage.
Definition: fetch.cc:318
gem5::o3::Fetch::updateFetchStatus
FetchStatus updateFetchStatus()
Updates overall fetch stage status; to be called at the end of each cycle.
Definition: fetch.cc:789
gem5::o3::Fetch::cacheBlocked
bool cacheBlocked
Is the cache blocked? If so no threads can access it.
Definition: fetch.hh:465
gem5::o3::Fetch::buildInst
DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst, StaticInstPtr curMacroop, TheISA::PCState thisPC, TheISA::PCState nextPC, bool trace)
Definition: fetch.cc:1046
gem5::o3::Fetch::squash
void squash(const TheISA::PCState &newPC, const InstSeqNum seq_num, DynInstPtr squashInst, ThreadID tid)
Squashes a specific thread and resets the PC.
Definition: fetch.cc:828
gem5::o3::Fetch::decodeToFetchDelay
Cycles decodeToFetchDelay
Decode to fetch delay.
Definition: fetch.hh:447
gem5::o3::Fetch::checkSignalsAndUpdate
bool checkSignalsAndUpdate(ThreadID tid)
Checks all input signals and updates the status as necessary.
Definition: fetch.cc:942
gem5::o3::Fetch::FinishTranslationEvent::fetch
Fetch * fetch
Definition: fetch.hh:132
gem5::o3::Fetch::startupStage
void startupStage()
Initialize stage.
Definition: fetch.cc:288
gem5::o3::Fetch::FetchTranslation::markDelayed
void markDelayed()
Signal that the translation has been delayed due to a hw page table walk.
Definition: fetch.hh:113
gem5::ProbePointArg
ProbePointArg generates a point for the class of Arg.
Definition: thermal_domain.hh:54
gem5::o3::Fetch::FetchTranslation::fetch
Fetch * fetch
Definition: fetch.hh:108
gem5::BaseMMU::Translation
Definition: mmu.hh:55
gem5::o3::Fetch::decodeWidth
unsigned decodeWidth
The width of decode in instructions.
Definition: fetch.hh:462
gem5::o3::MaxThreads
static constexpr int MaxThreads
Definition: limits.hh:38
gem5::o3::Fetch::FinishTranslationEvent::FinishTranslationEvent
FinishTranslationEvent(Fetch *_fetch)
Definition: fetch.hh:137
gem5::o3::Fetch::ppFetch
ProbePointArg< DynInstPtr > * ppFetch
Probe points.
Definition: fetch.hh:200
gem5::o3::Fetch::IcachePort
IcachePort class for instruction fetch.
Definition: fetch.hh:85
gem5::o3::Fetch::FetchTranslation::finish
void finish(const Fault &fault, const RequestPtr &req, gem5::ThreadContext *tc, BaseMMU::Mode mode)
Definition: fetch.hh:116
gem5::o3::Fetch::FetchStatGroup
Definition: fetch.hh:532
gem5::o3::Fetch::toDecode
TimeBuffer< FetchStruct >::wire toDecode
Wire used to write any information heading to decode.
Definition: fetch.hh:411
gem5::o3::Fetch::iqCount
ThreadID iqCount()
Returns the appropriate thread to fetch using the IQ count policy.
Definition: fetch.cc:1453
pc_event.hh
bpred_unit.hh
gem5::o3::Fetch::FetchStatGroup::noActiveThreadStallCycles
statistics::Scalar noActiveThreadStallCycles
Total number of stall cycles caused by no active threads to run.
Definition: fetch.hh:563
gem5::o3::Fetch::issuePipelinedIfetch
bool issuePipelinedIfetch[MaxThreads]
Set to true if a pipelined I-cache request should be issued.
Definition: fetch.hh:526
gem5::o3::Fetch::ThreadStatus
ThreadStatus
Individual thread status.
Definition: fetch.hh:170
gem5::o3::Fetch::fetchPolicy
SMTFetchPolicy fetchPolicy
Fetch policy.
Definition: fetch.hh:194
gem5::o3::Fetch::fromRename
TimeBuffer< TimeStruct >::wire fromRename
Wire to get rename's information from backwards time buffer.
Definition: fetch.hh:401
gem5::o3::Fetch::takeOverFrom
void takeOverFrom()
Takes over from another CPU's thread.
Definition: fetch.cc:451
std::deque< DynInstPtr >
gem5::o3::Fetch::doSquash
void doSquash(const TheISA::PCState &newPC, const DynInstPtr squashInst, ThreadID tid)
Squashes a specific thread and resets the PC.
Definition: fetch.cc:711
gem5::o3::Fetch::activeThreads
std::list< ThreadID > * activeThreads
List of Active Threads.
Definition: fetch.hh:506
gem5::statistics::Counter
double Counter
All counters are of 64-bit values.
Definition: types.hh:47
gem5::o3::Fetch::fetchBufferPC
Addr fetchBufferPC[MaxThreads]
The PC of the first instruction loaded into the fetch buffer.
Definition: fetch.hh:488
gem5::branch_prediction::BPredUnit
Basically a wrapper class to hold both the branch predictor and the BTB.
Definition: bpred_unit.hh:68
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::o3::Fetch::NoGoodAddr
@ NoGoodAddr
Definition: fetch.hh:183
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::o3::Fetch::fromCommit
TimeBuffer< TimeStruct >::wire fromCommit
Wire to get commit's information from backwards time buffer.
Definition: fetch.hh:407
gem5::o3::Fetch::finishTranslation
void finishTranslation(const Fault &fault, const RequestPtr &mem_req)
Definition: fetch.cc:604
gem5::o3::Fetch::Stalls::decode
bool decode
Definition: fetch.hh:439
gem5::o3::Fetch::fetchBufferMask
Addr fetchBufferMask
Mask to align a fetch address to a fetch buffer boundary.
Definition: fetch.hh:482
gem5::o3::Fetch::IcachePort::IcachePort
IcachePort(Fetch *_fetch, CPU *_cpu)
Default constructor.
Definition: fetch.cc:79
gem5::o3::Fetch::FetchStatGroup::icacheWaitRetryStallCycles
statistics::Scalar icacheWaitRetryStallCycles
Total number of stall cycles caused by I-cache wait retrys.
Definition: fetch.hh:570
gem5::o3::Fetch::regProbePoints
void regProbePoints()
Registers probes.
Definition: fetch.cc:153
gem5::o3::Fetch::Inactive
@ Inactive
Definition: fetch.hh:166
gem5::o3::Fetch::icachePort
IcachePort icachePort
Instruction port.
Definition: fetch.hh:523
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
std::list< ThreadID >
gem5::o3::Fetch::setFetchQueue
void setFetchQueue(TimeBuffer< FetchStruct > *fq_ptr)
Sets pointer to time buffer used to communicate to the next stage.
Definition: fetch.cc:281
gem5::o3::Fetch::Stalls::drain
bool drain
Definition: fetch.hh:440
gem5::o3::Fetch::fetchQueueSize
unsigned fetchQueueSize
The size of the fetch queue in micro-ops.
Definition: fetch.hh:491
probe.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::o3::Fetch::branchCount
ThreadID branchCount()
Returns the appropriate thread to fetch using the branch count policy.
Definition: fetch.cc:1524
limits.hh
gem5::o3::Fetch::TrapPending
@ TrapPending
Definition: fetch.hh:177
gem5::o3::Fetch::fetchOffset
Addr fetchOffset[MaxThreads]
Definition: fetch.hh:418
gem5::o3::Fetch::FetchStatGroup::idleRate
statistics::Formula idleRate
Rate of how often fetch was idle.
Definition: fetch.hh:584
gem5::o3::Fetch::FetchStatGroup::predictedBranches
statistics::Scalar predictedBranches
Stat for total number of predicted branches.
Definition: fetch.hh:544
gem5::o3::Fetch::memReq
RequestPtr memReq[MaxThreads]
Memory request used to access cache.
Definition: fetch.hh:426
gem5::o3::Fetch::FinishTranslationEvent::fault
Fault fault
Definition: fetch.hh:133
gem5::o3::Fetch::numThreads
ThreadID numThreads
Number of threads.
Definition: fetch.hh:509
gem5::o3::Fetch::cacheBlkSize
unsigned int cacheBlkSize
Cache block size.
Definition: fetch.hh:474
gem5::o3::Fetch::FetchStatGroup::FetchStatGroup
FetchStatGroup(CPU *cpu, Fetch *fetch)
Definition: fetch.cc:161
gem5::o3::Fetch::fetchStatus
ThreadStatus fetchStatus[MaxThreads]
Per-thread status.
Definition: fetch.hh:191
gem5::o3::Fetch::renameToFetchDelay
Cycles renameToFetchDelay
Rename to fetch delay.
Definition: fetch.hh:450
gem5::o3::Fetch::decoder
TheISA::Decoder * decoder[MaxThreads]
The decoder.
Definition: fetch.hh:359
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242
gem5::o3::Fetch::FinishTranslationEvent
Definition: fetch.hh:129
gem5::TimeBuffer::wire
Definition: timebuf.hh:59
gem5::o3::Fetch::IcacheWaitResponse
@ IcacheWaitResponse
Definition: fetch.hh:180
gem5::o3::Fetch::IcachePort::recvTimingResp
virtual bool recvTimingResp(PacketPtr pkt)
Timing version of receive.
Definition: fetch.cc:1609
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:73
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
eventq.hh

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