gem5  v21.1.0.2
gpu_dyn_inst.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2015-2017 Advanced Micro Devices, Inc.
3  * All rights reserved.
4  *
5  * For use for simulation and test purposes only
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions are met:
9  *
10  * 1. Redistributions of source code must retain the above copyright notice,
11  * this list of conditions and the following disclaimer.
12  *
13  * 2. Redistributions in binary form must reproduce the above copyright notice,
14  * this list of conditions and the following disclaimer in the documentation
15  * and/or other materials provided with the distribution.
16  *
17  * 3. Neither the name of the copyright holder nor the names of its
18  * contributors may be used to endorse or promote products derived from this
19  * software without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31  * POSSIBILITY OF SUCH DAMAGE.
32  */
33 
35 
36 #include "debug/GPUInst.hh"
37 #include "debug/GPUMem.hh"
40 #include "gpu-compute/shader.hh"
41 #include "gpu-compute/wavefront.hh"
42 
43 namespace gem5
44 {
45 
47  GPUStaticInst *static_inst, InstSeqNum instSeqNum)
48  : GPUExecContext(_cu, _wf), scalarAddr(0), addr(computeUnit()->wfSize(),
49  (Addr)0), numScalarReqs(0), isSaveRestore(false),
50  _staticInst(static_inst), _seqNum(instSeqNum),
51  maxSrcVecRegOpSize(-1), maxSrcScalarRegOpSize(-1)
52 {
55  tlbHitLevel.assign(computeUnit()->wfSize(), -1);
56  // vector instructions can have up to 4 source/destination operands
57  d_data = new uint8_t[computeUnit()->wfSize() * 4 * sizeof(double)];
58  a_data = new uint8_t[computeUnit()->wfSize() * 8];
59  x_data = new uint8_t[computeUnit()->wfSize() * 8];
60  // scalar loads can read up to 16 Dwords of data (see publicly
61  // available GCN3 ISA manual)
62  scalar_data = new uint8_t[16 * sizeof(uint32_t)];
63  for (int i = 0; i < (16 * sizeof(uint32_t)); ++i) {
64  scalar_data[i] = 0;
65  }
66  for (int i = 0; i < (computeUnit()->wfSize() * 8); ++i) {
67  a_data[i] = 0;
68  x_data[i] = 0;
69  }
70  for (int i = 0; i < (computeUnit()->wfSize() * 4 * sizeof(double)); ++i) {
71  d_data[i] = 0;
72  }
73  time = 0;
74 
75  cu_id = _cu->cu_id;
76  if (_wf) {
77  simdId = _wf->simdId;
78  wfDynId = _wf->wfDynId;
79  kern_id = _wf->kernId;
80  wg_id = _wf->wgId;
81  wfSlotId = _wf->wfSlotId;
82  } else {
83  simdId = -1;
84  wfDynId = -1;
85  kern_id = -1;
86  wg_id = -1;
87  wfSlotId = -1;
88  }
89 
90 
91  DPRINTF(GPUInst, "%s: generating operand info for %d operands\n",
93 
95 
96 }
97 
99 {
100  delete[] d_data;
101  delete[] a_data;
102  delete[] x_data;
103  delete[] scalar_data;
104  delete _staticInst;
105 }
106 
107 void
109 {
110  _staticInst->execute(gpuDynInst);
111 }
112 
115 {
116  return _staticInst->srcVecRegOperands();
117 }
118 
121 {
122  return _staticInst->dstVecRegOperands();
123 }
124 
127 {
129 }
130 
133 {
135 }
136 
137 int
139 {
140  return _staticInst->numSrcRegOperands();
141 }
142 
143 int
145 {
146  return _staticInst->numDstRegOperands();
147 }
148 
149 int
151 {
152  return _staticInst->numSrcVecOperands();
153 }
154 
155 int
157 {
158  return _staticInst->numDstVecOperands();
159 }
160 
161 int
163 {
164  if (maxSrcVecRegOpSize != -1)
165  return maxSrcVecRegOpSize;
166 
167  maxSrcVecRegOpSize = 0;
168  for (const auto& srcVecOp : srcVecRegOperands())
169  if (srcVecOp.sizeInDWords() > maxSrcVecRegOpSize)
170  maxSrcVecRegOpSize = srcVecOp.sizeInDWords();
171 
172  return maxSrcVecRegOpSize;
173 }
174 
175 int
177 {
178  return _staticInst->numSrcVecDWords();
179 }
180 
181 int
183 {
184  return _staticInst->numDstVecDWords();
185 }
186 
187 int
189 {
191 }
192 
193 int
195 {
197 }
198 
199 int
201 {
202  if (maxSrcScalarRegOpSize != -1)
203  return maxSrcScalarRegOpSize;
204 
206  for (const auto& srcScOp : srcScalarRegOperands())
207  if (srcScOp.sizeInDWords() > maxSrcScalarRegOpSize)
208  maxSrcScalarRegOpSize = srcScOp.sizeInDWords();
209 
210  return maxSrcScalarRegOpSize;
211 }
212 
213 int
215 {
217 }
218 
219 int
221 {
223 }
224 
225 int
227 {
228  return _staticInst->maxOperandSize();
229 }
230 
231 int
233 {
234  return _staticInst->getNumOperands();
235 }
236 
237 bool
239 {
240  return !srcVecRegOperands().empty();
241 }
242 
243 bool
245 {
246  return !dstVecRegOperands().empty();
247 }
248 
249 bool
251 {
252  return !srcScalarRegOperands().empty();
253 }
254 
255 bool
257 {
258  return !dstScalarRegOperands().empty();
259 }
260 
261 bool
262 GPUDynInst::isOpcode(const std::string& opcodeStr,
263  const std::string& extStr) const
264 {
265  return _staticInst->opcode().find(opcodeStr) != std::string::npos &&
266  _staticInst->opcode().find(extStr) != std::string::npos;
267 }
268 
269 bool
270 GPUDynInst::isOpcode(const std::string& opcodeStr) const
271 {
272  return _staticInst->opcode().find(opcodeStr) != std::string::npos;
273 }
274 
275 const std::string&
277 {
278  return _staticInst->disassemble();
279 }
280 
283 {
284  return _seqNum;
285 }
286 
287 enums::StorageClassType
289 {
290  return _staticInst->executed_as;
291 }
292 
293 // Process a memory instruction and (if necessary) submit timing request
294 void
296 {
297  DPRINTF(GPUMem, "CU%d: WF[%d][%d]: mempacket status bitvector=%#x\n",
299 
300  _staticInst->initiateAcc(gpuDynInst);
301 }
302 
303 void
305 {
306  DPRINTF(GPUMem, "CU%d: WF[%d][%d]: mempacket status bitvector="
307  "%#x\n complete",
309 
310  _staticInst->completeAcc(gpuDynInst);
311 }
312 
317 bool
319 {
320  return _staticInst->isALU();
321 }
322 
323 bool
325 {
326  return _staticInst->isBranch();
327 }
328 
329 bool
331 {
332  return _staticInst->isCondBranch();
333 }
334 
335 bool
337 {
338  return _staticInst->isNop();
339 }
340 
341 bool
343 {
344  return _staticInst->isEndOfKernel();
345 }
346 
347 bool
349 {
350  return _staticInst->isKernelLaunch();
351 }
352 
353 bool
355 {
356  return _staticInst->isSDWAInst();
357 }
358 
359 bool
361 {
362  return _staticInst->isDPPInst();
363 }
364 
365 bool
367 {
368  return _staticInst->isReturn();
369 }
370 
371 bool
373 {
375 }
376 
377 bool
379 {
380  return _staticInst->isSpecialOp();
381 }
382 
383 bool
385 {
386  return _staticInst->isWaitcnt();
387 }
388 
389 bool
391 {
392  return _staticInst->isSleep();
393 }
394 
395 bool
397 {
398  return _staticInst->isBarrier();
399 }
400 
401 bool
403 {
404  return _staticInst->isMemSync();
405 }
406 
407 bool
409 {
410  return _staticInst->isMemRef();
411 }
412 
413 bool
415 {
416  return _staticInst->isFlat();
417 }
418 
419 bool
421 {
422  return _staticInst->isLoad();
423 }
424 
425 bool
427 {
428  return _staticInst->isStore();
429 }
430 
431 bool
433 {
434  return _staticInst->isAtomic();
435 }
436 
437 bool
439 {
440  return _staticInst->isAtomicNoRet();
441 }
442 
443 bool
445 {
446  return _staticInst->isAtomicRet();
447 }
448 
449 bool
451 {
452  return !_staticInst->isScalar();
453 }
454 
455 bool
457 {
458  return _staticInst->isScalar();
459 }
460 
461 bool
463 {
464  return _staticInst->readsSCC();
465 }
466 
467 bool
469 {
470  return _staticInst->writesSCC();
471 }
472 
473 bool
475 {
476  for (const auto& srcOp : _staticInst->srcOperands())
477  if (srcOp.isVcc())
478  return true;
479 
480  return _staticInst->readsVCC();
481 }
482 
483 bool
485 {
486  for (const auto& dstOp : _staticInst->dstOperands())
487  if (dstOp.isVcc())
488  return true;
489 
490  return _staticInst->writesVCC();
491 }
492 
493 bool
495 {
496  return _staticInst->readsMode();
497 }
498 
499 bool
501 {
502  return _staticInst->writesMode();
503 }
504 
505 bool
507 {
508  return _staticInst->readsEXEC();
509 }
510 
511 bool
513 {
514  return _staticInst->writesEXEC();
515 }
516 
517 bool
519 {
520  return _staticInst->ignoreExec();
521 }
522 
523 bool
525 {
526  for (const auto& dstOp : _staticInst->dstOperands())
527  if (dstOp.isExec())
528  return true;
529 
530  return _staticInst->writesEXEC();
531 }
532 
533 bool
535 {
536  for (const auto& srcOp : _staticInst->srcOperands())
537  if (srcOp.isExec())
538  return true;
539 
540  return _staticInst->readsEXEC();
541 }
542 
543 bool
545 {
546  for (const auto& dstScalarOp : dstScalarRegOperands())
547  if (dstScalarOp.isFlatScratch())
548  return true;
549 
550  return false;
551 }
552 
553 bool
555 {
556  for (const auto& srcScalarOp : srcScalarRegOperands())
557  if (srcScalarOp.isFlatScratch())
558  return true;
559 
560  return false;
561 }
562 
563 bool
565 {
566  return _staticInst->isAtomicAnd();
567 }
568 
569 bool
571 {
572  return _staticInst->isAtomicOr();
573 }
574 
575 bool
577 {
578  return _staticInst->isAtomicXor();
579 }
580 
581 bool
583 {
584  return _staticInst->isAtomicCAS();
585 }
586 
588 {
589  return _staticInst->isAtomicExch();
590 }
591 
592 bool
594 {
595  return _staticInst->isAtomicAdd();
596 }
597 
598 bool
600 {
601  return _staticInst->isAtomicSub();
602 }
603 
604 bool
606 {
607  return _staticInst->isAtomicInc();
608 }
609 
610 bool
612 {
613  return _staticInst->isAtomicDec();
614 }
615 
616 bool
618 {
619  return _staticInst->isAtomicMax();
620 }
621 
622 bool
624 {
625  return _staticInst->isAtomicMin();
626 }
627 
628 bool
630 {
631  return _staticInst->isArgLoad();
632 }
633 
634 bool
636 {
637  return _staticInst->isGlobalMem();
638 }
639 
640 bool
642 {
643  return _staticInst->isLocalMem();
644 }
645 
646 bool
648 {
649  return _staticInst->isArgSeg();
650 }
651 
652 bool
654 {
655  return _staticInst->isGlobalSeg();
656 }
657 
658 bool
660 {
661  return _staticInst->isGroupSeg();
662 }
663 
664 bool
666 {
667  return _staticInst->isKernArgSeg();
668 }
669 
670 bool
672 {
673  return _staticInst->isPrivateSeg();
674 }
675 
676 bool
678 {
679  return _staticInst->isReadOnlySeg();
680 }
681 
682 bool
684 {
685  return _staticInst->isSpillSeg();
686 }
687 
688 bool
690 {
692 }
693 
694 bool
696 {
697  return _staticInst->isSystemCoherent();
698 }
699 
700 bool
702 {
703  return _staticInst->isF16();
704 }
705 
706 bool
708 {
709  return _staticInst->isF32();
710 }
711 
712 bool
714 {
715  return _staticInst->isF64();
716 }
717 
718 bool
720 {
721  return _staticInst->isFMA();
722 }
723 
724 bool
726 {
727  return _staticInst->isMAC();
728 }
729 
730 bool
732 {
733  return _staticInst->isMAD();
734 }
735 
736 void
738 {
739  assert(mask.any());
740  // find the segment of the first active address, after
741  // that we check that all other active addresses also
742  // fall within the same APE
743  for (int lane = 0; lane < computeUnit()->wfSize(); ++lane) {
744  if (mask[lane]) {
745  if (computeUnit()->shader->isLdsApe(addr[lane])) {
746  // group segment
747  staticInstruction()->executed_as = enums::SC_GROUP;
748  break;
749  } else if (computeUnit()->shader->isScratchApe(addr[lane])) {
750  // private segment
751  staticInstruction()->executed_as = enums::SC_PRIVATE;
752  break;
753  } else if (computeUnit()->shader->isGpuVmApe(addr[lane])) {
754  // we won't support GPUVM
755  fatal("flat access is in GPUVM APE\n");
756  } else if (bits(addr[lane], 63, 47) != 0x1FFFF &&
757  bits(addr[lane], 63, 47)) {
758  // we are in the "hole", this is a memory violation
759  fatal("flat access at addr %#x has a memory violation\n",
760  addr[lane]);
761  } else {
762  // global memory segment
763  staticInstruction()->executed_as = enums::SC_GLOBAL;
764  break;
765  }
766  }
767  }
768 
769  // we should have found the segment
770  assert(executedAs() != enums::SC_NONE);
771 
772  // flat accesses should not straddle multiple APEs so we
773  // must check that all addresses fall within the same APE
774  if (executedAs() == enums::SC_GROUP) {
775  for (int lane = 0; lane < computeUnit()->wfSize(); ++lane) {
776  if (mask[lane]) {
777  // if the first valid addr we found above was LDS,
778  // all the rest should be
779  assert(computeUnit()->shader->isLdsApe(addr[lane]));
780  }
781  }
782  } else if (executedAs() == enums::SC_PRIVATE) {
783  for (int lane = 0; lane < computeUnit()->wfSize(); ++lane) {
784  if (mask[lane]) {
785  // if the first valid addr we found above was private,
786  // all the rest should be
787  assert(computeUnit()->shader->isScratchApe(addr[lane]));
788  }
789  }
790  } else {
791  for (int lane = 0; lane < computeUnit()->wfSize(); ++lane) {
792  if (mask[lane]) {
793  // if the first valid addr we found above was global,
794  // all the rest should be. because we don't have an
795  // explicit range of the global segment, we just make
796  // sure that the address fall in no other APE and that
797  // it is not a memory violation
798  assert(!computeUnit()->shader->isLdsApe(addr[lane]));
799  assert(!computeUnit()->shader->isScratchApe(addr[lane]));
800  assert(!computeUnit()->shader->isGpuVmApe(addr[lane]));
801  assert(!(bits(addr[lane], 63, 47) != 0x1FFFF
802  && bits(addr[lane], 63, 47)));
803  }
804  }
805  }
806 }
807 
808 void
810 {
812 
813 
814  // Now that we know the aperature, do the following:
815  // 1. Transform the flat address to its segmented equivalent.
816  // 2. Set the execUnitId based an the aperture check.
817  // 3. Decrement any extra resources that were reserved. Other
818  // resources are released as normal, below.
819  if (executedAs() == enums::SC_GLOBAL) {
820  // no transormation for global segment
822  if (isLoad()) {
824  } else if (isStore()) {
826  } else if (isAtomic() || isMemSync()) {
829  } else {
830  panic("Invalid memory operation!\n");
831  }
832  } else if (executedAs() == enums::SC_GROUP) {
833  for (int lane = 0; lane < wavefront()->computeUnit->wfSize(); ++lane) {
834  if (mask[lane]) {
835  // flat address calculation goes here.
836  // addr[lane] = segmented address
837  addr[lane] = addr[lane] -
839  assert(addr[lane] <
841  }
842  }
845  if (isLoad()) {
847  } else if (isStore()) {
849  } else if (isAtomic() || isMemSync()) {
852  } else {
853  panic("Invalid memory operation!\n");
854  }
855  } else if (executedAs() == enums::SC_PRIVATE) {
885  uint32_t numSgprs = wavefront()->maxSgprs;
886  uint32_t physSgprIdx =
888  numSgprs - 3);
889  uint32_t offset =
890  wavefront()->computeUnit->srf[simdId]->read(physSgprIdx);
891  physSgprIdx =
893  numSgprs - 4);
894  uint32_t size =
895  wavefront()->computeUnit->srf[simdId]->read(physSgprIdx);
896  for (int lane = 0; lane < wavefront()->computeUnit->wfSize(); ++lane) {
897  if (mask[lane]) {
898  addr[lane] = addr[lane] + lane * size + offset +
901  }
902  }
905  if (isLoad()) {
907  } else if (isStore()) {
909  } else if (isAtomic() || isMemSync()) {
912  } else {
913  panic("Invalid memory operation!\n");
914  }
915  } else {
916  for (int lane = 0; lane < wavefront()->computeUnit->wfSize(); ++lane) {
917  if (mask[lane]) {
918  panic("flat addr %#llx maps to bad segment %d\n",
919  addr[lane], executedAs());
920  }
921  }
922  }
923 }
924 
927 {
928  return _staticInst->srcLiteral();
929 }
930 
931 void
933 {
934  if (_staticInst->isLocalMem()) {
935  // access to LDS (shared) memory
937  } else if (_staticInst->isFlat()) {
939  } else {
940  // access to global memory
941 
942  // update PageDivergence histogram
943  int number_pages_touched = cu->pagesTouched.size();
944  assert(number_pages_touched);
945  cu->stats.pageDivergenceDist.sample(number_pages_touched);
946 
948 
949  for (auto it : cu->pagesTouched) {
950  // see if this page has been touched before. if not, this also
951  // inserts the page into the table.
952  ret = cu->pageAccesses
953  .insert(ComputeUnit::pageDataStruct::value_type(it.first,
954  std::make_pair(1, it.second)));
955 
956  // if yes, then update the stats
957  if (!ret.second) {
958  ret.first->second.first++;
959  ret.first->second.second += it.second;
960  }
961  }
962 
963  cu->pagesTouched.clear();
964 
965  // total number of memory instructions (dynamic)
966  // Atomics are counted as a single memory instruction.
967  // this is # memory instructions per wavefronts, not per workitem
969  }
970 }
971 
972 void
973 GPUDynInst::profileRoundTripTime(Tick currentTime, int hopId)
974 {
975  // Only take the first measurement in the case of coalescing
976  if (roundTripTime.size() > hopId)
977  return;
978 
979  roundTripTime.push_back(currentTime);
980 }
981 
982 void
984 {
985  if (lineAddressTime.count(addr)) {
986  if (lineAddressTime[addr].size() > hopId) {
987  return;
988  }
989 
990  lineAddressTime[addr].push_back(currentTime);
991  } else if (hopId == 0) {
992  auto addressTimeVec = std::vector<Tick> { currentTime };
993  lineAddressTime.insert(std::make_pair(addr, addressTimeVec));
994  }
995 }
996 
997 } // namespace gem5
gem5::GPUStaticInst::initDynOperandInfo
void initDynOperandInfo(Wavefront *wf, ComputeUnit *cu)
Definition: gpu_static_inst.cc:60
gem5::GPUStaticInst::isReturn
bool isReturn() const
Definition: gpu_static_inst.hh:114
gem5::GPUDynInst::wfSlotId
int wfSlotId
Definition: gpu_dyn_inst.hh:195
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:189
gem5::ArmISA::NumVecElemPerVecReg
constexpr unsigned NumVecElemPerVecReg
Definition: vec.hh:58
gem5::GPUStaticInst::isAtomicMin
bool isAtomicMin() const
Definition: gpu_static_inst.hh:169
gem5::GPUStaticInst::isDPPInst
bool isDPPInst() const
Definition: gpu_static_inst.hh:118
gem5::GPUDynInst::isMAD
bool isMAD() const
Definition: gpu_dyn_inst.cc:731
gem5::GPUDynInst::hasDestinationSgpr
bool hasDestinationSgpr() const
Definition: gpu_dyn_inst.cc:256
gem5::GPUDynInst::tlbHitLevel
std::vector< int > tlbHitLevel
Definition: gpu_dyn_inst.hh:458
gem5::GPUStaticInst::isAtomicInc
bool isAtomicInc() const
Definition: gpu_static_inst.hh:166
gem5::GPUDynInst::writesFlatScratch
bool writesFlatScratch() const
Definition: gpu_dyn_inst.cc:544
gem5::GPUStaticInst::numSrcVecOperands
int numSrcVecOperands()
Definition: gpu_static_inst.cc:113
gem5::GPUDynInst::isAtomic
bool isAtomic() const
Definition: gpu_dyn_inst.cc:432
gem5::GPUDynInst::doApertureCheck
void doApertureCheck(const VectorMask &mask)
Definition: gpu_dyn_inst.cc:737
gem5::GPUDynInst::wfDynId
int wfDynId
Definition: gpu_dyn_inst.hh:187
gem5::GPUStaticInst::isMAD
bool isMAD() const
Definition: gpu_static_inst.hh:220
gem5::GPUDynInst::isAtomicDec
bool isAtomicDec() const
Definition: gpu_dyn_inst.cc:611
gem5::GPUDynInst::isCondBranch
bool isCondBranch() const
Definition: gpu_dyn_inst.cc:330
gem5::GPUDynInst::isLoad
bool isLoad() const
Definition: gpu_dyn_inst.cc:420
gem5::GPUDynInst::isKernelLaunch
bool isKernelLaunch() const
Definition: gpu_dyn_inst.cc:348
gem5::GPUStaticInst::numSrcRegOperands
virtual int numSrcRegOperands()=0
gem5::GPUDynInst::isAtomicXor
bool isAtomicXor() const
Definition: gpu_dyn_inst.cc:576
gem5::LdsState::getAddrRange
AddrRange getAddrRange() const
Definition: lds_state.hh:460
gem5::GPUDynInst::roundTripTime
std::vector< Tick > roundTripTime
Definition: gpu_dyn_inst.hh:488
shader.hh
gem5::GPUStaticInst::isAtomicMax
bool isAtomicMax() const
Definition: gpu_static_inst.hh:168
gem5::GPUStaticInst::isAtomicExch
bool isAtomicExch() const
Definition: gpu_static_inst.hh:163
gem5::GPUStaticInst::isNop
bool isNop() const
Definition: gpu_static_inst.hh:113
gem5::GPUDynInst::isKernArgSeg
bool isKernArgSeg() const
Definition: gpu_dyn_inst.cc:665
gem5::Wavefront::flatLmUnitId
int flatLmUnitId
Definition: wavefront.hh:105
gem5::GPUStaticInst::isFlat
bool isFlat() const
Definition: gpu_static_inst.hh:133
gem5::GPUStaticInst::writesEXEC
bool writesEXEC() const
Definition: gpu_static_inst.hh:154
gem5::ComputeUnit::srf
std::vector< ScalarRegisterFile * > srf
Definition: compute_unit.hh:299
gem5::GPUStaticInst::disassemble
const std::string & disassemble()
Definition: gpu_static_inst.cc:49
gem5::Wavefront::maxSgprs
uint32_t maxSgprs
Definition: wavefront.hh:135
gem5::GPUDynInst::seqNum
InstSeqNum seqNum() const
Definition: gpu_dyn_inst.cc:282
gem5::GPUDynInst::_seqNum
const InstSeqNum _seqNum
Definition: gpu_dyn_inst.hh:479
gem5::GPUDynInst::readsExec
bool readsExec() const
Definition: gpu_dyn_inst.cc:506
gem5::GPUStaticInst::isScalar
bool isScalar() const
Definition: gpu_static_inst.hh:146
gem5::Shader::getScratchBase
Addr getScratchBase()
Definition: shader.hh:157
gem5::GPUDynInst::isOpcode
bool isOpcode(const std::string &opcodeStr) const
Definition: gpu_dyn_inst.cc:270
gem5::GPUDynInst::readsMode
bool readsMode() const
Definition: gpu_dyn_inst.cc:494
gem5::GPUDynInst::readsSCC
bool readsSCC() const
Definition: gpu_dyn_inst.cc:462
gem5::GPUDynInst::isFMA
bool isFMA() const
Definition: gpu_dyn_inst.cc:719
gem5::Wavefront
Definition: wavefront.hh:62
gem5::GPUDynInst::_staticInst
GPUStaticInst * _staticInst
Definition: gpu_dyn_inst.hh:478
gem5::GPUDynInst::profileRoundTripTime
void profileRoundTripTime(Tick currentTime, int hopId)
Definition: gpu_dyn_inst.cc:973
gem5::ComputeUnit::ComputeUnitStats::dynamicGMemInstrCnt
statistics::Scalar dynamicGMemInstrCnt
Definition: compute_unit.hh:1025
gem5::GPUDynInst::isArgSeg
bool isArgSeg() const
Definition: gpu_dyn_inst.cc:647
gem5::GPUDynInst::kern_id
int kern_id
Definition: gpu_dyn_inst.hh:189
gem5::GPUStaticInst::isAtomicNoRet
bool isAtomicNoRet() const
Definition: gpu_static_inst.hh:143
gem5::GPUStaticInst::isGroupSeg
bool isGroupSeg() const
Definition: gpu_static_inst.hh:193
gem5::GPUStaticInst::initiateAcc
virtual void initiateAcc(GPUDynInstPtr gpuDynInst)
Definition: gpu_static_inst.hh:226
gem5::ComputeUnit::pagesTouched
std::map< Addr, int > pagesTouched
Definition: compute_unit.hh:380
gpu_static_inst.hh
gem5::GPUDynInst::scalar_data
uint8_t * scalar_data
Definition: gpu_dyn_inst.hh:176
gem5::GPUDynInst::d_data
uint8_t * d_data
Definition: gpu_dyn_inst.hh:174
gem5::VectorMask
std::bitset< std::numeric_limits< unsigned long long >::digits > VectorMask
Definition: misc.hh:47
gem5::Wavefront::kernId
int kernId
Definition: wavefront.hh:99
gem5::GPUDynInst::srcVecRegOperands
const std::vector< OperandInfo > & srcVecRegOperands() const
Definition: gpu_dyn_inst.cc:114
gem5::ComputeUnit::stats
gem5::ComputeUnit::ComputeUnitStats stats
gem5::GPUDynInst::isBarrier
bool isBarrier() const
Definition: gpu_dyn_inst.cc:396
gem5::GPUStaticInst::isWaitcnt
bool isWaitcnt() const
Definition: gpu_static_inst.hh:127
gem5::GPUDynInst::maxSrcVecRegOperandSize
int maxSrcVecRegOperandSize()
Definition: gpu_dyn_inst.cc:162
gem5::GPUStaticInst::writesVCC
bool writesVCC() const
Definition: gpu_static_inst.hh:150
gem5::GPUDynInst::readsVCC
bool readsVCC() const
Definition: gpu_dyn_inst.cc:474
gem5::GPUDynInst::writesExec
bool writesExec() const
Definition: gpu_dyn_inst.cc:512
gem5::GPUStaticInst::executed_as
enums::StorageClassType executed_as
Definition: gpu_static_inst.hh:243
gem5::GPUDynInst::numSrcScalarRegOperands
int numSrcScalarRegOperands() const
Definition: gpu_dyn_inst.cc:188
gem5::GPUStaticInst::srcScalarRegOperands
const std::vector< OperandInfo > & srcScalarRegOperands() const
Definition: gpu_static_inst.hh:282
gem5::GPUDynInst::isGroupSeg
bool isGroupSeg() const
Definition: gpu_dyn_inst.cc:659
gem5::GPUDynInst::numSrcScalarDWords
int numSrcScalarDWords()
Definition: gpu_dyn_inst.cc:214
std::vector
STL vector class.
Definition: stl.hh:37
gem5::GPUDynInst::isAtomicInc
bool isAtomicInc() const
Definition: gpu_dyn_inst.cc:605
gem5::GPUStaticInst::isMemSync
bool isMemSync() const
Definition: gpu_static_inst.hh:131
gem5::GPUStaticInst::dstVecRegOperands
const std::vector< OperandInfo > & dstVecRegOperands() const
Definition: gpu_static_inst.hh:276
gem5::GPUStaticInst::isSDWAInst
bool isSDWAInst() const
Definition: gpu_static_inst.hh:117
gem5::GPUDynInst::isAtomicAnd
bool isAtomicAnd() const
Definition: gpu_dyn_inst.cc:564
gem5::GPUDynInst::initiateAcc
void initiateAcc(GPUDynInstPtr gpuDynInst)
Definition: gpu_dyn_inst.cc:295
gem5::GPUDynInst::numSrcVecRegOperands
int numSrcVecRegOperands() const
Definition: gpu_dyn_inst.cc:150
gem5::GPUStaticInst::isFMA
bool isFMA() const
Definition: gpu_static_inst.hh:218
gem5::GPUStaticInst
Definition: gpu_static_inst.hh:63
gem5::ComputeUnit::getLds
LdsState & getLds() const
Definition: compute_unit.hh:474
gem5::GPUDynInst::disassemble
const std::string & disassemble() const
Definition: gpu_dyn_inst.cc:276
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::ComputeUnit::shader
Shader * shader
Definition: compute_unit.hh:355
gem5::GPUStaticInst::isGloballyCoherent
bool isGloballyCoherent() const
Coherence domain of a memory instruction.
Definition: gpu_static_inst.hh:209
gem5::GPUDynInst::isAtomicRet
bool isAtomicRet() const
Definition: gpu_dyn_inst.cc:444
gem5::ComputeUnit::cu_id
int cu_id
Definition: compute_unit.hh:294
gem5::statistics::DistBase::sample
void sample(const U &v, int n=1)
Add a value to the distribtion n times.
Definition: statistics.hh:1325
gem5::GPUStaticInst::numDstVecOperands
int numDstVecOperands()
Definition: gpu_static_inst.cc:119
gem5::GPUDynInst::isAtomicNoRet
bool isAtomicNoRet() const
Definition: gpu_dyn_inst.cc:438
gem5::ComputeUnit::ComputeUnitStats::dynamicFlatMemInstrCnt
statistics::Scalar dynamicFlatMemInstrCnt
Definition: compute_unit.hh:1027
wavefront.hh
gem5::GPUDynInst::profileLineAddressTime
void profileLineAddressTime(Addr addr, Tick currentTime, int hopId)
Definition: gpu_dyn_inst.cc:983
gem5::mask
constexpr uint64_t mask(unsigned nbits)
Generate a 64-bit mask of 'nbits' 1s, right justified.
Definition: bitfield.hh:63
gem5::GPUStaticInst::isStore
bool isStore() const
Definition: gpu_static_inst.hh:135
gem5::GPUStaticInst::isALU
bool isALU() const
Definition: gpu_static_inst.hh:110
gem5::Wavefront::flatGmUnitId
int flatGmUnitId
Definition: wavefront.hh:106
gem5::GPUStaticInst::isAtomicRet
bool isAtomicRet() const
Definition: gpu_static_inst.hh:144
gem5::Wavefront::wrLmReqsInPipe
int wrLmReqsInPipe
Definition: wavefront.hh:188
gem5::GPUExecContext::computeUnit
ComputeUnit * computeUnit()
Definition: gpu_exec_context.cc:46
gem5::Wavefront::wgId
uint32_t wgId
Definition: wavefront.hh:162
gem5::GPUStaticInst::opcode
const std::string & opcode() const
Definition: gpu_static_inst.hh:264
gem5::GPUStaticInst::isEndOfKernel
bool isEndOfKernel() const
Definition: gpu_static_inst.hh:115
gem5::RegisterManager::mapSgpr
int mapSgpr(Wavefront *w, int sgprIndex)
Definition: register_manager.cc:104
gem5::GPUDynInst::isSleep
bool isSleep() const
Definition: gpu_dyn_inst.cc:390
gem5::GPUDynInst::time
Tick time
Definition: gpu_dyn_inst.hh:199
gem5::GPUDynInst::hasDestinationVgpr
bool hasDestinationVgpr() const
Definition: gpu_dyn_inst.cc:244
gem5::ComputeUnit
Definition: compute_unit.hh:203
gem5::ComputeUnit::pageAccesses
pageDataStruct pageAccesses
Definition: compute_unit.hh:485
gem5::GPUStaticInst::readsMode
bool readsMode() const
Definition: gpu_static_inst.hh:155
gem5::GPUDynInst::isVector
bool isVector() const
Definition: gpu_dyn_inst.cc:450
gem5::GPUDynInst::isGloballyCoherent
bool isGloballyCoherent() const
Definition: gpu_dyn_inst.cc:689
gem5::GPUStaticInst::isBarrier
bool isBarrier() const
Definition: gpu_static_inst.hh:130
gem5::GPUStaticInst::isF16
bool isF16() const
Definition: gpu_static_inst.hh:213
gem5::GPUDynInst::statusVector
std::vector< int > statusVector
Definition: gpu_dyn_inst.hh:456
gem5::GPUStaticInst::numDstScalarDWords
int numDstScalarDWords()
Definition: gpu_static_inst.cc:184
gem5::GPUDynInst::isMemSync
bool isMemSync() const
Definition: gpu_dyn_inst.cc:402
gem5::GPUStaticInst::isBranch
bool isBranch() const
Definition: gpu_static_inst.hh:111
gem5::GPUStaticInst::execute
virtual void execute(GPUDynInstPtr gpuDynInst)=0
gem5::GPUStaticInst::isAtomicSub
bool isAtomicSub() const
Definition: gpu_static_inst.hh:165
gem5::Wavefront::wrGmReqsInPipe
int wrGmReqsInPipe
Definition: wavefront.hh:189
gem5::GPUDynInst::GPUDynInst
GPUDynInst(ComputeUnit *_cu, Wavefront *_wf, GPUStaticInst *static_inst, uint64_t instSeqNum)
Definition: gpu_dyn_inst.cc:46
gem5::GPUDynInst::hasSourceVgpr
bool hasSourceVgpr() const
Definition: gpu_dyn_inst.cc:238
gem5::GPUStaticInst::maxOperandSize
int maxOperandSize()
Definition: gpu_static_inst.cc:199
gem5::GPUDynInst::isNop
bool isNop() const
Definition: gpu_dyn_inst.cc:336
gem5::GPUStaticInst::writesMode
bool writesMode() const
Definition: gpu_static_inst.hh:156
gem5::GPUStaticInst::getNumOperands
virtual int getNumOperands()=0
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::GPUDynInst::isUnconditionalJump
bool isUnconditionalJump() const
Definition: gpu_dyn_inst.cc:372
gem5::GPUStaticInst::srcLiteral
virtual TheGpuISA::ScalarRegU32 srcLiteral() const
Definition: gpu_static_inst.hh:80
gem5::GPUDynInst::dstScalarRegOperands
const std::vector< OperandInfo > & dstScalarRegOperands() const
Definition: gpu_dyn_inst.cc:132
gem5::Wavefront::rdLmReqsInPipe
int rdLmReqsInPipe
Definition: wavefront.hh:186
gem5::GPUDynInst::isAtomicMin
bool isAtomicMin() const
Definition: gpu_dyn_inst.cc:623
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::GPUDynInst::isAtomicOr
bool isAtomicOr() const
Definition: gpu_dyn_inst.cc:570
gem5::GPUStaticInst::numDstVecDWords
int numDstVecDWords()
Definition: gpu_static_inst.cc:141
gem5::GPUStaticInst::isAtomicDec
bool isAtomicDec() const
Definition: gpu_static_inst.hh:167
gem5::GPUStaticInst::srcVecRegOperands
const std::vector< OperandInfo > & srcVecRegOperands() const
Definition: gpu_static_inst.hh:270
gem5::GPUDynInst::numDstRegOperands
int numDstRegOperands()
Definition: gpu_dyn_inst.cc:144
gem5::GPUDynInst::resolveFlatSegment
void resolveFlatSegment(const VectorMask &mask)
Definition: gpu_dyn_inst.cc:809
gem5::GPUDynInst::addr
std::vector< Addr > addr
Definition: gpu_dyn_inst.hh:170
gem5::GPUDynInst::x_data
uint8_t * x_data
Definition: gpu_dyn_inst.hh:180
gem5::Wavefront::wfSlotId
const int wfSlotId
Definition: wavefront.hh:98
gem5::GPUDynInst::isMAC
bool isMAC() const
Definition: gpu_dyn_inst.cc:725
gem5::Wavefront::execUnitId
int execUnitId
Definition: wavefront.hh:104
gem5::ComputeUnit::registerManager
RegisterManager * registerManager
Definition: compute_unit.hh:280
gem5::GPUDynInst::isSDWAInst
bool isSDWAInst() const
Definition: gpu_dyn_inst.cc:354
gem5::GPUDynInst::writesMode
bool writesMode() const
Definition: gpu_dyn_inst.cc:500
gem5::GPUDynInst::cu_id
int cu_id
Definition: gpu_dyn_inst.hh:191
gem5::GPUDynInst::isSystemCoherent
bool isSystemCoherent() const
Definition: gpu_dyn_inst.cc:695
scalar_register_file.hh
gem5::GPUDynInst::getNumOperands
int getNumOperands() const
Definition: gpu_dyn_inst.cc:232
gpu_dyn_inst.hh
gem5::GPUDynInst::dstVecRegOperands
const std::vector< OperandInfo > & dstVecRegOperands() const
Definition: gpu_dyn_inst.cc:120
gem5::AddrRange::size
Addr size() const
Get the size of the address range.
Definition: addr_range.hh:300
gem5::GPUDynInst::numSrcRegOperands
int numSrcRegOperands()
Definition: gpu_dyn_inst.cc:138
gem5::GPUDynInst::staticInstruction
GPUStaticInst * staticInstruction()
Definition: gpu_dyn_inst.hh:213
gem5::GPUStaticInst::dstScalarRegOperands
const std::vector< OperandInfo > & dstScalarRegOperands() const
Definition: gpu_static_inst.hh:288
gem5::ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:144
gem5::GPUStaticInst::isMAC
bool isMAC() const
Definition: gpu_static_inst.hh:219
gem5::Shader::ldsApe
const ApertureRegister & ldsApe() const
Definition: shader.hh:120
gem5::GPUDynInst::isLocalMem
bool isLocalMem() const
Definition: gpu_dyn_inst.cc:641
gem5::GPUStaticInst::numDstScalarOperands
int numDstScalarOperands()
Definition: gpu_static_inst.cc:163
gem5::GPUDynInst::numDstScalarDWords
int numDstScalarDWords()
Definition: gpu_dyn_inst.cc:220
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::GPUStaticInst::isAtomicCAS
bool isAtomicCAS() const
Definition: gpu_static_inst.hh:162
gem5::GPUDynInst::~GPUDynInst
~GPUDynInst()
Definition: gpu_dyn_inst.cc:98
gem5::GPUDynInst::isDPPInst
bool isDPPInst() const
Definition: gpu_dyn_inst.cc:360
gem5::GPUDynInst::isF32
bool isF32() const
Definition: gpu_dyn_inst.cc:707
gem5::GPUStaticInst::isReadOnlySeg
bool isReadOnlySeg() const
Definition: gpu_static_inst.hh:196
std::pair
STL pair class.
Definition: stl.hh:58
gem5::GPUDynInst::maxSrcScalarRegOpSize
int maxSrcScalarRegOpSize
Definition: gpu_dyn_inst.hh:481
gem5::Wavefront::wfDynId
uint64_t wfDynId
Definition: wavefront.hh:228
gem5::Wavefront::computeUnit
ComputeUnit * computeUnit
Definition: wavefront.hh:108
gem5::GPUDynInst::writesVCC
bool writesVCC() const
Definition: gpu_dyn_inst.cc:484
gem5::GPUStaticInst::numSrcScalarDWords
int numSrcScalarDWords()
Definition: gpu_static_inst.cc:169
gem5::GPUDynInst::numDstScalarRegOperands
int numDstScalarRegOperands() const
Definition: gpu_dyn_inst.cc:194
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::GPUStaticInst::readsVCC
bool readsVCC() const
Definition: gpu_static_inst.hh:149
gem5::GPUDynInst::isStore
bool isStore() const
Definition: gpu_dyn_inst.cc:426
gem5::GPUStaticInst::isLoad
bool isLoad() const
Definition: gpu_static_inst.hh:134
gem5::GPUDynInst::ignoreExec
bool ignoreExec() const
Definition: gpu_dyn_inst.cc:518
gem5::Shader::isLdsApe
bool isLdsApe(Addr addr) const
Definition: shader.hh:140
gem5::GPUExecContext::wavefront
Wavefront * wavefront()
Definition: gpu_exec_context.cc:52
gem5::GPUStaticInst::srcOperands
const std::vector< OperandInfo > & srcOperands() const
Definition: gpu_static_inst.hh:266
gem5::GPUDynInstPtr
std::shared_ptr< GPUDynInst > GPUDynInstPtr
Definition: misc.hh:51
gem5::GPUStaticInst::isKernArgSeg
bool isKernArgSeg() const
Definition: gpu_static_inst.hh:194
gem5::GPUDynInst::isFlat
bool isFlat() const
Definition: gpu_dyn_inst.cc:414
gem5::ComputeUnit::wfSize
int wfSize() const
Definition: compute_unit.hh:396
gem5::Wavefront::decVMemInstsIssued
void decVMemInstsIssued()
Definition: wavefront.cc:1347
gem5::GPUStaticInst::dstOperands
const std::vector< OperandInfo > & dstOperands() const
Definition: gpu_static_inst.hh:267
gem5::Wavefront::rdGmReqsInPipe
int rdGmReqsInPipe
Definition: wavefront.hh:187
gem5::GPUDynInst::updateStats
void updateStats()
Definition: gpu_dyn_inst.cc:932
gem5::GPUStaticInst::isAtomicAdd
bool isAtomicAdd() const
Definition: gpu_static_inst.hh:164
gem5::GPUStaticInst::isUnconditionalJump
bool isUnconditionalJump() const
Definition: gpu_static_inst.hh:121
gem5::GPUStaticInst::isKernelLaunch
bool isKernelLaunch() const
Definition: gpu_static_inst.hh:116
gem5::GPUStaticInst::isF32
bool isF32() const
Definition: gpu_static_inst.hh:214
gem5::GPUExecContext
Definition: gpu_exec_context.hh:47
gem5::GPUDynInst::isSpillSeg
bool isSpillSeg() const
Definition: gpu_dyn_inst.cc:683
gem5::GPUStaticInst::isF64
bool isF64() const
Definition: gpu_static_inst.hh:215
gem5::ApertureRegister::base
Addr base
Definition: shader.hh:77
gem5::GPUDynInst::execute
void execute(GPUDynInstPtr gpuDynInst)
Definition: gpu_dyn_inst.cc:108
gem5::GPUDynInst::simdId
int simdId
Definition: gpu_dyn_inst.hh:185
gem5::Wavefront::decLGKMInstsIssued
void decLGKMInstsIssued()
Definition: wavefront.cc:1359
gem5::GPUStaticInst::writesSCC
bool writesSCC() const
Definition: gpu_static_inst.hh:148
gem5::GPUDynInst::isScalar
bool isScalar() const
Definition: gpu_dyn_inst.cc:456
gem5::GPUDynInst::isSpecialOp
bool isSpecialOp() const
Definition: gpu_dyn_inst.cc:378
gem5::GPUDynInst::readsFlatScratch
bool readsFlatScratch() const
Definition: gpu_dyn_inst.cc:554
gem5::GPUDynInst::readsExecMask
bool readsExecMask() const
Definition: gpu_dyn_inst.cc:534
gem5::GPUDynInst::isAtomicAdd
bool isAtomicAdd() const
Definition: gpu_dyn_inst.cc:593
gem5::GPUStaticInst::isSpillSeg
bool isSpillSeg() const
Definition: gpu_static_inst.hh:197
gem5::GPUDynInst::isGlobalSeg
bool isGlobalSeg() const
Definition: gpu_dyn_inst.cc:653
gem5::GPUDynInst::numDstVecRegOperands
int numDstVecRegOperands() const
Definition: gpu_dyn_inst.cc:156
gem5::GPUDynInst::completeAcc
void completeAcc(GPUDynInstPtr gpuDynInst)
Definition: gpu_dyn_inst.cc:304
gem5::GPUDynInst::isMemRef
bool isMemRef() const
Definition: gpu_dyn_inst.cc:408
gem5::GPUStaticInst::isSystemCoherent
bool isSystemCoherent() const
Definition: gpu_static_inst.hh:210
gem5::GPUDynInst::numDstVecDWords
int numDstVecDWords()
Definition: gpu_dyn_inst.cc:182
gem5::GPUStaticInst::isAtomicOr
bool isAtomicOr() const
Definition: gpu_static_inst.hh:160
gem5::GPUDynInst::isEndOfKernel
bool isEndOfKernel() const
Definition: gpu_dyn_inst.cc:342
gem5::GPUDynInst::isBranch
bool isBranch() const
Definition: gpu_dyn_inst.cc:324
gem5::GPUStaticInst::numSrcScalarOperands
int numSrcScalarOperands()
Definition: gpu_static_inst.cc:157
gem5::GPUDynInst::maxSrcVecRegOpSize
int maxSrcVecRegOpSize
Definition: gpu_dyn_inst.hh:480
gem5::GPUStaticInst::isGlobalMem
bool isGlobalMem() const
Definition: gpu_static_inst.hh:178
gem5::GPUDynInst::a_data
uint8_t * a_data
Definition: gpu_dyn_inst.hh:178
gem5::GPUDynInst::srcLiteral
TheGpuISA::ScalarRegU32 srcLiteral() const
Definition: gpu_dyn_inst.cc:926
gem5::GPUDynInst::isF16
bool isF16() const
Definition: gpu_dyn_inst.cc:701
gem5::GPUDynInst::lineAddressTime
std::map< Addr, std::vector< Tick > > lineAddressTime
Definition: gpu_dyn_inst.hh:492
gem5::GPUStaticInst::readsEXEC
bool readsEXEC() const
Definition: gpu_static_inst.hh:153
gem5::GPUDynInst::maxSrcScalarRegOperandSize
int maxSrcScalarRegOperandSize()
Definition: gpu_dyn_inst.cc:200
gem5::GPUDynInst::isArgLoad
bool isArgLoad() const
Definition: gpu_dyn_inst.cc:629
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::GPUStaticInst::isMemRef
bool isMemRef() const
Definition: gpu_static_inst.hh:132
gem5::GPUStaticInst::isAtomicXor
bool isAtomicXor() const
Definition: gpu_static_inst.hh:161
sc_core::SC_NONE
@ SC_NONE
Definition: sc_report.hh:50
gem5::GPUDynInst::isReadOnlySeg
bool isReadOnlySeg() const
Definition: gpu_dyn_inst.cc:677
gem5::GPUStaticInst::isAtomic
bool isAtomic() const
Definition: gpu_static_inst.hh:138
gem5::GPUStaticInst::isArgLoad
bool isArgLoad() const
Definition: gpu_static_inst.hh:172
gem5::ComputeUnit::ComputeUnitStats::pageDivergenceDist
statistics::Distribution pageDivergenceDist
Definition: compute_unit.hh:1023
gem5::GPUStaticInst::numSrcVecDWords
int numSrcVecDWords()
Definition: gpu_static_inst.cc:125
gem5::GPUDynInst::isAtomicMax
bool isAtomicMax() const
Definition: gpu_dyn_inst.cc:617
gem5::GPUDynInst::isPrivateSeg
bool isPrivateSeg() const
Definition: gpu_dyn_inst.cc:671
gem5::GPUStaticInst::isAtomicAnd
bool isAtomicAnd() const
Definition: gpu_static_inst.hh:159
gem5::GPUDynInst::wg_id
int wg_id
Definition: gpu_dyn_inst.hh:193
gem5::GPUDynInst::writesExecMask
bool writesExecMask() const
Definition: gpu_dyn_inst.cc:524
gem5::GPUStaticInst::readsSCC
bool readsSCC() const
Definition: gpu_static_inst.hh:147
gem5::GPUDynInst::hasSourceSgpr
bool hasSourceSgpr() const
Definition: gpu_dyn_inst.cc:250
gem5::GPUStaticInst::isArgSeg
bool isArgSeg() const
Definition: gpu_static_inst.hh:191
gem5::ComputeUnit::ComputeUnitStats::dynamicLMemInstrCnt
statistics::Scalar dynamicLMemInstrCnt
Definition: compute_unit.hh:1028
gem5::GPUStaticInst::initOperandInfo
virtual void initOperandInfo()=0
gem5::GPUDynInst::isAtomicCAS
bool isAtomicCAS() const
Definition: gpu_dyn_inst.cc:582
gem5::GPUStaticInst::completeAcc
virtual void completeAcc(GPUDynInstPtr gpuDynInst)
Definition: gpu_static_inst.hh:233
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::GPUDynInst::numSrcVecDWords
int numSrcVecDWords()
Definition: gpu_dyn_inst.cc:176
gem5::GPUDynInst::writesSCC
bool writesSCC() const
Definition: gpu_dyn_inst.cc:468
gem5::GPUExecContext::cu
ComputeUnit * cu
Definition: gpu_exec_context.hh:64
gem5::GPUDynInst::isWaitcnt
bool isWaitcnt() const
Definition: gpu_dyn_inst.cc:384
gem5::GPUDynInst::isAtomicExch
bool isAtomicExch() const
Definition: gpu_dyn_inst.cc:587
gem5::GPUDynInst::isF64
bool isF64() const
Definition: gpu_dyn_inst.cc:713
gem5::GPUStaticInst::isSpecialOp
bool isSpecialOp() const
Definition: gpu_static_inst.hh:126
gem5::GPUStaticInst::isPrivateSeg
bool isPrivateSeg() const
Definition: gpu_static_inst.hh:195
gem5::GPUDynInst::isAtomicSub
bool isAtomicSub() const
Definition: gpu_dyn_inst.cc:599
gem5::GPUStaticInst::ignoreExec
bool ignoreExec() const
Definition: gpu_static_inst.hh:157
gem5::GPUDynInst::isALU
bool isALU() const
accessor methods for the attributes of the underlying GPU static instruction
Definition: gpu_dyn_inst.cc:318
gem5::GPUStaticInst::isLocalMem
bool isLocalMem() const
Definition: gpu_static_inst.hh:186
gem5::GPUDynInst::exec_mask
VectorMask exec_mask
Definition: gpu_dyn_inst.hh:182
gem5::GPUStaticInst::numDstRegOperands
virtual int numDstRegOperands()=0
gem5::GPUDynInst::isReturn
bool isReturn() const
Definition: gpu_dyn_inst.cc:366
gem5::GPUDynInst::isGlobalMem
bool isGlobalMem() const
Definition: gpu_dyn_inst.cc:635
gem5::Gcn3ISA::ScalarRegU32
uint32_t ScalarRegU32
Definition: gpu_registers.hh:155
gem5::GPUStaticInst::isSleep
bool isSleep() const
Definition: gpu_static_inst.hh:128
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::GPUStaticInst::isGlobalSeg
bool isGlobalSeg() const
Definition: gpu_static_inst.hh:192
gem5::GPUDynInst::maxOperandSize
int maxOperandSize()
Definition: gpu_dyn_inst.cc:226
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::GPUDynInst::srcScalarRegOperands
const std::vector< OperandInfo > & srcScalarRegOperands() const
Definition: gpu_dyn_inst.cc:126
gem5::GPUStaticInst::isCondBranch
bool isCondBranch() const
Definition: gpu_static_inst.hh:112
gem5::GPUDynInst::executedAs
enums::StorageClassType executedAs()
Definition: gpu_dyn_inst.cc:288
gem5::Shader::getHiddenPrivateBase
Addr getHiddenPrivateBase()
Definition: shader.hh:163
gem5::Wavefront::simdId
const int simdId
Definition: wavefront.hh:101

Generated on Tue Sep 21 2021 12:25:23 for gem5 by doxygen 1.8.17