gem5  v22.0.0.1
gpu_dyn_inst.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2015-2017 Advanced Micro Devices, Inc.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *
8  * 1. Redistributions of source code must retain the above copyright notice,
9  * this list of conditions and the following disclaimer.
10  *
11  * 2. Redistributions in binary form must reproduce the above copyright notice,
12  * this list of conditions and the following disclaimer in the documentation
13  * and/or other materials provided with the distribution.
14  *
15  * 3. Neither the name of the copyright holder nor the names of its
16  * contributors may be used to endorse or promote products derived from this
17  * software without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31 
33 
34 #include "debug/GPUInst.hh"
35 #include "debug/GPUMem.hh"
38 #include "gpu-compute/shader.hh"
39 #include "gpu-compute/wavefront.hh"
40 
41 namespace gem5
42 {
43 
45  GPUStaticInst *static_inst, InstSeqNum instSeqNum)
46  : GPUExecContext(_cu, _wf), scalarAddr(0), addr(computeUnit()->wfSize(),
47  (Addr)0), numScalarReqs(0), isSaveRestore(false),
48  _staticInst(static_inst), _seqNum(instSeqNum),
49  maxSrcVecRegOpSize(-1), maxSrcScalarRegOpSize(-1)
50 {
53  tlbHitLevel.assign(computeUnit()->wfSize(), -1);
54  // vector instructions can have up to 4 source/destination operands
55  d_data = new uint8_t[computeUnit()->wfSize() * 4 * sizeof(double)];
56  a_data = new uint8_t[computeUnit()->wfSize() * 8];
57  x_data = new uint8_t[computeUnit()->wfSize() * 8];
58  // scalar loads can read up to 16 Dwords of data (see publicly
59  // available GCN3 ISA manual)
60  scalar_data = new uint8_t[16 * sizeof(uint32_t)];
61  for (int i = 0; i < (16 * sizeof(uint32_t)); ++i) {
62  scalar_data[i] = 0;
63  }
64  for (int i = 0; i < (computeUnit()->wfSize() * 8); ++i) {
65  a_data[i] = 0;
66  x_data[i] = 0;
67  }
68  for (int i = 0; i < (computeUnit()->wfSize() * 4 * sizeof(double)); ++i) {
69  d_data[i] = 0;
70  }
71  time = 0;
72 
73  cu_id = _cu->cu_id;
74  if (_wf) {
75  simdId = _wf->simdId;
76  wfDynId = _wf->wfDynId;
77  kern_id = _wf->kernId;
78  wg_id = _wf->wgId;
79  wfSlotId = _wf->wfSlotId;
80  } else {
81  simdId = -1;
82  wfDynId = -1;
83  kern_id = -1;
84  wg_id = -1;
85  wfSlotId = -1;
86  }
87 
88 
89  DPRINTF(GPUInst, "%s: generating operand info for %d operands\n",
91 
93 
94 }
95 
97 {
98  delete[] d_data;
99  delete[] a_data;
100  delete[] x_data;
101  delete[] scalar_data;
102  delete _staticInst;
103 }
104 
105 void
107 {
108  _staticInst->execute(gpuDynInst);
109 }
110 
113 {
114  return _staticInst->srcVecRegOperands();
115 }
116 
119 {
120  return _staticInst->dstVecRegOperands();
121 }
122 
125 {
127 }
128 
131 {
133 }
134 
135 int
137 {
138  return _staticInst->numSrcRegOperands();
139 }
140 
141 int
143 {
144  return _staticInst->numDstRegOperands();
145 }
146 
147 int
149 {
150  return _staticInst->numSrcVecOperands();
151 }
152 
153 int
155 {
156  return _staticInst->numDstVecOperands();
157 }
158 
159 int
161 {
162  if (maxSrcVecRegOpSize != -1)
163  return maxSrcVecRegOpSize;
164 
165  maxSrcVecRegOpSize = 0;
166  for (const auto& srcVecOp : srcVecRegOperands())
167  if (srcVecOp.sizeInDWords() > maxSrcVecRegOpSize)
168  maxSrcVecRegOpSize = srcVecOp.sizeInDWords();
169 
170  return maxSrcVecRegOpSize;
171 }
172 
173 int
175 {
176  return _staticInst->numSrcVecDWords();
177 }
178 
179 int
181 {
182  return _staticInst->numDstVecDWords();
183 }
184 
185 int
187 {
189 }
190 
191 int
193 {
195 }
196 
197 int
199 {
200  if (maxSrcScalarRegOpSize != -1)
201  return maxSrcScalarRegOpSize;
202 
204  for (const auto& srcScOp : srcScalarRegOperands())
205  if (srcScOp.sizeInDWords() > maxSrcScalarRegOpSize)
206  maxSrcScalarRegOpSize = srcScOp.sizeInDWords();
207 
208  return maxSrcScalarRegOpSize;
209 }
210 
211 int
213 {
215 }
216 
217 int
219 {
221 }
222 
223 int
225 {
226  return _staticInst->maxOperandSize();
227 }
228 
229 int
231 {
232  return _staticInst->getNumOperands();
233 }
234 
235 bool
237 {
238  return !srcVecRegOperands().empty();
239 }
240 
241 bool
243 {
244  return !dstVecRegOperands().empty();
245 }
246 
247 bool
249 {
250  return !srcScalarRegOperands().empty();
251 }
252 
253 bool
255 {
256  return !dstScalarRegOperands().empty();
257 }
258 
259 bool
260 GPUDynInst::isOpcode(const std::string& opcodeStr,
261  const std::string& extStr) const
262 {
263  return _staticInst->opcode().find(opcodeStr) != std::string::npos &&
264  _staticInst->opcode().find(extStr) != std::string::npos;
265 }
266 
267 bool
268 GPUDynInst::isOpcode(const std::string& opcodeStr) const
269 {
270  return _staticInst->opcode().find(opcodeStr) != std::string::npos;
271 }
272 
273 const std::string&
275 {
276  return _staticInst->disassemble();
277 }
278 
281 {
282  return _seqNum;
283 }
284 
285 Addr
287 {
288  return wavefront()->pc();
289 }
290 
291 void
293 {
294  wavefront()->pc(_pc);
295 }
296 
297 enums::StorageClassType
299 {
300  return _staticInst->executed_as;
301 }
302 
303 // Process a memory instruction and (if necessary) submit timing request
304 void
306 {
307  DPRINTF(GPUMem, "CU%d: WF[%d][%d]: mempacket status bitvector=%#x\n",
309 
310  _staticInst->initiateAcc(gpuDynInst);
311 }
312 
313 void
315 {
316  DPRINTF(GPUMem, "CU%d: WF[%d][%d]: mempacket status bitvector="
317  "%#x\n complete",
319 
320  _staticInst->completeAcc(gpuDynInst);
321 }
322 
327 bool
329 {
330  return _staticInst->isALU();
331 }
332 
333 bool
335 {
336  return _staticInst->isBranch();
337 }
338 
339 bool
341 {
342  return _staticInst->isCondBranch();
343 }
344 
345 bool
347 {
348  return _staticInst->isNop();
349 }
350 
351 bool
353 {
354  return _staticInst->isEndOfKernel();
355 }
356 
357 bool
359 {
360  return _staticInst->isKernelLaunch();
361 }
362 
363 bool
365 {
366  return _staticInst->isSDWAInst();
367 }
368 
369 bool
371 {
372  return _staticInst->isDPPInst();
373 }
374 
375 bool
377 {
378  return _staticInst->isReturn();
379 }
380 
381 bool
383 {
385 }
386 
387 bool
389 {
390  return _staticInst->isSpecialOp();
391 }
392 
393 bool
395 {
396  return _staticInst->isWaitcnt();
397 }
398 
399 bool
401 {
402  return _staticInst->isSleep();
403 }
404 
405 bool
407 {
408  return _staticInst->isBarrier();
409 }
410 
411 bool
413 {
414  return _staticInst->isMemSync();
415 }
416 
417 bool
419 {
420  return _staticInst->isMemRef();
421 }
422 
423 bool
425 {
426  return _staticInst->isFlat();
427 }
428 
429 bool
431 {
432  return _staticInst->isFlatGlobal();
433 }
434 
435 bool
437 {
438  return _staticInst->isLoad();
439 }
440 
441 bool
443 {
444  return _staticInst->isStore();
445 }
446 
447 bool
449 {
450  return _staticInst->isAtomic();
451 }
452 
453 bool
455 {
456  return _staticInst->isAtomicNoRet();
457 }
458 
459 bool
461 {
462  return _staticInst->isAtomicRet();
463 }
464 
465 bool
467 {
468  return !_staticInst->isScalar();
469 }
470 
471 bool
473 {
474  return _staticInst->isScalar();
475 }
476 
477 bool
479 {
480  return _staticInst->readsSCC();
481 }
482 
483 bool
485 {
486  return _staticInst->writesSCC();
487 }
488 
489 bool
491 {
492  for (const auto& srcOp : _staticInst->srcOperands())
493  if (srcOp.isVcc())
494  return true;
495 
496  return _staticInst->readsVCC();
497 }
498 
499 bool
501 {
502  for (const auto& dstOp : _staticInst->dstOperands())
503  if (dstOp.isVcc())
504  return true;
505 
506  return _staticInst->writesVCC();
507 }
508 
509 bool
511 {
512  return _staticInst->readsMode();
513 }
514 
515 bool
517 {
518  return _staticInst->writesMode();
519 }
520 
521 bool
523 {
524  return _staticInst->readsEXEC();
525 }
526 
527 bool
529 {
530  return _staticInst->writesEXEC();
531 }
532 
533 bool
535 {
536  return _staticInst->ignoreExec();
537 }
538 
539 bool
541 {
542  for (const auto& dstOp : _staticInst->dstOperands())
543  if (dstOp.isExec())
544  return true;
545 
546  return _staticInst->writesEXEC();
547 }
548 
549 bool
551 {
552  for (const auto& srcOp : _staticInst->srcOperands())
553  if (srcOp.isExec())
554  return true;
555 
556  return _staticInst->readsEXEC();
557 }
558 
559 bool
561 {
562  for (const auto& dstScalarOp : dstScalarRegOperands())
563  if (dstScalarOp.isFlatScratch())
564  return true;
565 
566  return false;
567 }
568 
569 bool
571 {
572  for (const auto& srcScalarOp : srcScalarRegOperands())
573  if (srcScalarOp.isFlatScratch())
574  return true;
575 
576  return false;
577 }
578 
579 bool
581 {
582  return _staticInst->isAtomicAnd();
583 }
584 
585 bool
587 {
588  return _staticInst->isAtomicOr();
589 }
590 
591 bool
593 {
594  return _staticInst->isAtomicXor();
595 }
596 
597 bool
599 {
600  return _staticInst->isAtomicCAS();
601 }
602 
604 {
605  return _staticInst->isAtomicExch();
606 }
607 
608 bool
610 {
611  return _staticInst->isAtomicAdd();
612 }
613 
614 bool
616 {
617  return _staticInst->isAtomicSub();
618 }
619 
620 bool
622 {
623  return _staticInst->isAtomicInc();
624 }
625 
626 bool
628 {
629  return _staticInst->isAtomicDec();
630 }
631 
632 bool
634 {
635  return _staticInst->isAtomicMax();
636 }
637 
638 bool
640 {
641  return _staticInst->isAtomicMin();
642 }
643 
644 bool
646 {
647  return _staticInst->isArgLoad();
648 }
649 
650 bool
652 {
653  return _staticInst->isGlobalMem();
654 }
655 
656 bool
658 {
659  return _staticInst->isLocalMem();
660 }
661 
662 bool
664 {
665  return _staticInst->isArgSeg();
666 }
667 
668 bool
670 {
671  return _staticInst->isGlobalSeg();
672 }
673 
674 bool
676 {
677  return _staticInst->isGroupSeg();
678 }
679 
680 bool
682 {
683  return _staticInst->isKernArgSeg();
684 }
685 
686 bool
688 {
689  return _staticInst->isPrivateSeg();
690 }
691 
692 bool
694 {
695  return _staticInst->isReadOnlySeg();
696 }
697 
698 bool
700 {
701  return _staticInst->isSpillSeg();
702 }
703 
704 bool
706 {
708 }
709 
710 bool
712 {
713  return _staticInst->isSystemCoherent();
714 }
715 
716 bool
718 {
719  return _staticInst->isF16();
720 }
721 
722 bool
724 {
725  return _staticInst->isF32();
726 }
727 
728 bool
730 {
731  return _staticInst->isF64();
732 }
733 
734 bool
736 {
737  return _staticInst->isFMA();
738 }
739 
740 bool
742 {
743  return _staticInst->isMAC();
744 }
745 
746 bool
748 {
749  return _staticInst->isMAD();
750 }
751 
752 void
754 {
755  assert(mask.any());
756  // find the segment of the first active address, after
757  // that we check that all other active addresses also
758  // fall within the same APE
759  for (int lane = 0; lane < computeUnit()->wfSize(); ++lane) {
760  if (mask[lane]) {
761  if (computeUnit()->shader->isLdsApe(addr[lane])) {
762  // group segment
763  staticInstruction()->executed_as = enums::SC_GROUP;
764  break;
765  } else if (computeUnit()->shader->isScratchApe(addr[lane])) {
766  // private segment
767  staticInstruction()->executed_as = enums::SC_PRIVATE;
768  break;
769  } else if (computeUnit()->shader->isGpuVmApe(addr[lane])) {
770  // we won't support GPUVM
771  fatal("flat access is in GPUVM APE\n");
772  } else if (bits(addr[lane], 63, 47) != 0x1FFFF &&
773  bits(addr[lane], 63, 47)) {
774  // we are in the "hole", this is a memory violation
775  fatal("flat access at addr %#x has a memory violation\n",
776  addr[lane]);
777  } else {
778  // global memory segment
779  staticInstruction()->executed_as = enums::SC_GLOBAL;
780  break;
781  }
782  }
783  }
784 
785  // we should have found the segment
786  assert(executedAs() != enums::SC_NONE);
787 
788  // flat accesses should not straddle multiple APEs so we
789  // must check that all addresses fall within the same APE
790  if (executedAs() == enums::SC_GROUP) {
791  for (int lane = 0; lane < computeUnit()->wfSize(); ++lane) {
792  if (mask[lane]) {
793  // if the first valid addr we found above was LDS,
794  // all the rest should be
795  assert(computeUnit()->shader->isLdsApe(addr[lane]));
796  }
797  }
798  } else if (executedAs() == enums::SC_PRIVATE) {
799  for (int lane = 0; lane < computeUnit()->wfSize(); ++lane) {
800  if (mask[lane]) {
801  // if the first valid addr we found above was private,
802  // all the rest should be
803  assert(computeUnit()->shader->isScratchApe(addr[lane]));
804  }
805  }
806  } else {
807  for (int lane = 0; lane < computeUnit()->wfSize(); ++lane) {
808  if (mask[lane]) {
809  // if the first valid addr we found above was global,
810  // all the rest should be. because we don't have an
811  // explicit range of the global segment, we just make
812  // sure that the address fall in no other APE and that
813  // it is not a memory violation
814  assert(!computeUnit()->shader->isLdsApe(addr[lane]));
815  assert(!computeUnit()->shader->isScratchApe(addr[lane]));
816  assert(!computeUnit()->shader->isGpuVmApe(addr[lane]));
817  assert(!(bits(addr[lane], 63, 47) != 0x1FFFF
818  && bits(addr[lane], 63, 47)));
819  }
820  }
821  }
822 }
823 
824 void
826 {
828 
829 
830  // Now that we know the aperature, do the following:
831  // 1. Transform the flat address to its segmented equivalent.
832  // 2. Set the execUnitId based an the aperture check.
833  // 3. Decrement any extra resources that were reserved. Other
834  // resources are released as normal, below.
835  if (executedAs() == enums::SC_GLOBAL) {
836  // no transormation for global segment
838  if (isLoad()) {
840  } else if (isStore()) {
842  } else if (isAtomic() || isMemSync()) {
845  } else {
846  panic("Invalid memory operation!\n");
847  }
848  } else if (executedAs() == enums::SC_GROUP) {
849  for (int lane = 0; lane < wavefront()->computeUnit->wfSize(); ++lane) {
850  if (mask[lane]) {
851  // flat address calculation goes here.
852  // addr[lane] = segmented address
853  addr[lane] = addr[lane] -
855  assert(addr[lane] <
857  }
858  }
861  if (isLoad()) {
863  } else if (isStore()) {
865  } else if (isAtomic() || isMemSync()) {
868  } else {
869  panic("Invalid memory operation!\n");
870  }
871  } else if (executedAs() == enums::SC_PRIVATE) {
901  uint32_t numSgprs = wavefront()->maxSgprs;
902  uint32_t physSgprIdx =
904  numSgprs - 3);
905  uint32_t offset =
906  wavefront()->computeUnit->srf[simdId]->read(physSgprIdx);
907  physSgprIdx =
909  numSgprs - 4);
910  uint32_t size =
911  wavefront()->computeUnit->srf[simdId]->read(physSgprIdx);
912  for (int lane = 0; lane < wavefront()->computeUnit->wfSize(); ++lane) {
913  if (mask[lane]) {
914  addr[lane] = addr[lane] + lane * size + offset +
917  }
918  }
921  if (isLoad()) {
923  } else if (isStore()) {
925  } else if (isAtomic() || isMemSync()) {
928  } else {
929  panic("Invalid memory operation!\n");
930  }
931  } else {
932  for (int lane = 0; lane < wavefront()->computeUnit->wfSize(); ++lane) {
933  if (mask[lane]) {
934  panic("flat addr %#llx maps to bad segment %d\n",
935  addr[lane], executedAs());
936  }
937  }
938  }
939 }
940 
943 {
944  return _staticInst->srcLiteral();
945 }
946 
947 void
949 {
950  if (_staticInst->isLocalMem()) {
951  // access to LDS (shared) memory
953  } else if (_staticInst->isFlat()) {
955  } else {
956  // access to global memory
957 
958  // update PageDivergence histogram
959  int number_pages_touched = cu->pagesTouched.size();
960  assert(number_pages_touched);
961  cu->stats.pageDivergenceDist.sample(number_pages_touched);
962 
964 
965  for (auto it : cu->pagesTouched) {
966  // see if this page has been touched before. if not, this also
967  // inserts the page into the table.
968  ret = cu->pageAccesses
969  .insert(ComputeUnit::pageDataStruct::value_type(it.first,
970  std::make_pair(1, it.second)));
971 
972  // if yes, then update the stats
973  if (!ret.second) {
974  ret.first->second.first++;
975  ret.first->second.second += it.second;
976  }
977  }
978 
979  cu->pagesTouched.clear();
980 
981  // total number of memory instructions (dynamic)
982  // Atomics are counted as a single memory instruction.
983  // this is # memory instructions per wavefronts, not per workitem
985  }
986 }
987 
988 void
989 GPUDynInst::profileRoundTripTime(Tick currentTime, int hopId)
990 {
991  // Only take the first measurement in the case of coalescing
992  if (roundTripTime.size() > hopId)
993  return;
994 
995  roundTripTime.push_back(currentTime);
996 }
997 
998 void
1000 {
1001  if (lineAddressTime.count(addr)) {
1002  if (lineAddressTime[addr].size() > hopId) {
1003  return;
1004  }
1005 
1006  lineAddressTime[addr].push_back(currentTime);
1007  } else if (hopId == 0) {
1008  auto addressTimeVec = std::vector<Tick> { currentTime };
1009  lineAddressTime.insert(std::make_pair(addr, addressTimeVec));
1010  }
1011 }
1012 
1013 } // namespace gem5
gem5::GPUStaticInst::initDynOperandInfo
void initDynOperandInfo(Wavefront *wf, ComputeUnit *cu)
Definition: gpu_static_inst.cc:58
gem5::GPUStaticInst::isReturn
bool isReturn() const
Definition: gpu_static_inst.hh:112
gem5::GPUDynInst::wfSlotId
int wfSlotId
Definition: gpu_dyn_inst.hh:196
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:190
gem5::ArmISA::NumVecElemPerVecReg
constexpr unsigned NumVecElemPerVecReg
Definition: vec.hh:58
gem5::GPUStaticInst::isAtomicMin
bool isAtomicMin() const
Definition: gpu_static_inst.hh:168
gem5::GPUStaticInst::isDPPInst
bool isDPPInst() const
Definition: gpu_static_inst.hh:116
gem5::GPUDynInst::isMAD
bool isMAD() const
Definition: gpu_dyn_inst.cc:747
gem5::GPUDynInst::hasDestinationSgpr
bool hasDestinationSgpr() const
Definition: gpu_dyn_inst.cc:254
gem5::GPUDynInst::tlbHitLevel
std::vector< int > tlbHitLevel
Definition: gpu_dyn_inst.hh:460
gem5::GPUStaticInst::isAtomicInc
bool isAtomicInc() const
Definition: gpu_static_inst.hh:165
gem5::GPUDynInst::writesFlatScratch
bool writesFlatScratch() const
Definition: gpu_dyn_inst.cc:560
gem5::GPUStaticInst::numSrcVecOperands
int numSrcVecOperands()
Definition: gpu_static_inst.cc:111
gem5::GPUDynInst::isAtomic
bool isAtomic() const
Definition: gpu_dyn_inst.cc:448
gem5::GPUDynInst::doApertureCheck
void doApertureCheck(const VectorMask &mask)
Definition: gpu_dyn_inst.cc:753
gem5::GPUDynInst::wfDynId
int wfDynId
Definition: gpu_dyn_inst.hh:188
gem5::GPUStaticInst::isMAD
bool isMAD() const
Definition: gpu_static_inst.hh:219
gem5::GPUDynInst::isAtomicDec
bool isAtomicDec() const
Definition: gpu_dyn_inst.cc:627
gem5::GPUDynInst::isCondBranch
bool isCondBranch() const
Definition: gpu_dyn_inst.cc:340
gem5::GPUDynInst::isLoad
bool isLoad() const
Definition: gpu_dyn_inst.cc:436
gem5::GPUDynInst::isKernelLaunch
bool isKernelLaunch() const
Definition: gpu_dyn_inst.cc:358
gem5::GPUStaticInst::numSrcRegOperands
virtual int numSrcRegOperands()=0
gem5::GPUDynInst::isAtomicXor
bool isAtomicXor() const
Definition: gpu_dyn_inst.cc:592
gem5::LdsState::getAddrRange
AddrRange getAddrRange() const
Definition: lds_state.hh:458
gem5::GPUDynInst::roundTripTime
std::vector< Tick > roundTripTime
Definition: gpu_dyn_inst.hh:495
shader.hh
gem5::GPUStaticInst::isAtomicMax
bool isAtomicMax() const
Definition: gpu_static_inst.hh:167
gem5::GPUStaticInst::isAtomicExch
bool isAtomicExch() const
Definition: gpu_static_inst.hh:162
gem5::GPUStaticInst::isNop
bool isNop() const
Definition: gpu_static_inst.hh:111
gem5::GPUDynInst::isKernArgSeg
bool isKernArgSeg() const
Definition: gpu_dyn_inst.cc:681
gem5::Wavefront::flatLmUnitId
int flatLmUnitId
Definition: wavefront.hh:103
gem5::GPUStaticInst::isFlat
bool isFlat() const
Definition: gpu_static_inst.hh:131
gem5::GPUStaticInst::writesEXEC
bool writesEXEC() const
Definition: gpu_static_inst.hh:153
gem5::ComputeUnit::srf
std::vector< ScalarRegisterFile * > srf
Definition: compute_unit.hh:297
gem5::GPUStaticInst::disassemble
const std::string & disassemble()
Definition: gpu_static_inst.cc:47
gem5::Wavefront::maxSgprs
uint32_t maxSgprs
Definition: wavefront.hh:133
gem5::GPUDynInst::seqNum
InstSeqNum seqNum() const
Definition: gpu_dyn_inst.cc:280
gem5::GPUDynInst::_seqNum
const InstSeqNum _seqNum
Definition: gpu_dyn_inst.hh:485
gem5::GPUDynInst::readsExec
bool readsExec() const
Definition: gpu_dyn_inst.cc:522
gem5::GPUStaticInst::isScalar
bool isScalar() const
Definition: gpu_static_inst.hh:145
gem5::Shader::getScratchBase
Addr getScratchBase()
Definition: shader.hh:156
gem5::GPUDynInst::isOpcode
bool isOpcode(const std::string &opcodeStr) const
Definition: gpu_dyn_inst.cc:268
gem5::GPUDynInst::readsMode
bool readsMode() const
Definition: gpu_dyn_inst.cc:510
gem5::GPUDynInst::readsSCC
bool readsSCC() const
Definition: gpu_dyn_inst.cc:478
gem5::GPUDynInst::isFMA
bool isFMA() const
Definition: gpu_dyn_inst.cc:735
gem5::Wavefront
Definition: wavefront.hh:60
gem5::GPUDynInst::_staticInst
GPUStaticInst * _staticInst
Definition: gpu_dyn_inst.hh:484
gem5::GPUDynInst::profileRoundTripTime
void profileRoundTripTime(Tick currentTime, int hopId)
Definition: gpu_dyn_inst.cc:989
gem5::ComputeUnit::ComputeUnitStats::dynamicGMemInstrCnt
statistics::Scalar dynamicGMemInstrCnt
Definition: compute_unit.hh:1074
gem5::GPUDynInst::isArgSeg
bool isArgSeg() const
Definition: gpu_dyn_inst.cc:663
gem5::GPUDynInst::kern_id
int kern_id
Definition: gpu_dyn_inst.hh:190
gem5::GPUStaticInst::isAtomicNoRet
bool isAtomicNoRet() const
Definition: gpu_static_inst.hh:142
gem5::GPUStaticInst::isGroupSeg
bool isGroupSeg() const
Definition: gpu_static_inst.hh:192
gem5::GPUStaticInst::initiateAcc
virtual void initiateAcc(GPUDynInstPtr gpuDynInst)
Definition: gpu_static_inst.hh:225
gem5::ComputeUnit::pagesTouched
std::map< Addr, int > pagesTouched
Definition: compute_unit.hh:378
gpu_static_inst.hh
gem5::GPUDynInst::scalar_data
uint8_t * scalar_data
Definition: gpu_dyn_inst.hh:177
gem5::GPUDynInst::d_data
uint8_t * d_data
Definition: gpu_dyn_inst.hh:175
gem5::VectorMask
std::bitset< std::numeric_limits< unsigned long long >::digits > VectorMask
Definition: misc.hh:45
gem5::Wavefront::kernId
int kernId
Definition: wavefront.hh:97
gem5::GPUDynInst::srcVecRegOperands
const std::vector< OperandInfo > & srcVecRegOperands() const
Definition: gpu_dyn_inst.cc:112
gem5::ComputeUnit::stats
gem5::ComputeUnit::ComputeUnitStats stats
gem5::GPUDynInst::isBarrier
bool isBarrier() const
Definition: gpu_dyn_inst.cc:406
gem5::GPUStaticInst::isWaitcnt
bool isWaitcnt() const
Definition: gpu_static_inst.hh:125
gem5::GPUDynInst::maxSrcVecRegOperandSize
int maxSrcVecRegOperandSize()
Definition: gpu_dyn_inst.cc:160
gem5::GPUStaticInst::writesVCC
bool writesVCC() const
Definition: gpu_static_inst.hh:149
gem5::GPUDynInst::readsVCC
bool readsVCC() const
Definition: gpu_dyn_inst.cc:490
gem5::GPUDynInst::writesExec
bool writesExec() const
Definition: gpu_dyn_inst.cc:528
gem5::GPUStaticInst::executed_as
enums::StorageClassType executed_as
Definition: gpu_static_inst.hh:242
gem5::GPUDynInst::numSrcScalarRegOperands
int numSrcScalarRegOperands() const
Definition: gpu_dyn_inst.cc:186
gem5::Wavefront::pc
Addr pc() const
Definition: wavefront.cc:1363
gem5::GPUStaticInst::srcScalarRegOperands
const std::vector< OperandInfo > & srcScalarRegOperands() const
Definition: gpu_static_inst.hh:281
gem5::GPUDynInst::isGroupSeg
bool isGroupSeg() const
Definition: gpu_dyn_inst.cc:675
gem5::GPUDynInst::numSrcScalarDWords
int numSrcScalarDWords()
Definition: gpu_dyn_inst.cc:212
std::vector
STL vector class.
Definition: stl.hh:37
gem5::GPUDynInst::isAtomicInc
bool isAtomicInc() const
Definition: gpu_dyn_inst.cc:621
gem5::GPUStaticInst::isMemSync
bool isMemSync() const
Definition: gpu_static_inst.hh:129
gem5::GPUStaticInst::dstVecRegOperands
const std::vector< OperandInfo > & dstVecRegOperands() const
Definition: gpu_static_inst.hh:275
gem5::GPUStaticInst::isFlatGlobal
bool isFlatGlobal() const
Definition: gpu_static_inst.hh:132
gem5::GPUStaticInst::isSDWAInst
bool isSDWAInst() const
Definition: gpu_static_inst.hh:115
gem5::GPUDynInst::isAtomicAnd
bool isAtomicAnd() const
Definition: gpu_dyn_inst.cc:580
gem5::GPUDynInst::initiateAcc
void initiateAcc(GPUDynInstPtr gpuDynInst)
Definition: gpu_dyn_inst.cc:305
gem5::GPUDynInst::numSrcVecRegOperands
int numSrcVecRegOperands() const
Definition: gpu_dyn_inst.cc:148
gem5::GPUStaticInst::isFMA
bool isFMA() const
Definition: gpu_static_inst.hh:217
gem5::GPUStaticInst
Definition: gpu_static_inst.hh:61
gem5::ComputeUnit::getLds
LdsState & getLds() const
Definition: compute_unit.hh:475
gem5::GPUDynInst::disassemble
const std::string & disassemble() const
Definition: gpu_dyn_inst.cc:274
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::ComputeUnit::shader
Shader * shader
Definition: compute_unit.hh:353
gem5::GPUStaticInst::isGloballyCoherent
bool isGloballyCoherent() const
Coherence domain of a memory instruction.
Definition: gpu_static_inst.hh:208
gem5::GPUDynInst::isAtomicRet
bool isAtomicRet() const
Definition: gpu_dyn_inst.cc:460
gem5::ComputeUnit::cu_id
int cu_id
Definition: compute_unit.hh:292
gem5::statistics::DistBase::sample
void sample(const U &v, int n=1)
Add a value to the distribtion n times.
Definition: statistics.hh:1328
gem5::GPUStaticInst::numDstVecOperands
int numDstVecOperands()
Definition: gpu_static_inst.cc:117
gem5::GPUDynInst::isAtomicNoRet
bool isAtomicNoRet() const
Definition: gpu_dyn_inst.cc:454
gem5::ComputeUnit::ComputeUnitStats::dynamicFlatMemInstrCnt
statistics::Scalar dynamicFlatMemInstrCnt
Definition: compute_unit.hh:1076
wavefront.hh
gem5::GPUDynInst::profileLineAddressTime
void profileLineAddressTime(Addr addr, Tick currentTime, int hopId)
Definition: gpu_dyn_inst.cc:999
gem5::mask
constexpr uint64_t mask(unsigned nbits)
Generate a 64-bit mask of 'nbits' 1s, right justified.
Definition: bitfield.hh:63
gem5::GPUStaticInst::isStore
bool isStore() const
Definition: gpu_static_inst.hh:134
gem5::GPUStaticInst::isALU
bool isALU() const
Definition: gpu_static_inst.hh:108
gem5::Wavefront::flatGmUnitId
int flatGmUnitId
Definition: wavefront.hh:104
gem5::GPUStaticInst::isAtomicRet
bool isAtomicRet() const
Definition: gpu_static_inst.hh:143
gem5::Wavefront::wrLmReqsInPipe
int wrLmReqsInPipe
Definition: wavefront.hh:186
gem5::GPUExecContext::computeUnit
ComputeUnit * computeUnit()
Definition: gpu_exec_context.cc:44
gem5::Wavefront::wgId
uint32_t wgId
Definition: wavefront.hh:160
gem5::GPUStaticInst::opcode
const std::string & opcode() const
Definition: gpu_static_inst.hh:263
gem5::GPUStaticInst::isEndOfKernel
bool isEndOfKernel() const
Definition: gpu_static_inst.hh:113
gem5::RegisterManager::mapSgpr
int mapSgpr(Wavefront *w, int sgprIndex)
Definition: register_manager.cc:102
gem5::GPUDynInst::isSleep
bool isSleep() const
Definition: gpu_dyn_inst.cc:400
gem5::GPUDynInst::time
Tick time
Definition: gpu_dyn_inst.hh:200
gem5::GPUDynInst::hasDestinationVgpr
bool hasDestinationVgpr() const
Definition: gpu_dyn_inst.cc:242
gem5::ComputeUnit
Definition: compute_unit.hh:201
gem5::ComputeUnit::pageAccesses
pageDataStruct pageAccesses
Definition: compute_unit.hh:486
gem5::GPUStaticInst::readsMode
bool readsMode() const
Definition: gpu_static_inst.hh:154
gem5::GPUDynInst::isVector
bool isVector() const
Definition: gpu_dyn_inst.cc:466
gem5::GPUDynInst::isGloballyCoherent
bool isGloballyCoherent() const
Definition: gpu_dyn_inst.cc:705
gem5::GPUStaticInst::isBarrier
bool isBarrier() const
Definition: gpu_static_inst.hh:128
gem5::GPUStaticInst::isF16
bool isF16() const
Definition: gpu_static_inst.hh:212
gem5::GPUDynInst::statusVector
std::vector< int > statusVector
Definition: gpu_dyn_inst.hh:458
gem5::GPUStaticInst::numDstScalarDWords
int numDstScalarDWords()
Definition: gpu_static_inst.cc:182
gem5::GPUDynInst::isMemSync
bool isMemSync() const
Definition: gpu_dyn_inst.cc:412
gem5::GPUStaticInst::isBranch
bool isBranch() const
Definition: gpu_static_inst.hh:109
gem5::GPUStaticInst::execute
virtual void execute(GPUDynInstPtr gpuDynInst)=0
gem5::GPUStaticInst::isAtomicSub
bool isAtomicSub() const
Definition: gpu_static_inst.hh:164
gem5::Wavefront::wrGmReqsInPipe
int wrGmReqsInPipe
Definition: wavefront.hh:187
gem5::GPUDynInst::GPUDynInst
GPUDynInst(ComputeUnit *_cu, Wavefront *_wf, GPUStaticInst *static_inst, uint64_t instSeqNum)
Definition: gpu_dyn_inst.cc:44
gem5::GPUDynInst::hasSourceVgpr
bool hasSourceVgpr() const
Definition: gpu_dyn_inst.cc:236
gem5::GPUStaticInst::maxOperandSize
int maxOperandSize()
Definition: gpu_static_inst.cc:197
gem5::GPUDynInst::isNop
bool isNop() const
Definition: gpu_dyn_inst.cc:346
gem5::GPUStaticInst::writesMode
bool writesMode() const
Definition: gpu_static_inst.hh:155
gem5::GPUStaticInst::getNumOperands
virtual int getNumOperands()=0
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::GPUDynInst::isUnconditionalJump
bool isUnconditionalJump() const
Definition: gpu_dyn_inst.cc:382
gem5::GPUStaticInst::srcLiteral
virtual TheGpuISA::ScalarRegU32 srcLiteral() const
Definition: gpu_static_inst.hh:78
gem5::GPUDynInst::dstScalarRegOperands
const std::vector< OperandInfo > & dstScalarRegOperands() const
Definition: gpu_dyn_inst.cc:130
gem5::Wavefront::rdLmReqsInPipe
int rdLmReqsInPipe
Definition: wavefront.hh:184
gem5::GPUDynInst::isAtomicMin
bool isAtomicMin() const
Definition: gpu_dyn_inst.cc:639
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::GPUDynInst::isAtomicOr
bool isAtomicOr() const
Definition: gpu_dyn_inst.cc:586
gem5::GPUStaticInst::numDstVecDWords
int numDstVecDWords()
Definition: gpu_static_inst.cc:139
gem5::GPUStaticInst::isAtomicDec
bool isAtomicDec() const
Definition: gpu_static_inst.hh:166
gem5::GPUStaticInst::srcVecRegOperands
const std::vector< OperandInfo > & srcVecRegOperands() const
Definition: gpu_static_inst.hh:269
gem5::GPUDynInst::numDstRegOperands
int numDstRegOperands()
Definition: gpu_dyn_inst.cc:142
gem5::GPUDynInst::resolveFlatSegment
void resolveFlatSegment(const VectorMask &mask)
Definition: gpu_dyn_inst.cc:825
gem5::GPUDynInst::addr
std::vector< Addr > addr
Definition: gpu_dyn_inst.hh:171
gem5::GPUDynInst::x_data
uint8_t * x_data
Definition: gpu_dyn_inst.hh:181
gem5::GPUDynInst::isFlatGlobal
bool isFlatGlobal() const
Definition: gpu_dyn_inst.cc:430
gem5::Wavefront::wfSlotId
const int wfSlotId
Definition: wavefront.hh:96
gem5::GPUDynInst::isMAC
bool isMAC() const
Definition: gpu_dyn_inst.cc:741
gem5::Wavefront::execUnitId
int execUnitId
Definition: wavefront.hh:102
gem5::ComputeUnit::registerManager
RegisterManager * registerManager
Definition: compute_unit.hh:278
gem5::GPUDynInst::isSDWAInst
bool isSDWAInst() const
Definition: gpu_dyn_inst.cc:364
gem5::GPUDynInst::writesMode
bool writesMode() const
Definition: gpu_dyn_inst.cc:516
gem5::GPUDynInst::cu_id
int cu_id
Definition: gpu_dyn_inst.hh:192
gem5::GPUDynInst::isSystemCoherent
bool isSystemCoherent() const
Definition: gpu_dyn_inst.cc:711
scalar_register_file.hh
gem5::GPUDynInst::getNumOperands
int getNumOperands() const
Definition: gpu_dyn_inst.cc:230
gpu_dyn_inst.hh
gem5::GPUDynInst::dstVecRegOperands
const std::vector< OperandInfo > & dstVecRegOperands() const
Definition: gpu_dyn_inst.cc:118
gem5::AddrRange::size
Addr size() const
Get the size of the address range.
Definition: addr_range.hh:326
gem5::GPUDynInst::numSrcRegOperands
int numSrcRegOperands()
Definition: gpu_dyn_inst.cc:136
gem5::GPUDynInst::staticInstruction
GPUStaticInst * staticInstruction()
Definition: gpu_dyn_inst.hh:214
gem5::GPUStaticInst::dstScalarRegOperands
const std::vector< OperandInfo > & dstScalarRegOperands() const
Definition: gpu_static_inst.hh:287
gem5::ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:144
gem5::GPUStaticInst::isMAC
bool isMAC() const
Definition: gpu_static_inst.hh:218
gem5::Shader::ldsApe
const ApertureRegister & ldsApe() const
Definition: shader.hh:119
gem5::GPUDynInst::pc
Addr pc()
Definition: gpu_dyn_inst.cc:286
gem5::GPUDynInst::isLocalMem
bool isLocalMem() const
Definition: gpu_dyn_inst.cc:657
gem5::GPUStaticInst::numDstScalarOperands
int numDstScalarOperands()
Definition: gpu_static_inst.cc:161
gem5::GPUDynInst::numDstScalarDWords
int numDstScalarDWords()
Definition: gpu_dyn_inst.cc:218
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::GPUStaticInst::isAtomicCAS
bool isAtomicCAS() const
Definition: gpu_static_inst.hh:161
gem5::GPUDynInst::~GPUDynInst
~GPUDynInst()
Definition: gpu_dyn_inst.cc:96
gem5::GPUDynInst::isDPPInst
bool isDPPInst() const
Definition: gpu_dyn_inst.cc:370
gem5::GPUDynInst::isF32
bool isF32() const
Definition: gpu_dyn_inst.cc:723
gem5::GPUStaticInst::isReadOnlySeg
bool isReadOnlySeg() const
Definition: gpu_static_inst.hh:195
std::pair
STL pair class.
Definition: stl.hh:58
gem5::GPUDynInst::maxSrcScalarRegOpSize
int maxSrcScalarRegOpSize
Definition: gpu_dyn_inst.hh:487
gem5::Wavefront::wfDynId
uint64_t wfDynId
Definition: wavefront.hh:226
gem5::Wavefront::computeUnit
ComputeUnit * computeUnit
Definition: wavefront.hh:106
gem5::GPUDynInst::writesVCC
bool writesVCC() const
Definition: gpu_dyn_inst.cc:500
gem5::GPUStaticInst::numSrcScalarDWords
int numSrcScalarDWords()
Definition: gpu_static_inst.cc:167
gem5::GPUDynInst::numDstScalarRegOperands
int numDstScalarRegOperands() const
Definition: gpu_dyn_inst.cc:192
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::GPUStaticInst::readsVCC
bool readsVCC() const
Definition: gpu_static_inst.hh:148
gem5::GPUDynInst::isStore
bool isStore() const
Definition: gpu_dyn_inst.cc:442
gem5::GPUStaticInst::isLoad
bool isLoad() const
Definition: gpu_static_inst.hh:133
gem5::GPUDynInst::ignoreExec
bool ignoreExec() const
Definition: gpu_dyn_inst.cc:534
gem5::Shader::isLdsApe
bool isLdsApe(Addr addr) const
Definition: shader.hh:139
gem5::GPUExecContext::wavefront
Wavefront * wavefront()
Definition: gpu_exec_context.cc:50
gem5::GPUStaticInst::srcOperands
const std::vector< OperandInfo > & srcOperands() const
Definition: gpu_static_inst.hh:265
gem5::GPUDynInstPtr
std::shared_ptr< GPUDynInst > GPUDynInstPtr
Definition: misc.hh:49
gem5::GPUStaticInst::isKernArgSeg
bool isKernArgSeg() const
Definition: gpu_static_inst.hh:193
gem5::GPUDynInst::isFlat
bool isFlat() const
Definition: gpu_dyn_inst.cc:424
gem5::ComputeUnit::wfSize
int wfSize() const
Definition: compute_unit.hh:394
gem5::Wavefront::decVMemInstsIssued
void decVMemInstsIssued()
Definition: wavefront.cc:1345
gem5::GPUStaticInst::dstOperands
const std::vector< OperandInfo > & dstOperands() const
Definition: gpu_static_inst.hh:266
gem5::Wavefront::rdGmReqsInPipe
int rdGmReqsInPipe
Definition: wavefront.hh:185
gem5::GPUDynInst::updateStats
void updateStats()
Definition: gpu_dyn_inst.cc:948
gem5::GPUStaticInst::isAtomicAdd
bool isAtomicAdd() const
Definition: gpu_static_inst.hh:163
gem5::GPUStaticInst::isUnconditionalJump
bool isUnconditionalJump() const
Definition: gpu_static_inst.hh:119
gem5::GPUStaticInst::isKernelLaunch
bool isKernelLaunch() const
Definition: gpu_static_inst.hh:114
gem5::GPUStaticInst::isF32
bool isF32() const
Definition: gpu_static_inst.hh:213
gem5::GPUExecContext
Definition: gpu_exec_context.hh:45
gem5::GPUDynInst::isSpillSeg
bool isSpillSeg() const
Definition: gpu_dyn_inst.cc:699
gem5::GPUStaticInst::isF64
bool isF64() const
Definition: gpu_static_inst.hh:214
gem5::ApertureRegister::base
Addr base
Definition: shader.hh:76
gem5::GPUDynInst::execute
void execute(GPUDynInstPtr gpuDynInst)
Definition: gpu_dyn_inst.cc:106
gem5::GPUDynInst::simdId
int simdId
Definition: gpu_dyn_inst.hh:186
gem5::Wavefront::decLGKMInstsIssued
void decLGKMInstsIssued()
Definition: wavefront.cc:1357
gem5::GPUStaticInst::writesSCC
bool writesSCC() const
Definition: gpu_static_inst.hh:147
gem5::GPUDynInst::isScalar
bool isScalar() const
Definition: gpu_dyn_inst.cc:472
gem5::GPUDynInst::isSpecialOp
bool isSpecialOp() const
Definition: gpu_dyn_inst.cc:388
gem5::GPUDynInst::readsFlatScratch
bool readsFlatScratch() const
Definition: gpu_dyn_inst.cc:570
gem5::GPUDynInst::readsExecMask
bool readsExecMask() const
Definition: gpu_dyn_inst.cc:550
gem5::GPUDynInst::isAtomicAdd
bool isAtomicAdd() const
Definition: gpu_dyn_inst.cc:609
gem5::GPUStaticInst::isSpillSeg
bool isSpillSeg() const
Definition: gpu_static_inst.hh:196
gem5::GPUDynInst::isGlobalSeg
bool isGlobalSeg() const
Definition: gpu_dyn_inst.cc:669
gem5::GPUDynInst::numDstVecRegOperands
int numDstVecRegOperands() const
Definition: gpu_dyn_inst.cc:154
gem5::GPUDynInst::completeAcc
void completeAcc(GPUDynInstPtr gpuDynInst)
Definition: gpu_dyn_inst.cc:314
gem5::GPUDynInst::isMemRef
bool isMemRef() const
Definition: gpu_dyn_inst.cc:418
gem5::GPUStaticInst::isSystemCoherent
bool isSystemCoherent() const
Definition: gpu_static_inst.hh:209
gem5::GPUDynInst::numDstVecDWords
int numDstVecDWords()
Definition: gpu_dyn_inst.cc:180
gem5::GPUStaticInst::isAtomicOr
bool isAtomicOr() const
Definition: gpu_static_inst.hh:159
gem5::GPUDynInst::isEndOfKernel
bool isEndOfKernel() const
Definition: gpu_dyn_inst.cc:352
gem5::GPUDynInst::isBranch
bool isBranch() const
Definition: gpu_dyn_inst.cc:334
gem5::GPUStaticInst::numSrcScalarOperands
int numSrcScalarOperands()
Definition: gpu_static_inst.cc:155
gem5::GPUDynInst::maxSrcVecRegOpSize
int maxSrcVecRegOpSize
Definition: gpu_dyn_inst.hh:486
gem5::GPUStaticInst::isGlobalMem
bool isGlobalMem() const
Definition: gpu_static_inst.hh:177
gem5::GPUDynInst::a_data
uint8_t * a_data
Definition: gpu_dyn_inst.hh:179
gem5::GPUDynInst::srcLiteral
TheGpuISA::ScalarRegU32 srcLiteral() const
Definition: gpu_dyn_inst.cc:942
gem5::GPUDynInst::isF16
bool isF16() const
Definition: gpu_dyn_inst.cc:717
gem5::GPUDynInst::lineAddressTime
std::map< Addr, std::vector< Tick > > lineAddressTime
Definition: gpu_dyn_inst.hh:499
gem5::GPUStaticInst::readsEXEC
bool readsEXEC() const
Definition: gpu_static_inst.hh:152
gem5::GPUDynInst::maxSrcScalarRegOperandSize
int maxSrcScalarRegOperandSize()
Definition: gpu_dyn_inst.cc:198
gem5::GPUDynInst::isArgLoad
bool isArgLoad() const
Definition: gpu_dyn_inst.cc:645
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::GPUStaticInst::isMemRef
bool isMemRef() const
Definition: gpu_static_inst.hh:130
gem5::GPUStaticInst::isAtomicXor
bool isAtomicXor() const
Definition: gpu_static_inst.hh:160
sc_core::SC_NONE
@ SC_NONE
Definition: sc_report.hh:50
gem5::GPUDynInst::isReadOnlySeg
bool isReadOnlySeg() const
Definition: gpu_dyn_inst.cc:693
gem5::GPUStaticInst::isAtomic
bool isAtomic() const
Definition: gpu_static_inst.hh:137
gem5::GPUStaticInst::isArgLoad
bool isArgLoad() const
Definition: gpu_static_inst.hh:171
gem5::ComputeUnit::ComputeUnitStats::pageDivergenceDist
statistics::Distribution pageDivergenceDist
Definition: compute_unit.hh:1072
gem5::GPUStaticInst::numSrcVecDWords
int numSrcVecDWords()
Definition: gpu_static_inst.cc:123
gem5::GPUDynInst::isAtomicMax
bool isAtomicMax() const
Definition: gpu_dyn_inst.cc:633
gem5::GPUDynInst::isPrivateSeg
bool isPrivateSeg() const
Definition: gpu_dyn_inst.cc:687
gem5::GPUStaticInst::isAtomicAnd
bool isAtomicAnd() const
Definition: gpu_static_inst.hh:158
gem5::GPUDynInst::wg_id
int wg_id
Definition: gpu_dyn_inst.hh:194
gem5::GPUDynInst::writesExecMask
bool writesExecMask() const
Definition: gpu_dyn_inst.cc:540
gem5::GPUStaticInst::readsSCC
bool readsSCC() const
Definition: gpu_static_inst.hh:146
gem5::GPUDynInst::hasSourceSgpr
bool hasSourceSgpr() const
Definition: gpu_dyn_inst.cc:248
gem5::GPUStaticInst::isArgSeg
bool isArgSeg() const
Definition: gpu_static_inst.hh:190
gem5::ComputeUnit::ComputeUnitStats::dynamicLMemInstrCnt
statistics::Scalar dynamicLMemInstrCnt
Definition: compute_unit.hh:1077
gem5::GPUStaticInst::initOperandInfo
virtual void initOperandInfo()=0
gem5::GPUDynInst::isAtomicCAS
bool isAtomicCAS() const
Definition: gpu_dyn_inst.cc:598
gem5::GPUStaticInst::completeAcc
virtual void completeAcc(GPUDynInstPtr gpuDynInst)
Definition: gpu_static_inst.hh:232
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::GPUDynInst::numSrcVecDWords
int numSrcVecDWords()
Definition: gpu_dyn_inst.cc:174
gem5::GPUDynInst::writesSCC
bool writesSCC() const
Definition: gpu_dyn_inst.cc:484
gem5::GPUExecContext::cu
ComputeUnit * cu
Definition: gpu_exec_context.hh:62
gem5::GPUDynInst::isWaitcnt
bool isWaitcnt() const
Definition: gpu_dyn_inst.cc:394
gem5::GPUDynInst::isAtomicExch
bool isAtomicExch() const
Definition: gpu_dyn_inst.cc:603
gem5::GPUDynInst::isF64
bool isF64() const
Definition: gpu_dyn_inst.cc:729
gem5::GPUStaticInst::isSpecialOp
bool isSpecialOp() const
Definition: gpu_static_inst.hh:124
gem5::GPUStaticInst::isPrivateSeg
bool isPrivateSeg() const
Definition: gpu_static_inst.hh:194
gem5::GPUDynInst::isAtomicSub
bool isAtomicSub() const
Definition: gpu_dyn_inst.cc:615
gem5::GPUStaticInst::ignoreExec
bool ignoreExec() const
Definition: gpu_static_inst.hh:156
gem5::GPUDynInst::isALU
bool isALU() const
accessor methods for the attributes of the underlying GPU static instruction
Definition: gpu_dyn_inst.cc:328
gem5::GPUStaticInst::isLocalMem
bool isLocalMem() const
Definition: gpu_static_inst.hh:185
gem5::GPUDynInst::exec_mask
VectorMask exec_mask
Definition: gpu_dyn_inst.hh:183
gem5::GPUStaticInst::numDstRegOperands
virtual int numDstRegOperands()=0
gem5::GPUDynInst::isReturn
bool isReturn() const
Definition: gpu_dyn_inst.cc:376
gem5::GPUDynInst::isGlobalMem
bool isGlobalMem() const
Definition: gpu_dyn_inst.cc:651
gem5::Gcn3ISA::ScalarRegU32
uint32_t ScalarRegU32
Definition: gpu_registers.hh:153
gem5::GPUStaticInst::isSleep
bool isSleep() const
Definition: gpu_static_inst.hh:126
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::GPUStaticInst::isGlobalSeg
bool isGlobalSeg() const
Definition: gpu_static_inst.hh:191
gem5::GPUDynInst::maxOperandSize
int maxOperandSize()
Definition: gpu_dyn_inst.cc:224
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::GPUDynInst::srcScalarRegOperands
const std::vector< OperandInfo > & srcScalarRegOperands() const
Definition: gpu_dyn_inst.cc:124
gem5::GPUStaticInst::isCondBranch
bool isCondBranch() const
Definition: gpu_static_inst.hh:110
gem5::GPUDynInst::executedAs
enums::StorageClassType executedAs()
Definition: gpu_dyn_inst.cc:298
gem5::Shader::getHiddenPrivateBase
Addr getHiddenPrivateBase()
Definition: shader.hh:162
gem5::Wavefront::simdId
const int simdId
Definition: wavefront.hh:99

Generated on Sat Jun 18 2022 08:12:26 for gem5 by doxygen 1.8.17