gem5  v21.1.0.2
rv_ctrl.cc
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37 
38 #include "dev/arm/rv_ctrl.hh"
39 
40 #include "base/trace.hh"
41 #include "debug/RVCTRL.hh"
42 #include "mem/packet.hh"
43 #include "mem/packet_access.hh"
45 #include "sim/system.hh"
46 #include "sim/voltage_domain.hh"
47 
48 namespace gem5
49 {
50 
52  : BasicPioDevice(p, 0xD4), flags(0), scData(0)
53 {
54 }
55 
56 Tick
58 {
59  assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
60  assert(pkt->getSize() == 4);
61  Addr daddr = pkt->getAddr() - pioAddr;
62 
63  switch(daddr) {
64  case ProcId0:
65  pkt->setLE(params().proc_id0);
66  break;
67  case ProcId1:
68  pkt->setLE(params().proc_id1);
69  break;
70  case Clock24:
71  Tick clk;
72  clk = sim_clock::as_float::MHz * curTick() * 24;
73  pkt->setLE((uint32_t)(clk));
74  break;
75  case Clock100:
76  Tick clk100;
77  clk100 = sim_clock::as_float::MHz * curTick() * 100;
78  pkt->setLE((uint32_t)(clk100));
79  break;
80  case Flash:
81  pkt->setLE<uint32_t>(0);
82  break;
83  case Clcd:
84  pkt->setLE<uint32_t>(0x00001F00);
85  break;
86  case Osc0:
87  pkt->setLE<uint32_t>(0x00012C5C);
88  break;
89  case Osc1:
90  pkt->setLE<uint32_t>(0x00002CC0);
91  break;
92  case Osc2:
93  pkt->setLE<uint32_t>(0x00002C75);
94  break;
95  case Osc3:
96  pkt->setLE<uint32_t>(0x00020211);
97  break;
98  case Osc4:
99  pkt->setLE<uint32_t>(0x00002C75);
100  break;
101  case Lock:
102  pkt->setLE<uint32_t>(sysLock);
103  break;
104  case Flags:
105  pkt->setLE<uint32_t>(flags);
106  break;
107  case IdReg:
108  pkt->setLE<uint32_t>(params().idreg);
109  break;
110  case CfgStat:
111  pkt->setLE<uint32_t>(1);
112  break;
113  case CfgData:
114  pkt->setLE<uint32_t>(scData);
115  DPRINTF(RVCTRL, "Read %#x from SCReg\n", scData);
116  break;
117  case CfgCtrl:
118  pkt->setLE<uint32_t>(0); // not busy
119  DPRINTF(RVCTRL, "Read 0 from CfgCtrl\n");
120  break;
121  default:
122  warn("Tried to read RealView I/O at offset %#x that doesn't exist\n",
123  daddr);
124  pkt->setLE<uint32_t>(0);
125  break;
126  }
127  pkt->makeAtomicResponse();
128  return pioDelay;
129 
130 }
131 
132 Tick
134 {
135  assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
136 
137  Addr daddr = pkt->getAddr() - pioAddr;
138  switch (daddr) {
139  case Flash:
140  case Clcd:
141  case Osc0:
142  case Osc1:
143  case Osc2:
144  case Osc3:
145  case Osc4:
146  break;
147  case Lock:
148  sysLock.lockVal = pkt->getLE<uint16_t>();
149  break;
150  case ResetCtl:
151  // Ignore writes to reset control
152  warn_once("Ignoring write to reset control\n");
153  break;
154  case Flags:
155  flags = pkt->getLE<uint32_t>();
156  break;
157  case FlagsClr:
158  flags = 0;
159  break;
160  case CfgData:
161  scData = pkt->getLE<uint32_t>();
162  break;
163  case CfgCtrl: {
164  // A request is being submitted to read/write the system control
165  // registers. See
166  // http://infocenter.arm.com/help/topic/com.arm.doc.dui0447h/CACDEFGH.html
167  CfgCtrlReg req = pkt->getLE<uint32_t>();
168  if (!req.start) {
169  DPRINTF(RVCTRL, "SCReg: write %#x to ctrl but not starting\n",
170  req);
171  break;
172  }
173 
174  auto it_dev(devices.find(req & CFG_CTRL_ADDR_MASK));
175  if (it_dev == devices.end()) {
176  warn_once("SCReg: Access to unknown device "
177  "dcc%d:site%d:pos%d:fn%d:dev%d\n",
178  req.dcc, req.site, req.pos, req.func, req.dev);
179  break;
180  }
181 
182  // Service the request as a read or write depending on the
183  // wr bit in the control register.
184  Device &dev(*it_dev->second);
185  if (req.wr) {
186  DPRINTF(RVCTRL, "SCReg: Writing %#x (ctrlWr %#x)\n",
187  scData, req);
188  dev.write(scData);
189 
190  } else {
191  scData = dev.read();
192  DPRINTF(RVCTRL, "SCReg: Reading %#x (ctrlRd %#x)\n",
193  scData, req);
194  }
195  } break;
196  case CfgStat: // Weird to write this
197  default:
198  warn("Tried to write RVIO at offset %#x (data %#x) that doesn't exist\n",
199  daddr, pkt->getLE<uint32_t>());
200  break;
201  }
202  pkt->makeAtomicResponse();
203  return pioDelay;
204 }
205 
206 void
208 {
210 }
211 
212 void
214 {
216 }
217 
218 void
219 RealViewCtrl::registerDevice(DeviceFunc func, uint8_t site, uint8_t pos,
220  uint8_t dcc, uint16_t dev,
221  Device *handler)
222 {
223  CfgCtrlReg addr = 0;
224  addr.func = func;
225  addr.site = site;
226  addr.pos = pos;
227  addr.dcc = dcc;
228  addr.dev = dev;
229 
230  if (devices.find(addr) != devices.end()) {
231  fatal("Platform device dcc%d:site%d:pos%d:fn%d:dev%d "
232  "already registered.",
233  addr.dcc, addr.site, addr.pos, addr.func, addr.dev);
234  }
235 
236  devices[addr] = handler;
237 }
238 
239 
240 RealViewOsc::RealViewOsc(const RealViewOscParams &p)
241  : ClockDomain(p, p.voltage_domain),
242  RealViewCtrl::Device(*p.parent, RealViewCtrl::FUNC_OSC,
243  p.site, p.position, p.dcc, p.device)
244 {
245  if (sim_clock::as_float::s / p.freq > UINT32_MAX) {
246  fatal("Oscillator frequency out of range: %f\n",
247  sim_clock::as_float::s / p.freq / 1E6);
248  }
249 
250  _clockPeriod = p.freq;
251 }
252 
253 void
255 {
256  // Tell dependent object to set their clock frequency
257  for (auto m : members)
258  m->updateClockPeriod();
259 }
260 
261 void
263 {
265 }
266 
267 void
269 {
271 }
272 
273 void
275 {
276  panic_if(clock_period == 0, "%s has a clock period of zero\n", name());
277 
278  // Align all members to the current tick
279  for (auto m : members)
280  m->updateClockPeriod();
281 
282  _clockPeriod = clock_period;
283 
284  // inform any derived clocks they need to updated their period
285  for (auto m : children)
286  m->updateClockPeriod();
287 }
288 
289 uint32_t
291 {
292  const uint32_t freq(sim_clock::as_float::s / _clockPeriod);
293  DPRINTF(RVCTRL, "Reading OSC frequency: %f MHz\n", freq / 1E6);
294  return freq;
295 }
296 
297 void
298 RealViewOsc::write(uint32_t freq)
299 {
300  DPRINTF(RVCTRL, "Setting new OSC frequency: %f MHz\n", freq / 1E6);
302 }
303 
304 uint32_t
306 {
307  // Temperature reported in uC
309  if (tm) {
310  double t = tm->getTemperature().toCelsius();
311  if (t < 0)
312  warn("Temperature below zero!\n");
313  return fmax(0, t) * 1000000;
314  }
315 
316  // Report a dummy 25 degrees temperature
317  return 25000000;
318 }
319 
320 } // namespace gem5
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:189
gem5::ClockDomain::members
std::vector< Clocked * > members
Pointers to members of this clock domain, so that when the clock period changes, we can update each m...
Definition: clock_domain.hh:96
gem5::RealViewCtrl::Clock24
@ Clock24
Definition: rv_ctrl.hh:114
gem5::BasicPioDevice::pioAddr
Addr pioAddr
Address that the device listens to.
Definition: io_device.hh:151
gem5::RealViewCtrl::scData
uint32_t scData
This register contains the result from a system control reg access.
Definition: rv_ctrl.hh:158
gem5::RealViewOsc::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: rv_ctrl.cc:262
warn
#define warn(...)
Definition: logging.hh:245
system.hh
voltage_domain.hh
gem5::RealViewCtrl::FlagsClr
@ FlagsClr
Definition: rv_ctrl.hh:104
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:575
warn_once
#define warn_once(...)
Definition: logging.hh:249
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::ThermalModel
Definition: thermal_model.hh:144
gem5::RealViewOsc::startup
void startup() override
startup() is the final initialization call before simulation.
Definition: rv_ctrl.cc:254
gem5::RealViewCtrl::site
Bitfield< 17, 16 > site
Definition: rv_ctrl.hh:138
gem5::RealViewOsc::write
void write(uint32_t freq) override
Definition: rv_ctrl.cc:298
thermal_model.hh
gem5::System::getThermalModel
ThermalModel * getThermalModel() const
The thermal model used for this system (if any).
Definition: system.hh:419
gem5::Packet::makeAtomicResponse
void makeAtomicResponse()
Definition: packet.hh:1043
gem5::RealViewCtrl::CfgStat
@ CfgStat
Definition: rv_ctrl.hh:121
gem5::RealViewCtrl::Clock100
@ Clock100
Definition: rv_ctrl.hh:100
gem5::RealViewCtrl::Osc0
@ Osc0
Definition: rv_ctrl.hh:94
packet.hh
gem5::RealViewCtrl::Osc4
@ Osc4
Definition: rv_ctrl.hh:98
gem5::PioDevice::Params
PioDeviceParams Params
Definition: io_device.hh:134
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
gem5::ClockDomain
The ClockDomain provides clock to group of clocked objects bundled under the same clock domain.
Definition: clock_domain.hh:71
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
rv_ctrl.hh
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::RealViewCtrl::Osc2
@ Osc2
Definition: rv_ctrl.hh:96
gem5::RealViewCtrl::func
Bitfield< 25, 20 > func
Definition: rv_ctrl.hh:139
gem5::BasicPioDevice::pioDelay
Tick pioDelay
Delay that the device experinces on an access.
Definition: io_device.hh:157
gem5::RealViewCtrl::Device
Definition: rv_ctrl.hh:73
gem5::RealViewCtrl::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: rv_ctrl.cc:207
gem5::RealViewOsc::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: rv_ctrl.cc:268
gem5::ArmISA::t
Bitfield< 5 > t
Definition: misc_types.hh:70
gem5::RealViewCtrl::IdReg
@ IdReg
Definition: rv_ctrl.hh:91
gem5::PowerISA::tm
Bitfield< 32 > tm
Definition: misc.hh:107
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::RealViewCtrl::dcc
Bitfield< 29, 26 > dcc
Definition: rv_ctrl.hh:140
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:568
gem5::RealViewCtrl::ProcId0
@ ProcId0
Definition: rv_ctrl.hh:117
packet_access.hh
gem5::RealViewOsc::read
uint32_t read() const override
Definition: rv_ctrl.cc:290
gem5::RealViewCtrl::pos
Bitfield< 15, 12 > pos
Definition: rv_ctrl.hh:137
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
gem5::RealViewCtrl::CfgData
@ CfgData
Definition: rv_ctrl.hh:119
gem5::RealViewCtrl::RealViewCtrl
RealViewCtrl(const Params &p)
The constructor for RealView just registers itself with the MMU.
Definition: rv_ctrl.cc:51
gem5::ArmISA::m
Bitfield< 0 > m
Definition: misc_types.hh:394
gem5::RealViewTemperatureSensor::read
uint32_t read() const override
Definition: rv_ctrl.cc:305
gem5::RealViewCtrl::Osc1
@ Osc1
Definition: rv_ctrl.hh:95
gem5::RealViewCtrl::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: rv_ctrl.cc:213
gem5::RealViewCtrl
Definition: rv_ctrl.hh:54
gem5::RealViewCtrl::Lock
@ Lock
Definition: rv_ctrl.hh:99
gem5::ClockDomain::_clockPeriod
Tick _clockPeriod
Pre-computed clock period in ticks.
Definition: clock_domain.hh:79
gem5::RealViewCtrl::CfgCtrl
@ CfgCtrl
Definition: rv_ctrl.hh:120
gem5::RealViewCtrl::dev
dev
Definition: rv_ctrl.hh:136
gem5::RealViewCtrl::ResetCtl
@ ResetCtl
Definition: rv_ctrl.hh:107
gem5::RealViewCtrl::Flags
@ Flags
Definition: rv_ctrl.hh:103
gem5::RealViewTemperatureSensor::system
System * system
The system this RV device belongs to.
Definition: rv_ctrl.hh:246
gem5::RealViewCtrl::Clcd
@ Clcd
Definition: rv_ctrl.hh:111
gem5::Packet::getLE
T getLE() const
Get the data in the packet byte swapped from little endian to host endian.
Definition: packet_access.hh:78
gem5::BasicPioDevice::pioSize
Addr pioSize
Size that the device's address range.
Definition: io_device.hh:154
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::RealViewCtrl::write
Tick write(PacketPtr pkt) override
All writes are simply ignored.
Definition: rv_ctrl.cc:133
gem5::RealViewCtrl::devices
std::map< uint32_t, Device * > devices
Definition: rv_ctrl.hh:192
trace.hh
gem5::Packet::setLE
void setLE(T v)
Set the value in the data pointer to v as little endian.
Definition: packet_access.hh:108
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:781
gem5::RealViewCtrl::flags
uint32_t flags
This register is used for smp booting.
Definition: rv_ctrl.hh:154
gem5::RealViewCtrl::sysLock
SysLockReg sysLock
Definition: rv_ctrl.hh:147
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ClockDomain::clockPeriod
Tick clockPeriod() const
Get the clock period.
Definition: clock_domain.hh:108
gem5::BasicPioDevice
Definition: io_device.hh:147
gem5::RealViewCtrl::registerDevice
void registerDevice(DeviceFunc func, uint8_t site, uint8_t pos, uint8_t dcc, uint16_t dev, Device *handler)
Definition: rv_ctrl.cc:219
gem5::RealViewCtrl::read
Tick read(PacketPtr pkt) override
Handle a read to the device.
Definition: rv_ctrl.cc:57
gem5::RealViewCtrl::Flash
@ Flash
Definition: rv_ctrl.hh:110
gem5::RealViewOsc::RealViewOsc
RealViewOsc(const RealViewOscParams &p)
Definition: rv_ctrl.cc:240
gem5::RealViewCtrl::Osc3
@ Osc3
Definition: rv_ctrl.hh:97
gem5::RealViewCtrl::ProcId1
@ ProcId1
Definition: rv_ctrl.hh:118
gem5::RealViewCtrl::DeviceFunc
DeviceFunc
Definition: rv_ctrl.hh:57
gem5::Packet::getSize
unsigned getSize() const
Definition: packet.hh:791
gem5::ClockDomain::children
std::vector< DerivedClockDomain * > children
Pointers to potential derived clock domains so we can propagate changes.
Definition: clock_domain.hh:90
gem5::sim_clock::as_float::MHz
double MHz
MHz.
Definition: core.cc:61
gem5::sim_clock::as_float::s
double s
These variables equal the number of ticks in the unit of time they're named after in a double.
Definition: core.cc:53
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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