gem5  v21.2.1.1
op_encodings.cc
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31 
33 
34 #include <iomanip>
35 
36 namespace gem5
37 {
38 
39 namespace VegaISA
40 {
41  // --- Inst_SOP2 base class methods ---
42 
43  Inst_SOP2::Inst_SOP2(InFmt_SOP2 *iFmt, const std::string &opcode)
45  {
46  setFlag(Scalar);
47 
48  // copy first instruction DWORD
49  instData = iFmt[0];
50  if (hasSecondDword(iFmt)) {
51  // copy second instruction DWORD into union
52  extData = ((MachInst)iFmt)[1];
53  _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
54  varSize = 4 + 4;
55  } else {
56  varSize = 4;
57  } // if
58  } // Inst_SOP2
59 
60  void
62  {
63  int opNum = 0;
64 
65  // Needed because can't take addr of bitfield
66  int reg = instData.SSRC0;
67  srcOps.emplace_back(reg, getOperandSize(opNum), true,
68  isScalarReg(instData.SSRC0), false, false);
69  opNum++;
70 
71  reg = instData.SSRC1;
72  srcOps.emplace_back(reg, getOperandSize(opNum), true,
73  isScalarReg(instData.SSRC1), false, false);
74  opNum++;
75 
76  reg = instData.SDST;
77  dstOps.emplace_back(reg, getOperandSize(opNum), false,
78  isScalarReg(instData.SDST), false, false);
79 
80  assert(srcOps.size() == numSrcRegOperands());
81  assert(dstOps.size() == numDstRegOperands());
82  }
83 
84  int
86  {
87  return varSize;
88  } // instSize
89 
90  bool
92  {
93  if (iFmt->SSRC0 == REG_SRC_LITERAL)
94  return true;
95 
96  if (iFmt->SSRC1 == REG_SRC_LITERAL)
97  return true;
98 
99  return false;
100  }
101 
102  void
104  {
105  std::stringstream dis_stream;
106  dis_stream << _opcode << " ";
107  dis_stream << opSelectorToRegSym(instData.SDST) << ", ";
108 
109  if (instData.SSRC0 == REG_SRC_LITERAL) {
110  dis_stream << "0x" << std::hex << std::setfill('0') << std::setw(8)
111  << _srcLiteral << ", ";
112  } else {
113  dis_stream << opSelectorToRegSym(instData.SSRC0) << ", ";
114  }
115 
116  if (instData.SSRC1 == REG_SRC_LITERAL) {
117  dis_stream << "0x" << std::hex << std::setfill('0') << std::setw(8)
118  << _srcLiteral;
119  } else {
120  dis_stream << opSelectorToRegSym(instData.SSRC1);
121  }
122 
123  disassembly = dis_stream.str();
124  }
125 
126  // --- Inst_SOPK base class methods ---
127 
128  Inst_SOPK::Inst_SOPK(InFmt_SOPK *iFmt, const std::string &opcode)
130  {
131  setFlag(Scalar);
132 
133  // copy first instruction DWORD
134  instData = iFmt[0];
135  if (hasSecondDword(iFmt)) {
136  // copy second instruction DWORD into union
137  extData = ((MachInst)iFmt)[1];
138  _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
139  varSize = 4 + 4;
140  } else {
141  varSize = 4;
142  } // if
143  } // Inst_SOPK
144 
146  {
147  } // ~Inst_SOPK
148 
149  void
151  {
152  int opNum = 0;
153 
154  // Needed because can't take addr of bitfield
155  int reg = instData.SDST;
156  if (numSrcRegOperands() == getNumOperands()) {
157  srcOps.emplace_back(reg, getOperandSize(opNum), true,
158  isScalarReg(reg), false, false);
159  opNum++;
160  }
161 
162  reg = instData.SIMM16;
163  srcOps.emplace_back(reg, getOperandSize(opNum), true,
164  false, false, true);
165  opNum++;
166 
167  if (numDstRegOperands()) {
168  reg = instData.SDST;
169  dstOps.emplace_back(reg, getOperandSize(opNum), false,
170  isScalarReg(reg), false, false);
171  }
172 
173  assert(srcOps.size() == numSrcRegOperands());
174  assert(dstOps.size() == numDstRegOperands());
175  }
176 
177  int
179  {
180  return varSize;
181  } // instSize
182 
183  bool
185  {
186  /*
187  SOPK can be a 64-bit instruction, i.e., have a second dword:
188  S_SETREG_IMM32_B32 writes some or all of the LSBs of a 32-bit
189  literal constant into a hardware register;
190  the way to detect such special case is to explicitly check the
191  opcode (20/0x14)
192  */
193  if (iFmt->OP == 0x14)
194  return true;
195 
196  return false;
197  }
198 
199 
200  void
202  {
203  std::stringstream dis_stream;
204  dis_stream << _opcode << " ";
205 
206  // S_SETREG_IMM32_B32 is a 64-bit instruction, using a
207  // 32-bit literal constant
208  if (instData.OP == 0x14) {
209  dis_stream << "0x" << std::hex << std::setfill('0')
210  << std::setw(8) << extData.imm_u32 << ", ";
211  } else {
212  dis_stream << opSelectorToRegSym(instData.SDST) << ", ";
213  }
214 
215  dis_stream << "0x" << std::hex << std::setfill('0') << std::setw(4)
216  << instData.SIMM16;
217 
218  disassembly = dis_stream.str();
219  }
220 
221  // --- Inst_SOP1 base class methods ---
222 
223  Inst_SOP1::Inst_SOP1(InFmt_SOP1 *iFmt, const std::string &opcode)
225  {
226  setFlag(Scalar);
227 
228  // copy first instruction DWORD
229  instData = iFmt[0];
230  if (hasSecondDword(iFmt)) {
231  // copy second instruction DWORD into union
232  extData = ((MachInst)iFmt)[1];
233  _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
234  varSize = 4 + 4;
235  } else {
236  varSize = 4;
237  } // if
238  } // Inst_SOP1
239 
241  {
242  } // ~Inst_SOP1
243 
244  void
246  {
247  int opNum = 0;
248 
249  // Needed because can't take addr of bitfield
250  int reg = instData.SSRC0;
251  if (instData.OP != 0x1C) {
252  srcOps.emplace_back(reg, getOperandSize(opNum), true,
253  isScalarReg(instData.SSRC0), false, false);
254  opNum++;
255  }
256 
257  reg = instData.SDST;
258  dstOps.emplace_back(reg, getOperandSize(opNum), false,
259  isScalarReg(instData.SDST), false, false);
260 
261  assert(srcOps.size() == numSrcRegOperands());
262  assert(dstOps.size() == numDstRegOperands());
263  }
264 
265  int
267  {
268  return varSize;
269  } // instSize
270 
271  bool
273  {
274  if (iFmt->SSRC0 == REG_SRC_LITERAL)
275  return true;
276 
277  return false;
278  }
279 
280  void
282  {
283  std::stringstream dis_stream;
284  dis_stream << _opcode << " ";
285  dis_stream << opSelectorToRegSym(instData.SDST) << ", ";
286 
287  if (instData.SSRC0 == REG_SRC_LITERAL) {
288  dis_stream << "0x" << std::hex << std::setfill('0') << std::setw(8)
289  << extData.imm_u32;
290  } else {
291  dis_stream << opSelectorToRegSym(instData.SSRC0);
292  }
293 
294  disassembly = dis_stream.str();
295  }
296 
297  // --- Inst_SOPC base class methods ---
298 
299  Inst_SOPC::Inst_SOPC(InFmt_SOPC *iFmt, const std::string &opcode)
301  {
302  setFlag(Scalar);
303 
304  // copy first instruction DWORD
305  instData = iFmt[0];
306  if (hasSecondDword(iFmt)) {
307  // copy second instruction DWORD into union
308  extData = ((MachInst)iFmt)[1];
309  _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
310  varSize = 4 + 4;
311  } else {
312  varSize = 4;
313  } // if
314  } // Inst_SOPC
315 
317  {
318  } // ~Inst_SOPC
319 
320  void
322  {
323  int opNum = 0;
324 
325  // Needed because can't take addr of bitfield
326  int reg = instData.SSRC0;
327  srcOps.emplace_back(reg, getOperandSize(opNum), true,
328  isScalarReg(instData.SSRC0), false, false);
329  opNum++;
330 
331  reg = instData.SSRC1;
332  srcOps.emplace_back(reg, getOperandSize(opNum), true,
333  isScalarReg(instData.SSRC1), false, false);
334 
335  }
336 
337  int
339  {
340  return varSize;
341  } // instSize
342 
343  bool
345  {
346  if (iFmt->SSRC0 == REG_SRC_LITERAL)
347  return true;
348 
349  if (iFmt->SSRC1 == REG_SRC_LITERAL)
350  return true;
351 
352  return false;
353  }
354 
355  void
357  {
358  std::stringstream dis_stream;
359  dis_stream << _opcode << " ";
360 
361  if (instData.SSRC0 == REG_SRC_LITERAL) {
362  dis_stream << "0x" << std::hex << std::setfill('0') << std::setw(8)
363  << extData.imm_u32;
364  } else {
365  dis_stream << opSelectorToRegSym(instData.SSRC0) << ", ";
366  }
367 
368  if (instData.SSRC1 == REG_SRC_LITERAL) {
369  dis_stream << "0x" << std::hex << std::setfill('0') << std::setw(8)
370  << extData.imm_u32;
371  } else {
372  dis_stream << opSelectorToRegSym(instData.SSRC1);
373  }
374 
375  disassembly = dis_stream.str();
376  }
377 
378  // --- Inst_SOPP base class methods ---
379 
380  Inst_SOPP::Inst_SOPP(InFmt_SOPP *iFmt, const std::string &opcode)
382  {
383  setFlag(Scalar);
384 
385  // copy first instruction DWORD
386  instData = iFmt[0];
387  } // Inst_SOPP
388 
390  {
391  } // ~Inst_SOPP
392 
393  void
395  {
396  int opNum = 0;
397 
398 
399  if (numSrcRegOperands()) {
400  // Needed because can't take addr of bitfield
401  int reg = instData.SIMM16;
402  srcOps.emplace_back(reg, getOperandSize(opNum), true,
403  false, false, true);
404 
405  opNum++;
406 
407  if (readsVCC()) {
408  srcOps.emplace_back(REG_VCC_LO, getOperandSize(opNum), true,
409  true, false, false);
410  opNum++;
411  }
412  }
413  assert(srcOps.size() == numSrcRegOperands());
414  assert(dstOps.size() == numDstRegOperands());
415  }
416 
417  int
419  {
420  return 4;
421  } // instSize
422 
423  void
425  {
426  std::stringstream dis_stream;
427  dis_stream << _opcode;
428 
429  switch (instData.OP) {
430  case 8:
431  {
432  dis_stream << " ";
433  int dest = 4 * instData.SIMM16 + 4;
434  dis_stream << "label_" << std::hex << dest;
435  }
436  break;
437  case 12:
438  {
439  dis_stream << " ";
440 
441  int vm_cnt = 0;
442  int exp_cnt = 0;
443  int lgkm_cnt = 0;
444 
445  vm_cnt = bits<uint16_t>(instData.SIMM16, 3, 0);
446  exp_cnt = bits<uint16_t>(instData.SIMM16, 6, 4);
447  lgkm_cnt = bits<uint16_t>(instData.SIMM16, 11, 8);
448 
449  // if the counts are not maxed out, then we
450  // print out the count value
451  if (vm_cnt != 0xf) {
452  dis_stream << "vmcnt(" << vm_cnt << ")";
453  }
454 
455  if (lgkm_cnt != 0xf) {
456  if (vm_cnt != 0xf)
457  dis_stream << " & ";
458 
459  dis_stream << "lgkmcnt(" << lgkm_cnt << ")";
460  }
461 
462  if (exp_cnt != 0x7) {
463  if (vm_cnt != 0xf || lgkm_cnt != 0xf)
464  dis_stream << " & ";
465 
466  dis_stream << "expcnt(" << exp_cnt << ")";
467  }
468  }
469  break;
470  default:
471  break;
472  }
473 
474  disassembly = dis_stream.str();
475  }
476 
477  // --- Inst_SMEM base class methods ---
478 
479  Inst_SMEM::Inst_SMEM(InFmt_SMEM *iFmt, const std::string &opcode)
481  {
482  setFlag(Scalar);
483  setFlag(GlobalSegment);
484 
485  // copy first instruction DWORD
486  instData = iFmt[0];
487  // copy second instruction DWORD
488  extData = ((InFmt_SMEM_1 *)iFmt)[1];
489  _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
490 
491  if (instData.GLC)
492  setFlag(GloballyCoherent);
493  } // Inst_SMEM
494 
496  {
497  } // ~Inst_SMEM
498 
499  void
501  {
502  // Formats:
503  // 0 src + 0 dst
504  // 3 src + 0 dst
505  // 2 src + 1 dst
506  // 0 src + 1 dst
507  int opNum = 0;
508  // Needed because can't take addr of bitfield
509  int reg = 0;
510 
511  if (numSrcRegOperands()) {
512  reg = instData.SDATA;
513  if (numSrcRegOperands() == getNumOperands()) {
514  srcOps.emplace_back(reg, getOperandSize(opNum), true,
515  isScalarReg(reg), false, false);
516  opNum++;
517  }
518 
519  reg = instData.SBASE;
520  srcOps.emplace_back(reg, getOperandSize(opNum), true,
521  true, false, false);
522  opNum++;
523 
524  reg = extData.OFFSET;
525  if (instData.IMM) {
526  srcOps.emplace_back(reg, getOperandSize(opNum), true,
527  false, false, true);
528  } else {
529  srcOps.emplace_back(reg, getOperandSize(opNum), true,
530  isScalarReg(reg), false, false);
531  }
532  opNum++;
533  }
534 
535  if (numDstRegOperands()) {
536  reg = instData.SDATA;
537  dstOps.emplace_back(reg, getOperandSize(opNum), false,
538  isScalarReg(reg), false, false);
539  }
540 
541  assert(srcOps.size() == numSrcRegOperands());
542  assert(dstOps.size() == numDstRegOperands());
543  }
544 
545  int
547  {
548  return 8;
549  } // instSize
550 
551  void
553  {
554  std::stringstream dis_stream;
555  dis_stream << _opcode << " ";
556  if (numDstRegOperands()) {
557  if (getOperandSize(getNumOperands() - 1) > 4) {
558  dis_stream << "s[" << instData.SDATA << ":"
560  4 - 1 << "], ";
561  } else {
562  dis_stream << "s" << instData.SDATA << ", ";
563  }
564  }
565 
566  // SBASE has an implied LSB of 0, so we need
567  // to shift by one to get the actual value
568  dis_stream << "s[" << (instData.SBASE << 1) << ":"
569  << ((instData.SBASE << 1) + 1) << "], ";
570 
571  if (instData.IMM) {
572  // IMM == 1 implies OFFSET should be
573  // used as the offset
574  dis_stream << "0x" << std::hex << std::setfill('0') << std::setw(2)
575  << extData.OFFSET;
576  } else {
577  // IMM == 0 implies OFFSET should be
578  // used to specify SGRP in which the
579  // offset is held
580  dis_stream << "s" << extData.OFFSET;
581  }
582 
583  disassembly = dis_stream.str();
584  }
585 
586  // --- Inst_VOP2 base class methods ---
587 
588  Inst_VOP2::Inst_VOP2(InFmt_VOP2 *iFmt, const std::string &opcode)
590  {
591  // copy first instruction DWORD
592  instData = iFmt[0];
593  if (hasSecondDword(iFmt)) {
594  // copy second instruction DWORD into union
595  extData = ((MachInst)iFmt)[1];
596  _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
597  varSize = 4 + 4;
598  if (iFmt->SRC0 == REG_SRC_DPP) {
599  setFlag(IsDPP);
600  } else if (iFmt->SRC0 == REG_SRC_SWDA) {
601  setFlag(IsSDWA);
602  }
603  } else {
604  varSize = 4;
605  } // if
606  } // Inst_VOP2
607 
609  {
610  } // ~Inst_VOP2
611 
612  void
614  {
615  int opNum = 0;
616 
617  // Needed because can't take addr of bitfield
618  int reg = instData.SRC0;
619  srcOps.emplace_back(reg, getOperandSize(opNum), true,
620  isScalarReg(reg), isVectorReg(reg), false);
621  opNum++;
622 
623  reg = instData.VSRC1;
624  srcOps.emplace_back(reg, getOperandSize(opNum), true,
625  false, true, false);
626  opNum++;
627 
628  // VCC read
629  if (readsVCC()) {
630  srcOps.emplace_back(REG_VCC_LO, getOperandSize(opNum), true,
631  true, false, false);
632  opNum++;
633  }
634 
635  // VDST
636  reg = instData.VDST;
637  dstOps.emplace_back(reg, getOperandSize(opNum), false,
638  false, true, false);
639  opNum++;
640 
641  // VCC write
642  if (writesVCC()) {
643  dstOps.emplace_back(REG_VCC_LO, getOperandSize(opNum), false,
644  true, false, false);
645  }
646 
647  assert(srcOps.size() == numSrcRegOperands());
648  assert(dstOps.size() == numDstRegOperands());
649  }
650 
651  int
653  {
654  return varSize;
655  } // instSize
656 
657  bool
659  {
660  /*
661  There are a few cases where VOP2 instructions have a second dword:
662 
663  1. SRC0 is a literal
664  2. SRC0 is being used to add a data parallel primitive (DPP)
665  operation to the instruction.
666  3. SRC0 is being used for sub d-word addressing (SDWA) of the
667  operands in the instruction.
668  4. VOP2 instructions also have four special opcodes:',
669  V_MADMK_{F16, F32} (0x24, 0x17), and V_MADAK_{F16, F32}',
670  (0x25, 0x18), that are always 64b. the only way to',
671  detect these special cases is to explicitly check,',
672  the opcodes',
673  */
674  if (iFmt->SRC0 == REG_SRC_LITERAL || (iFmt->SRC0 == REG_SRC_DPP) ||
675  (iFmt->SRC0 == REG_SRC_SWDA) || iFmt->OP == 0x17 ||
676  iFmt->OP == 0x18 || iFmt->OP == 0x24 || iFmt->OP == 0x25)
677  return true;
678 
679  return false;
680  }
681 
682  void
684  {
685  std::stringstream dis_stream;
686  dis_stream << _opcode << " ";
687  dis_stream << "v" << instData.VDST << ", ";
688 
689  if (writesVCC())
690  dis_stream << "vcc, ";
691 
692  if ((instData.SRC0 == REG_SRC_LITERAL) ||
693  (instData.SRC0 == REG_SRC_DPP) ||
694  (instData.SRC0 == REG_SRC_SWDA)) {
695  dis_stream << "0x" << std::hex << std::setfill('0') << std::setw(8)
696  << _srcLiteral << ", ";
697  } else {
698  dis_stream << opSelectorToRegSym(instData.SRC0) << ", ";
699  }
700 
701  // VOP2 instructions have four special opcodes:',
702  // V_MADMK_{F16, F32} (0x24, 0x17), and V_MADAK_{F16, F32}',
703  // (0x25, 0x18), that are always 64b. the only way to',
704  // detect these special cases is to explicitly check,',
705  // the opcodes',
706  if (instData.OP == 0x17 || instData.OP == 0x18 || instData.OP == 0x24
707  || instData.OP == 0x25) {
708  dis_stream << "0x" << std::hex << std::setfill('0') << std::setw(8)
709  << extData.imm_u32 << ", ";
710  }
711 
712  dis_stream << std::resetiosflags(std::ios_base::basefield) << "v"
713  << instData.VSRC1;
714 
715  if (readsVCC())
716  dis_stream << ", vcc";
717 
718  disassembly = dis_stream.str();
719  }
720 
721  // --- Inst_VOP1 base class methods ---
722 
723  Inst_VOP1::Inst_VOP1(InFmt_VOP1 *iFmt, const std::string &opcode)
725  {
726  // copy first instruction DWORD
727  instData = iFmt[0];
728  if (hasSecondDword(iFmt)) {
729  // copy second instruction DWORD into union
730  extData = ((MachInst)iFmt)[1];
731  _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
732  varSize = 4 + 4;
733  if (iFmt->SRC0 == REG_SRC_DPP) {
734  setFlag(IsDPP);
735  } else if (iFmt->SRC0 == REG_SRC_SWDA) {
736  setFlag(IsSDWA);
737  }
738  } else {
739  varSize = 4;
740  } // if
741  } // Inst_VOP1
742 
744  {
745  } // ~Inst_VOP1
746 
747  void
749  {
750  int opNum = 0;
751  // Needed because can't take addr of bitfield
752  int reg = instData.SRC0;
753 
754  if (numSrcRegOperands()) {
755  srcOps.emplace_back(reg, getOperandSize(opNum), true,
756  isScalarReg(reg), isVectorReg(reg), false);
757  opNum++;
758  }
759 
760  if (numDstRegOperands()) {
761  reg = instData.VDST;
762  dstOps.emplace_back(reg, getOperandSize(opNum), false,
763  false, true, false);
764  }
765 
766  assert(srcOps.size() == numSrcRegOperands());
767  assert(dstOps.size() == numDstRegOperands());
768  }
769 
770  int
772  {
773  return varSize;
774  } // instSize
775 
776  bool
778  {
779  /*
780  There are several cases where VOP1 instructions have a second dword:
781 
782  1. SRC0 is a literal.
783  2. SRC0 is being used to add a data parallel primitive (DPP)
784  operation to the instruction.
785  3. SRC0 is being used for sub d-word addressing (SDWA) of the
786  operands in the instruction.
787  */
788  if ((iFmt->SRC0 == REG_SRC_LITERAL) || (iFmt->SRC0 == REG_SRC_DPP) ||
789  (iFmt->SRC0 == REG_SRC_SWDA))
790  return true;
791 
792  return false;
793  }
794 
795  void
797  {
798  std::stringstream dis_stream;
799  dis_stream << _opcode << " ";
800  dis_stream << "v" << instData.VDST << ", ";
801 
802  if ((instData.SRC0 == REG_SRC_LITERAL) ||
803  (instData.SRC0 == REG_SRC_DPP) ||
804  (instData.SRC0 == REG_SRC_SWDA)) {
805  dis_stream << "0x" << std::hex << std::setfill('0') << std::setw(8)
806  << _srcLiteral;
807  } else {
808  dis_stream << opSelectorToRegSym(instData.SRC0);
809  }
810 
811  disassembly = dis_stream.str();
812  }
813 
814  // --- Inst_VOPC base class methods ---
815 
816  Inst_VOPC::Inst_VOPC(InFmt_VOPC *iFmt, const std::string &opcode)
818  {
819  setFlag(WritesVCC);
820  // copy first instruction DWORD
821  instData = iFmt[0];
822  if (hasSecondDword(iFmt)) {
823  // copy second instruction DWORD into union
824  extData = ((MachInst)iFmt)[1];
825  _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
826  varSize = 4 + 4;
827  if (iFmt->SRC0 == REG_SRC_DPP) {
828  setFlag(IsDPP);
829  } else if (iFmt->SRC0 == REG_SRC_SWDA) {
830  setFlag(IsSDWA);
831  }
832  } else {
833  varSize = 4;
834  } // if
835  } // Inst_VOPC
836 
838  {
839  } // ~Inst_VOPC
840 
841  void
843  {
844  int opNum = 0;
845 
846  // Needed because can't take addr of bitfield
847  int reg = instData.SRC0;
848  srcOps.emplace_back(reg, getOperandSize(opNum), true,
849  isScalarReg(reg), isVectorReg(reg), false);
850  opNum++;
851 
852  reg = instData.VSRC1;
853  srcOps.emplace_back(reg, getOperandSize(opNum), true,
854  false, true, false);
855  opNum++;
856 
857  assert(writesVCC());
858  dstOps.emplace_back(REG_VCC_LO, getOperandSize(opNum), false,
859  true, false, false);
860 
861  assert(srcOps.size() == numSrcRegOperands());
862  assert(dstOps.size() == numDstRegOperands());
863  }
864 
865  int
867  {
868  return varSize;
869  } // instSize
870 
871  bool
873  {
874  /*
875  There are several cases where VOPC instructions have a second dword:
876 
877  1. SRC0 is a literal.
878  2. SRC0 is being used to add a data parallel primitive (DPP)
879  operation to the instruction.
880  3. SRC0 is being used for sub d-word addressing (SDWA) of the
881  operands in the instruction.
882  */
883  if ((iFmt->SRC0 == REG_SRC_LITERAL) || (iFmt->SRC0 == REG_SRC_DPP) ||
884  (iFmt->SRC0 == REG_SRC_SWDA))
885  return true;
886 
887  return false;
888  }
889 
890  void
892  {
893  std::stringstream dis_stream;
894  dis_stream << _opcode << " vcc, ";
895 
896  dis_stream << opSelectorToRegSym(instData.SRC0) << ", ";
897  dis_stream << "v" << instData.VSRC1;
898 
899  disassembly = dis_stream.str();
900  }
901 
902  // --- Inst_VINTRP base class methods ---
903 
904  Inst_VINTRP::Inst_VINTRP(InFmt_VINTRP *iFmt, const std::string &opcode)
906  {
907  // copy first instruction DWORD
908  instData = iFmt[0];
909  } // Inst_VINTRP
910 
912  {
913  } // ~Inst_VINTRP
914 
915  int
917  {
918  return 4;
919  } // instSize
920 
921  // --- Inst_VOP3A base class methods ---
922 
923  Inst_VOP3A::Inst_VOP3A(InFmt_VOP3A *iFmt, const std::string &opcode,
924  bool sgpr_dst)
925  : VEGAGPUStaticInst(opcode), sgprDst(sgpr_dst)
926  {
927  // copy first instruction DWORD
928  instData = iFmt[0];
929  // copy second instruction DWORD
930  extData = ((InFmt_VOP3_1 *)iFmt)[1];
931  _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
932  } // Inst_VOP3A
933 
935  {
936  } // ~Inst_VOP3A
937 
938  void
940  {
941  // Also takes care of bitfield addr issue
942  unsigned int srcs[3] = {extData.SRC0, extData.SRC1, extData.SRC2};
943 
944  int opNum = 0;
945 
946  int numSrc = numSrcRegOperands() - readsVCC();
947  int numDst = numDstRegOperands() - writesVCC();
948 
949  for (opNum = 0; opNum < numSrc; opNum++) {
950  srcOps.emplace_back(srcs[opNum], getOperandSize(opNum), true,
951  isScalarReg(srcs[opNum]),
952  isVectorReg(srcs[opNum]), false);
953  }
954 
955  if (readsVCC()) {
956  srcOps.emplace_back(REG_VCC_LO, getOperandSize(opNum), true,
957  true, false, false);
958  opNum++;
959  }
960 
961  if (numDst) {
962  // Needed because can't take addr of bitfield
963  int reg = instData.VDST;
964  dstOps.emplace_back(reg, getOperandSize(opNum), false,
965  sgprDst, !sgprDst, false);
966  opNum++;
967  }
968 
969  if (writesVCC()) {
970  dstOps.emplace_back(REG_VCC_LO, getOperandSize(opNum), false,
971  true, false, false);
972  }
973 
974  assert(srcOps.size() == numSrcRegOperands());
975  assert(dstOps.size() == numDstRegOperands());
976  }
977 
978  int
980  {
981  return 8;
982  } // instSize
983 
984  void
986  {
987  std::stringstream dis_stream;
988  dis_stream << _opcode << " ";
989  int num_regs = 0;
990 
991  if (getOperandSize(getNumOperands() - 1) > 4) {
992  num_regs = getOperandSize(getNumOperands() - 1) / 4;
993  if (sgprDst)
994  dis_stream << "s[";
995  else
996  dis_stream << "v[";
997  dis_stream << instData.VDST << ":" << instData.VDST +
998  num_regs - 1 << "], ";
999  } else {
1000  if (sgprDst)
1001  dis_stream << "s";
1002  else
1003  dis_stream << "v";
1004  dis_stream << instData.VDST << ", ";
1005  }
1006 
1007  num_regs = getOperandSize(0) / 4;
1008 
1009  if (extData.NEG & 0x1) {
1010  dis_stream << "-" << opSelectorToRegSym(extData.SRC0, num_regs);
1011  } else {
1012  dis_stream << opSelectorToRegSym(extData.SRC0, num_regs);
1013  }
1014 
1015  if (numSrcRegOperands() > 1) {
1016  num_regs = getOperandSize(1) / 4;
1017 
1018  if (extData.NEG & 0x2) {
1019  dis_stream << ", -"
1020  << opSelectorToRegSym(extData.SRC1, num_regs);
1021  } else {
1022  dis_stream << ", "
1023  << opSelectorToRegSym(extData.SRC1, num_regs);
1024  }
1025  }
1026 
1027  if (numSrcRegOperands() > 2) {
1028  num_regs = getOperandSize(2) / 4;
1029 
1030  if (extData.NEG & 0x4) {
1031  dis_stream << ", -"
1032  << opSelectorToRegSym(extData.SRC2, num_regs);
1033  } else {
1034  dis_stream << ", "
1035  << opSelectorToRegSym(extData.SRC2, num_regs);
1036  }
1037  }
1038 
1039  disassembly = dis_stream.str();
1040  }
1041 
1042  // --- Inst_VOP3B base class methods ---
1043 
1044  Inst_VOP3B::Inst_VOP3B(InFmt_VOP3B *iFmt, const std::string &opcode)
1046  {
1047  // copy first instruction DWORD
1048  instData = iFmt[0];
1049  // copy second instruction DWORD
1050  extData = ((InFmt_VOP3_1 *)iFmt)[1];
1051  _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
1052  } // Inst_VOP3B
1053 
1055  {
1056  } // ~Inst_VOP3B
1057 
1058  void
1060  {
1061  // Also takes care of bitfield addr issue
1062  unsigned int srcs[3] = {extData.SRC0, extData.SRC1, extData.SRC2};
1063 
1064  int opNum = 0;
1065 
1066  int numSrc = numSrcRegOperands() - readsVCC();
1067  int numDst = numDstRegOperands() - writesVCC();
1068 
1069  for (opNum = 0; opNum < numSrc; opNum++) {
1070  srcOps.emplace_back(srcs[opNum], getOperandSize(opNum), true,
1071  isScalarReg(srcs[opNum]),
1072  isVectorReg(srcs[opNum]), false);
1073  }
1074 
1075  if (readsVCC()) {
1076  srcOps.emplace_back(REG_VCC_LO, getOperandSize(opNum), true,
1077  true, false, false);
1078  opNum++;
1079  }
1080 
1081  if (numDst) {
1082  // Needed because can't take addr of bitfield
1083  int reg = instData.VDST;
1084  dstOps.emplace_back(reg, getOperandSize(opNum), false,
1085  false, true, false);
1086  opNum++;
1087  }
1088 
1089  if (writesVCC()) {
1090  dstOps.emplace_back(REG_VCC_LO, getOperandSize(opNum), false,
1091  true, false, false);
1092  }
1093 
1094  assert(srcOps.size() == numSrcRegOperands());
1095  assert(dstOps.size() == numDstRegOperands());
1096  }
1097 
1098  int
1100  {
1101  return 8;
1102  } // instSize
1103 
1104  void
1106  {
1107  std::stringstream dis_stream;
1108  dis_stream << _opcode << " ";
1109 
1110  dis_stream << "v" << instData.VDST << ", ";
1111 
1112  if (numDstRegOperands() == 2) {
1113  if (getOperandSize(getNumOperands() - 1) > 4) {
1114  int num_regs = getOperandSize(getNumOperands() - 1) / 4;
1115  dis_stream << opSelectorToRegSym(instData.SDST, num_regs)
1116  << ", ";
1117  } else {
1118  dis_stream << opSelectorToRegSym(instData.SDST) << ", ";
1119  }
1120  }
1121 
1122  if (extData.NEG & 0x1) {
1123  dis_stream << "-" << opSelectorToRegSym(extData.SRC0) << ", ";
1124  } else {
1125  dis_stream << opSelectorToRegSym(extData.SRC0) << ", ";
1126  }
1127 
1128  if (extData.NEG & 0x2) {
1129  dis_stream << "-" << opSelectorToRegSym(extData.SRC1);
1130  } else {
1131  dis_stream << opSelectorToRegSym(extData.SRC1);
1132  }
1133 
1134  if (numSrcRegOperands() == 3) {
1135  if (extData.NEG & 0x4) {
1136  dis_stream << ", -" << opSelectorToRegSym(extData.SRC2);
1137  } else {
1138  dis_stream << ", " << opSelectorToRegSym(extData.SRC2);
1139  }
1140  }
1141 
1142  if (readsVCC())
1143  dis_stream << ", vcc";
1144 
1145  disassembly = dis_stream.str();
1146  }
1147 
1148  // --- Inst_DS base class methods ---
1149 
1150  Inst_DS::Inst_DS(InFmt_DS *iFmt, const std::string &opcode)
1152  {
1153  setFlag(GroupSegment);
1154 
1155  // copy first instruction DWORD
1156  instData = iFmt[0];
1157  // copy second instruction DWORD
1158  extData = ((InFmt_DS_1 *)iFmt)[1];
1159  _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
1160  } // Inst_DS
1161 
1163  {
1164  } // ~Inst_DS
1165 
1166  void
1168  {
1169  unsigned int srcs[3] = {extData.ADDR, extData.DATA0, extData.DATA1};
1170 
1171  int opIdx = 0;
1172 
1173  for (opIdx = 0; opIdx < numSrcRegOperands(); opIdx++){
1174  srcOps.emplace_back(srcs[opIdx], getOperandSize(opIdx), true,
1175  false, true, false);
1176  }
1177 
1178  if (numDstRegOperands()) {
1179  // Needed because can't take addr of bitfield
1180  int reg = extData.VDST;
1181  dstOps.emplace_back(reg, getOperandSize(opIdx), false,
1182  false, true, false);
1183  }
1184 
1185  assert(srcOps.size() == numSrcRegOperands());
1186  assert(dstOps.size() == numDstRegOperands());
1187  }
1188 
1189  int
1191  {
1192  return 8;
1193  } // instSize
1194 
1195  void
1197  {
1198  std::stringstream dis_stream;
1199  dis_stream << _opcode << " ";
1200 
1201  if (numDstRegOperands())
1202  dis_stream << "v" << extData.VDST << ", ";
1203 
1204  dis_stream << "v" << extData.ADDR;
1205 
1206  if (numSrcRegOperands() > 1)
1207  dis_stream << ", v" << extData.DATA0;
1208 
1209  if (numSrcRegOperands() > 2)
1210  dis_stream << ", v" << extData.DATA1;
1211 
1212  uint16_t offset = 0;
1213 
1214  if (instData.OFFSET1) {
1215  offset += instData.OFFSET1;
1216  offset <<= 8;
1217  }
1218 
1219  if (instData.OFFSET0)
1220  offset += instData.OFFSET0;
1221 
1222  if (offset)
1223  dis_stream << " offset:" << offset;
1224 
1225  disassembly = dis_stream.str();
1226  }
1227 
1228  // --- Inst_MUBUF base class methods ---
1229 
1230  Inst_MUBUF::Inst_MUBUF(InFmt_MUBUF *iFmt, const std::string &opcode)
1232  {
1233  // copy first instruction DWORD
1234  instData = iFmt[0];
1235  // copy second instruction DWORD
1236  extData = ((InFmt_MUBUF_1 *)iFmt)[1];
1237  _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
1238 
1239  if (instData.GLC)
1240  setFlag(GloballyCoherent);
1241 
1242  if (instData.SLC)
1243  setFlag(SystemCoherent);
1244  } // Inst_MUBUF
1245 
1247  {
1248  } // ~Inst_MUBUF
1249 
1250  void
1252  {
1253  // Currently there are three formats:
1254  // 0 src + 0 dst
1255  // 3 src + 1 dst
1256  // 4 src + 0 dst
1257  int opNum = 0;
1258 
1259  // Needed because can't take addr of bitfield;
1260  int reg = 0;
1261 
1262  if (numSrcRegOperands()) {
1263  if (numSrcRegOperands() == getNumOperands()) {
1264  reg = extData.VDATA;
1265  srcOps.emplace_back(reg, getOperandSize(opNum), true,
1266  false, true, false);
1267  opNum++;
1268  }
1269 
1270  reg = extData.VADDR;
1271  srcOps.emplace_back(reg, getOperandSize(opNum), true,
1272  false, true, false);
1273  opNum++;
1274 
1275  reg = extData.SRSRC;
1276  srcOps.emplace_back(reg, getOperandSize(opNum), true,
1277  true, false, false);
1278  opNum++;
1279 
1280  reg = extData.SOFFSET;
1281  srcOps.emplace_back(reg, getOperandSize(opNum), true,
1282  true, false, false);
1283  opNum++;
1284  }
1285 
1286  // extData.VDATA moves in the reg list depending on the instruction
1287  if (numDstRegOperands()) {
1288  reg = extData.VDATA;
1289  dstOps.emplace_back(reg, getOperandSize(opNum), false,
1290  false, true, false);
1291  }
1292 
1293  assert(srcOps.size() == numSrcRegOperands());
1294  assert(dstOps.size() == numDstRegOperands());
1295  }
1296 
1297  int
1299  {
1300  return 8;
1301  } // instSize
1302 
1303  void
1305  {
1306  // SRSRC is always in units of 4 SGPRs
1307  int srsrc_val = extData.SRSRC * 4;
1308  std::stringstream dis_stream;
1309  dis_stream << _opcode << " ";
1310  dis_stream << "v" << extData.VDATA << ", v" << extData.VADDR << ", ";
1311  dis_stream << "s[" << srsrc_val << ":"
1312  << srsrc_val + 3 << "], ";
1313  dis_stream << "s" << extData.SOFFSET;
1314 
1315  if (instData.OFFSET)
1316  dis_stream << ", offset:" << instData.OFFSET;
1317 
1318  disassembly = dis_stream.str();
1319  }
1320 
1321  // --- Inst_MTBUF base class methods ---
1322 
1323  Inst_MTBUF::Inst_MTBUF(InFmt_MTBUF *iFmt, const std::string &opcode)
1325  {
1326  // copy first instruction DWORD
1327  instData = iFmt[0];
1328  // copy second instruction DWORD
1329  extData = ((InFmt_MTBUF_1 *)iFmt)[1];
1330  _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
1331 
1332  if (instData.GLC)
1333  setFlag(GloballyCoherent);
1334 
1335  if (extData.SLC)
1336  setFlag(SystemCoherent);
1337  } // Inst_MTBUF
1338 
1340  {
1341  } // ~Inst_MTBUF
1342 
1343  void
1345  {
1346  // Currently there are two formats:
1347  // 3 src + 1 dst
1348  // 4 src + 0 dst
1349  int opNum = 0;
1350 
1351  // Needed because can't take addr of bitfield
1352  int reg = 0;
1353 
1354  if (numSrcRegOperands() == getNumOperands()) {
1355  reg = extData.VDATA;
1356  srcOps.emplace_back(reg, getOperandSize(opNum), true,
1357  false, true, false);
1358  opNum++;
1359  }
1360 
1361  reg = extData.VADDR;
1362  srcOps.emplace_back(reg, getOperandSize(opNum), true,
1363  false, true, false);
1364  opNum++;
1365 
1366  reg = extData.SRSRC;
1367  srcOps.emplace_back(reg, getOperandSize(opNum), true,
1368  true, false, false);
1369  opNum++;
1370 
1371  reg = extData.SOFFSET;
1372  srcOps.emplace_back(reg, getOperandSize(opNum), true,
1373  true, false, false);
1374  opNum++;
1375 
1376  // extData.VDATA moves in the reg list depending on the instruction
1377  if (numDstRegOperands()) {
1378  reg = extData.VDATA;
1379  dstOps.emplace_back(reg, getOperandSize(opNum), false,
1380  false, true, false);
1381  }
1382 
1383  assert(srcOps.size() == numSrcRegOperands());
1384  assert(dstOps.size() == numDstRegOperands());
1385  }
1386 
1387  int
1389  {
1390  return 8;
1391  } // instSize
1392 
1393  // --- Inst_MIMG base class methods ---
1394 
1395  Inst_MIMG::Inst_MIMG(InFmt_MIMG *iFmt, const std::string &opcode)
1397  {
1398  // copy first instruction DWORD
1399  instData = iFmt[0];
1400  // copy second instruction DWORD
1401  extData = ((InFmt_MIMG_1 *)iFmt)[1];
1402  _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
1403 
1404  if (instData.GLC)
1405  setFlag(GloballyCoherent);
1406 
1407  if (instData.SLC)
1408  setFlag(SystemCoherent);
1409  } // Inst_MIMG
1410 
1412  {
1413  } // ~Inst_MIMG
1414 
1415  void
1417  {
1418  // Three formats:
1419  // 1 dst + 2 src : s,s,d
1420  // 0 dst + 3 src : s,s,s
1421  // 1 dst + 3 src : s,s,s,d
1422  int opNum = 0;
1423 
1424  // Needed because can't take addr of bitfield
1425  int reg = 0;
1426 
1427  if (numSrcRegOperands() == getNumOperands()) {
1428  reg = extData.VDATA;
1429  srcOps.emplace_back(reg, getOperandSize(opNum), true,
1430  false, true, false);
1431  opNum++;
1432  }
1433 
1434  reg = extData.VADDR;
1435  srcOps.emplace_back(reg, getOperandSize(opNum), true,
1436  false, true, false);
1437  opNum++;
1438 
1439  reg = extData.SRSRC;
1440  srcOps.emplace_back(reg, getOperandSize(opNum), true,
1441  true, false, false);
1442  opNum++;
1443 
1444  if (getNumOperands() == 4) {
1445  reg = extData.SSAMP;
1446  srcOps.emplace_back(reg, getOperandSize(opNum), true,
1447  true, false, false);
1448  opNum++;
1449  }
1450 
1451  // extData.VDATA moves in the reg list depending on the instruction
1452  if (numDstRegOperands()) {
1453  reg = extData.VDATA;
1454  dstOps.emplace_back(reg, getOperandSize(opNum), false,
1455  false, true, false);
1456  }
1457 
1458  assert(srcOps.size() == numSrcRegOperands());
1459  assert(dstOps.size() == numDstRegOperands());
1460  }
1461 
1462  int
1464  {
1465  return 8;
1466  } // instSize
1467 
1468  // --- Inst_EXP base class methods ---
1469 
1470  Inst_EXP::Inst_EXP(InFmt_EXP *iFmt, const std::string &opcode)
1472  {
1473  // copy first instruction DWORD
1474  instData = iFmt[0];
1475  // copy second instruction DWORD
1476  extData = ((InFmt_EXP_1 *)iFmt)[1];
1477  _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
1478  } // Inst_EXP
1479 
1481  {
1482  } // ~Inst_EXP
1483 
1484  void
1486  {
1487  // Only 1 instruction, 1 format: 1 dst + 4 src
1488  int opNum = 0;
1489 
1490  // Avoids taking addr of bitfield
1491  unsigned int srcs[4] = {extData.VSRC0, extData.VSRC1,
1493 
1494  for (opNum = 0; opNum < 4; opNum++) {
1495  srcOps.emplace_back(srcs[opNum], getOperandSize(opNum), true,
1496  false, true, false);
1497  }
1498 
1499  //TODO: Add the dst operand, don't know what it is right now
1500  }
1501 
1502  int
1504  {
1505  return 8;
1506  } // instSize
1507 
1508  // --- Inst_FLAT base class methods ---
1509 
1510  Inst_FLAT::Inst_FLAT(InFmt_FLAT *iFmt, const std::string &opcode)
1512  {
1513  // The SEG field specifies FLAT(0) SCRATCH(1) or GLOBAL(2)
1514  if (iFmt->SEG == 0) {
1515  setFlag(Flat);
1516  } else if (iFmt->SEG == 2) {
1517  setFlag(FlatGlobal);
1518  } else {
1519  panic("Unknown flat segment: %d\n", iFmt->SEG);
1520  }
1521 
1522  // copy first instruction DWORD
1523  instData = iFmt[0];
1524  // copy second instruction DWORD
1525  extData = ((InFmt_FLAT_1 *)iFmt)[1];
1526  _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
1527 
1528  if (instData.GLC)
1529  setFlag(GloballyCoherent);
1530 
1531  if (instData.SLC)
1532  setFlag(SystemCoherent);
1533  } // Inst_FLAT
1534 
1536  {
1537  } // ~Inst_FLAT
1538 
1539  void
1541  {
1542  // One of the flat subtypes should be specified via flags
1543  assert(isFlat() ^ isFlatGlobal());
1544 
1545  if (isFlat()) {
1547  } else if (isFlatGlobal()) {
1549  } else {
1550  panic("Unknown flat subtype!\n");
1551  }
1552  }
1553 
1554  void
1556  {
1557  //3 formats:
1558  // 1 dst + 1 src (load)
1559  // 0 dst + 2 src (store)
1560  // 1 dst + 2 src (atomic)
1561  int opNum = 0;
1562 
1563  // Needed because can't take addr of bitfield
1564  int reg = 0;
1565 
1566  if (getNumOperands() > 2)
1567  assert(isAtomic());
1568 
1569  reg = extData.ADDR;
1570  srcOps.emplace_back(reg, getOperandSize(opNum), true,
1571  false, true, false);
1572  opNum++;
1573 
1574  if (numSrcRegOperands() == 2) {
1575  reg = extData.DATA;
1576  srcOps.emplace_back(reg, getOperandSize(opNum), true,
1577  false, true, false);
1578  opNum++;
1579  }
1580 
1581  if (numDstRegOperands()) {
1582  reg = extData.VDST;
1583  dstOps.emplace_back(reg, getOperandSize(opNum), false,
1584  false, true, false);
1585  }
1586 
1587  assert(srcOps.size() == numSrcRegOperands());
1588  assert(dstOps.size() == numDstRegOperands());
1589  }
1590 
1591  void
1593  {
1594  //3 formats:
1595  // 1 dst + 2 src (load)
1596  // 0 dst + 3 src (store)
1597  // 1 dst + 3 src (atomic)
1598  int opNum = 0;
1599 
1600  // Needed because can't take addr of bitfield
1601  int reg = 0;
1602 
1603  if (getNumOperands() > 3)
1604  assert(isAtomic());
1605 
1606  reg = extData.ADDR;
1607  srcOps.emplace_back(reg, getOperandSize(opNum), true,
1608  false, true, false);
1609  opNum++;
1610 
1611  if (numSrcRegOperands() == 2) {
1612  reg = extData.SADDR;
1613  // 0x7f (off) means the sgpr is not used. Don't read it
1614  if (reg != 0x7f) {
1615  srcOps.emplace_back(reg, getOperandSize(opNum), true,
1616  true, false, false);
1617  }
1618  opNum++;
1619  }
1620 
1621  if (numSrcRegOperands() == 3) {
1622  reg = extData.DATA;
1623  srcOps.emplace_back(reg, getOperandSize(opNum), true,
1624  false, true, false);
1625  opNum++;
1626 
1627  reg = extData.SADDR;
1628  // 0x7f (off) means the sgpr is not used. Don't read it
1629  if (reg != 0x7f) {
1630  srcOps.emplace_back(reg, getOperandSize(opNum), true,
1631  true, false, false);
1632  }
1633  opNum++;
1634  }
1635 
1636  if (numDstRegOperands()) {
1637  reg = extData.VDST;
1638  dstOps.emplace_back(reg, getOperandSize(opNum), false,
1639  false, true, false);
1640  }
1641 
1642  reg = extData.SADDR;
1643  if (reg != 0x7f) {
1644  assert(srcOps.size() == numSrcRegOperands());
1645  } else {
1646  assert(srcOps.size() == numSrcRegOperands() - 1);
1647  }
1648  assert(dstOps.size() == numDstRegOperands());
1649  }
1650 
1651  int
1653  {
1654  return 8;
1655  } // instSize
1656 
1657  void
1659  {
1660  // One of the flat subtypes should be specified via flags
1661  assert(isFlat() ^ isFlatGlobal());
1662 
1663  if (isFlat()) {
1665  } else if (isFlatGlobal()) {
1667  } else {
1668  panic("Unknown flat subtype!\n");
1669  }
1670  }
1671 
1672  void
1674  {
1675  std::stringstream dis_stream;
1676  dis_stream << _opcode << " ";
1677 
1678  if (isLoad())
1679  dis_stream << "v" << extData.VDST << ", ";
1680 
1681  dis_stream << "v[" << extData.ADDR << ":" << extData.ADDR + 1 << "]";
1682 
1683  if (isStore())
1684  dis_stream << ", v" << extData.DATA;
1685 
1686  disassembly = dis_stream.str();
1687  }
1688 
1689  void
1691  {
1692  // Replace flat_ with global_ in assembly string
1693  std::string global_opcode = _opcode;
1694  global_opcode.replace(0, 4, "global");
1695 
1696  std::stringstream dis_stream;
1697  dis_stream << global_opcode << " ";
1698 
1699  if (isLoad())
1700  dis_stream << "v" << extData.VDST << ", ";
1701 
1702  dis_stream << "v[" << extData.ADDR << ":" << extData.ADDR + 1 << "]";
1703 
1704  if (isStore())
1705  dis_stream << ", v" << extData.DATA;
1706 
1707  if (extData.SADDR == 0x7f)
1708  dis_stream << ", off";
1709  else
1710  dis_stream << ", " << extData.SADDR;
1711 
1712  disassembly = dis_stream.str();
1713  }
1714 } // namespace VegaISA
1715 } // namespace gem5
gem5::VegaISA::Inst_SOPK::extData
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Definition: op_encodings.hh:109
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This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1930
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Definition: op_encodings.cc:85
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Definition: gpu_decoder.hh:1701
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Definition: op_encodings.cc:837
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Definition: op_encodings.cc:150
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Definition: registers.cc:225
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Definition: op_encodings.cc:683
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InstFormat * MachInst
used to represent the encoding of a VEGA inst.
Definition: gpu_types.hh:61
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Definition: gpu_decoder.hh:1750
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Definition: op_encodings.cc:891
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Definition: gpu_decoder.hh:1611
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Definition: gpu_static_inst.hh:303
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Definition: op_encodings.cc:338
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Definition: op_encodings.hh:294
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Definition: gpu_decoder.hh:1626
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Definition: op_encodings.cc:1658
gem5::VegaISA::InFmt_VOP3_1::SRC0
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Definition: gpu_decoder.hh:1810
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@ REG_SRC_LITERAL
Definition: gpu_registers.hh:130
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Definition: gpu_decoder.hh:1776
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int instSize() const override
Definition: op_encodings.cc:652
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Definition: gpu_decoder.hh:1827
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Definition: op_encodings.cc:985
gem5::VegaISA::Inst_MUBUF::initOperandInfo
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Definition: op_encodings.cc:1251
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Definition: op_encodings.cc:1230
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Definition: gpu_decoder.hh:1636
gem5::VegaISA::Inst_FLAT::instData
InFmt_FLAT instData
Definition: op_encodings.hh:831
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Bitfield< 23, 0 > offset
Definition: types.hh:144
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unsigned int SIMM16
Definition: gpu_decoder.hh:1764
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Definition: op_encodings.cc:1470
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Definition: op_encodings.cc:872
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unsigned int SDATA
Definition: gpu_decoder.hh:1725
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gem5::VegaISA::Inst_SOPC::extData
InstFormat extData
Definition: op_encodings.hh:153
gem5::VegaISA::InFmt_SMEM::IMM
unsigned int IMM
Definition: gpu_decoder.hh:1730
gem5::VegaISA::InFmt_MIMG::SLC
unsigned int SLC
Definition: gpu_decoder.hh:1667
gem5::VegaISA::Inst_VOP2::instData
InFmt_VOP2 instData
Definition: op_encodings.hh:270
gem5::VegaISA::InFmt_VOP3B::VDST
unsigned int VDST
Definition: gpu_decoder.hh:1818
gem5::VegaISA::InFmt_DS_1::VDST
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Definition: gpu_decoder.hh:1613
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