gem5  v21.1.0.2
op_encodings.hh
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33 
34 #ifndef __ARCH_VEGA_INSTS_OP_ENCODINGS_HH__
35 #define __ARCH_VEGA_INSTS_OP_ENCODINGS_HH__
36 
41 #include "debug/GPUExec.hh"
42 #include "debug/VEGA.hh"
44 
45 namespace gem5
46 {
47 
48 namespace VegaISA
49 {
51  {
52  uint64_t baseAddr : 48;
53  uint32_t stride : 14;
54  uint32_t cacheSwizzle : 1;
55  uint32_t swizzleEn : 1;
56  uint32_t numRecords : 32;
57  uint32_t dstSelX : 3;
58  uint32_t dstSelY : 3;
59  uint32_t dstSelZ : 3;
60  uint32_t dstSelW : 3;
61  uint32_t numFmt : 3;
62  uint32_t dataFmt : 4;
63  uint32_t elemSize : 2;
64  uint32_t idxStride : 2;
65  uint32_t addTidEn : 1;
66  uint32_t atc : 1;
67  uint32_t hashEn : 1;
68  uint32_t heap : 1;
69  uint32_t mType : 3;
70  uint32_t type : 2;
71  };
72 
73  // --- purely virtual instruction classes ---
74 
76  {
77  public:
78  Inst_SOP2(InFmt_SOP2*, const std::string &opcode);
79 
80  int instSize() const override;
81  void generateDisassembly() override;
82 
83  void initOperandInfo() override;
84 
85  protected:
86  // first instruction DWORD
88  // possible second DWORD
90  uint32_t varSize;
91 
92  private:
93  bool hasSecondDword(InFmt_SOP2 *);
94  }; // Inst_SOP2
95 
97  {
98  public:
99  Inst_SOPK(InFmt_SOPK*, const std::string &opcode);
100  ~Inst_SOPK();
101 
102  int instSize() const override;
103  void generateDisassembly() override;
104 
105  void initOperandInfo() override;
106 
107  protected:
108  // first instruction DWORD
110  // possible second DWORD
112  uint32_t varSize;
113 
114  private:
115  bool hasSecondDword(InFmt_SOPK *);
116  }; // Inst_SOPK
117 
119  {
120  public:
121  Inst_SOP1(InFmt_SOP1*, const std::string &opcode);
122  ~Inst_SOP1();
123 
124  int instSize() const override;
125  void generateDisassembly() override;
126 
127  void initOperandInfo() override;
128 
129  protected:
130  // first instruction DWORD
132  // possible second DWORD
134  uint32_t varSize;
135 
136  private:
137  bool hasSecondDword(InFmt_SOP1 *);
138  }; // Inst_SOP1
139 
141  {
142  public:
143  Inst_SOPC(InFmt_SOPC*, const std::string &opcode);
144  ~Inst_SOPC();
145 
146  int instSize() const override;
147  void generateDisassembly() override;
148 
149  void initOperandInfo() override;
150 
151  protected:
152  // first instruction DWORD
154  // possible second DWORD
156  uint32_t varSize;
157 
158  private:
159  bool hasSecondDword(InFmt_SOPC *);
160  }; // Inst_SOPC
161 
163  {
164  public:
165  Inst_SOPP(InFmt_SOPP*, const std::string &opcode);
166  ~Inst_SOPP();
167 
168  int instSize() const override;
169  void generateDisassembly() override;
170 
171  void initOperandInfo() override;
172 
173  protected:
174  // first instruction DWORD
176  }; // Inst_SOPP
177 
179  {
180  public:
181  Inst_SMEM(InFmt_SMEM*, const std::string &opcode);
182  ~Inst_SMEM();
183 
184  int instSize() const override;
185  void generateDisassembly() override;
186 
187  void initOperandInfo() override;
188 
189  protected:
193  template<int N>
194  void
196  {
197  initMemReqScalarHelper<ScalarRegU32, N>(gpuDynInst,
199  }
200 
204  template<int N>
205  void
207  {
208  initMemReqScalarHelper<ScalarRegU32, N>(gpuDynInst,
210  }
211 
215  void
218  {
219  Addr vaddr = ((addr.rawData() + offset) & ~0x3);
220  gpu_dyn_inst->scalarAddr = vaddr;
221  }
222 
228  void
229  calcAddr(GPUDynInstPtr gpu_dyn_inst,
231  {
232  BufferRsrcDescriptor rsrc_desc;
233  ScalarRegU32 clamped_offset(offset);
234  std::memcpy((void*)&rsrc_desc, s_rsrc_desc.rawDataPtr(),
235  sizeof(BufferRsrcDescriptor));
236 
242  if (!rsrc_desc.stride && offset >= rsrc_desc.numRecords) {
243  clamped_offset = rsrc_desc.numRecords;
244  } else if (rsrc_desc.stride && offset
245  > (rsrc_desc.stride * rsrc_desc.numRecords)) {
246  clamped_offset = (rsrc_desc.stride * rsrc_desc.numRecords);
247  }
248 
249  Addr vaddr = ((rsrc_desc.baseAddr + clamped_offset) & ~0x3);
250  gpu_dyn_inst->scalarAddr = vaddr;
251  }
252 
253  // first instruction DWORD
255  // second instruction DWORD
257  }; // Inst_SMEM
258 
260  {
261  public:
262  Inst_VOP2(InFmt_VOP2*, const std::string &opcode);
263  ~Inst_VOP2();
264 
265  int instSize() const override;
266  void generateDisassembly() override;
267 
268  void initOperandInfo() override;
269 
270  protected:
271  // first instruction DWORD
273  // possible second DWORD
275  uint32_t varSize;
276 
277  private:
278  bool hasSecondDword(InFmt_VOP2 *);
279  }; // Inst_VOP2
280 
282  {
283  public:
284  Inst_VOP1(InFmt_VOP1*, const std::string &opcode);
285  ~Inst_VOP1();
286 
287  int instSize() const override;
288  void generateDisassembly() override;
289 
290  void initOperandInfo() override;
291 
292  protected:
293  // first instruction DWORD
295  // possible second DWORD
297  uint32_t varSize;
298 
299  private:
300  bool hasSecondDword(InFmt_VOP1 *);
301  }; // Inst_VOP1
302 
304  {
305  public:
306  Inst_VOPC(InFmt_VOPC*, const std::string &opcode);
307  ~Inst_VOPC();
308 
309  int instSize() const override;
310  void generateDisassembly() override;
311 
312  void initOperandInfo() override;
313 
314  protected:
315  // first instruction DWORD
317  // possible second DWORD
319  uint32_t varSize;
320 
321  private:
322  bool hasSecondDword(InFmt_VOPC *);
323  }; // Inst_VOPC
324 
326  {
327  public:
328  Inst_VINTRP(InFmt_VINTRP*, const std::string &opcode);
329  ~Inst_VINTRP();
330 
331  int instSize() const override;
332 
333  protected:
334  // first instruction DWORD
336  }; // Inst_VINTRP
337 
339  {
340  public:
341  Inst_VOP3A(InFmt_VOP3A*, const std::string &opcode, bool sgpr_dst);
342  ~Inst_VOP3A();
343 
344  int instSize() const override;
345  void generateDisassembly() override;
346 
347  void initOperandInfo() override;
348 
349  protected:
350  // first instruction DWORD
352  // second instruction DWORD
354 
355  private:
356  bool hasSecondDword(InFmt_VOP3A *);
367  const bool sgprDst;
368  }; // Inst_VOP3A
369 
371  {
372  public:
373  Inst_VOP3B(InFmt_VOP3B*, const std::string &opcode);
374  ~Inst_VOP3B();
375 
376  int instSize() const override;
377  void generateDisassembly() override;
378 
379  void initOperandInfo() override;
380 
381  protected:
382  // first instruction DWORD
384  // second instruction DWORD
386 
387  private:
388  bool hasSecondDword(InFmt_VOP3B *);
389  }; // Inst_VOP3B
390 
391  class Inst_DS : public VEGAGPUStaticInst
392  {
393  public:
394  Inst_DS(InFmt_DS*, const std::string &opcode);
395  ~Inst_DS();
396 
397  int instSize() const override;
398  void generateDisassembly() override;
399 
400  void initOperandInfo() override;
401 
402  protected:
403  template<typename T>
404  void
406  {
407  Wavefront *wf = gpuDynInst->wavefront();
408 
409  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
410  if (gpuDynInst->exec_mask[lane]) {
411  Addr vaddr = gpuDynInst->addr[lane] + offset;
412 
413  (reinterpret_cast<T*>(gpuDynInst->d_data))[lane]
414  = wf->ldsChunk->read<T>(vaddr);
415  }
416  }
417  }
418 
419  template<typename T>
420  void
421  initDualMemRead(GPUDynInstPtr gpuDynInst, Addr offset0, Addr offset1)
422  {
423  Wavefront *wf = gpuDynInst->wavefront();
424 
425  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
426  if (gpuDynInst->exec_mask[lane]) {
427  Addr vaddr0 = gpuDynInst->addr[lane] + offset0;
428  Addr vaddr1 = gpuDynInst->addr[lane] + offset1;
429 
430  (reinterpret_cast<T*>(gpuDynInst->d_data))[lane * 2]
431  = wf->ldsChunk->read<T>(vaddr0);
432  (reinterpret_cast<T*>(gpuDynInst->d_data))[lane * 2 + 1]
433  = wf->ldsChunk->read<T>(vaddr1);
434  }
435  }
436  }
437 
438  template<typename T>
439  void
441  {
442  Wavefront *wf = gpuDynInst->wavefront();
443 
444  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
445  if (gpuDynInst->exec_mask[lane]) {
446  Addr vaddr = gpuDynInst->addr[lane] + offset;
447  wf->ldsChunk->write<T>(vaddr,
448  (reinterpret_cast<T*>(gpuDynInst->d_data))[lane]);
449  }
450  }
451  }
452 
453  template<typename T>
454  void
455  initDualMemWrite(GPUDynInstPtr gpuDynInst, Addr offset0, Addr offset1)
456  {
457  Wavefront *wf = gpuDynInst->wavefront();
458 
459  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
460  if (gpuDynInst->exec_mask[lane]) {
461  Addr vaddr0 = gpuDynInst->addr[lane] + offset0;
462  Addr vaddr1 = gpuDynInst->addr[lane] + offset1;
463  wf->ldsChunk->write<T>(vaddr0, (reinterpret_cast<T*>(
464  gpuDynInst->d_data))[lane * 2]);
465  wf->ldsChunk->write<T>(vaddr1, (reinterpret_cast<T*>(
466  gpuDynInst->d_data))[lane * 2 + 1]);
467  }
468  }
469  }
470 
471  void
473  {
474  Wavefront *wf = gpuDynInst->wavefront();
475 
476  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
477  if (wf->execMask(lane)) {
478  gpuDynInst->addr.at(lane) = (Addr)addr[lane];
479  }
480  }
481  }
482 
483  // first instruction DWORD
485  // second instruction DWORD
487  }; // Inst_DS
488 
490  {
491  public:
492  Inst_MUBUF(InFmt_MUBUF*, const std::string &opcode);
493  ~Inst_MUBUF();
494 
495  int instSize() const override;
496  void generateDisassembly() override;
497 
498  void initOperandInfo() override;
499 
500  protected:
501  template<typename T>
502  void
504  {
505  // temporarily modify exec_mask to supress memory accesses to oob
506  // regions. Only issue memory requests for lanes that have their
507  // exec_mask set and are not out of bounds.
508  VectorMask old_exec_mask = gpuDynInst->exec_mask;
509  gpuDynInst->exec_mask &= ~oobMask;
510  initMemReqHelper<T, 1>(gpuDynInst, MemCmd::ReadReq);
511  gpuDynInst->exec_mask = old_exec_mask;
512  }
513 
514 
515  template<int N>
516  void
518  {
519  // temporarily modify exec_mask to supress memory accesses to oob
520  // regions. Only issue memory requests for lanes that have their
521  // exec_mask set and are not out of bounds.
522  VectorMask old_exec_mask = gpuDynInst->exec_mask;
523  gpuDynInst->exec_mask &= ~oobMask;
524  initMemReqHelper<VecElemU32, N>(gpuDynInst, MemCmd::ReadReq);
525  gpuDynInst->exec_mask = old_exec_mask;
526  }
527 
528  template<typename T>
529  void
531  {
532  // temporarily modify exec_mask to supress memory accesses to oob
533  // regions. Only issue memory requests for lanes that have their
534  // exec_mask set and are not out of bounds.
535  VectorMask old_exec_mask = gpuDynInst->exec_mask;
536  gpuDynInst->exec_mask &= ~oobMask;
537  initMemReqHelper<T, 1>(gpuDynInst, MemCmd::WriteReq);
538  gpuDynInst->exec_mask = old_exec_mask;
539  }
540 
541  template<int N>
542  void
544  {
545  // temporarily modify exec_mask to supress memory accesses to oob
546  // regions. Only issue memory requests for lanes that have their
547  // exec_mask set and are not out of bounds.
548  VectorMask old_exec_mask = gpuDynInst->exec_mask;
549  gpuDynInst->exec_mask &= ~oobMask;
550  initMemReqHelper<VecElemU32, N>(gpuDynInst, MemCmd::WriteReq);
551  gpuDynInst->exec_mask = old_exec_mask;
552  }
553 
554  void
556  {
557  // create request and set flags
558  gpuDynInst->resetEntireStatusVector();
559  gpuDynInst->setStatusVector(0, 1);
560  RequestPtr req = std::make_shared<Request>(0, 0, 0,
561  gpuDynInst->computeUnit()->
562  requestorId(), 0,
563  gpuDynInst->wfDynId);
564  gpuDynInst->setRequestFlags(req);
565  gpuDynInst->computeUnit()->
566  injectGlobalMemFence(gpuDynInst, false, req);
567  }
568 
589  template<typename VOFF, typename VIDX, typename SRSRC, typename SOFF>
590  void
591  calcAddr(GPUDynInstPtr gpuDynInst, VOFF v_off, VIDX v_idx,
592  SRSRC s_rsrc_desc, SOFF s_offset, int inst_offset)
593  {
594  Addr vaddr = 0;
595  Addr base_addr = 0;
596  Addr stride = 0;
597  Addr buf_idx = 0;
598  Addr buf_off = 0;
599  BufferRsrcDescriptor rsrc_desc;
600 
601  std::memcpy((void*)&rsrc_desc, s_rsrc_desc.rawDataPtr(),
602  sizeof(BufferRsrcDescriptor));
603 
604  base_addr = rsrc_desc.baseAddr;
605 
606  stride = rsrc_desc.addTidEn ? ((rsrc_desc.dataFmt << 14)
607  + rsrc_desc.stride) : rsrc_desc.stride;
608 
609  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
610  if (gpuDynInst->exec_mask[lane]) {
611  vaddr = base_addr + s_offset.rawData();
617  buf_idx = v_idx[lane] + (rsrc_desc.addTidEn ? lane : 0);
618 
619  buf_off = v_off[lane] + inst_offset;
620 
621 
629  if (stride == 0 || !rsrc_desc.swizzleEn) {
630  if (buf_off + stride * buf_idx >=
631  rsrc_desc.numRecords - s_offset.rawData()) {
632  DPRINTF(VEGA, "mubuf out-of-bounds condition 1: "
633  "lane = %d, buffer_offset = %llx, "
634  "const_stride = %llx, "
635  "const_num_records = %llx\n",
636  lane, buf_off + stride * buf_idx,
637  stride, rsrc_desc.numRecords);
638  oobMask.set(lane);
639  continue;
640  }
641  }
642 
643  if (stride != 0 && rsrc_desc.swizzleEn) {
644  if (buf_idx >= rsrc_desc.numRecords ||
645  buf_off >= stride) {
646  DPRINTF(VEGA, "mubuf out-of-bounds condition 2: "
647  "lane = %d, offset = %llx, "
648  "index = %llx, "
649  "const_num_records = %llx\n",
650  lane, buf_off, buf_idx,
651  rsrc_desc.numRecords);
652  oobMask.set(lane);
653  continue;
654  }
655  }
656 
657  if (rsrc_desc.swizzleEn) {
658  Addr idx_stride = 8 << rsrc_desc.idxStride;
659  Addr elem_size = 2 << rsrc_desc.elemSize;
660  Addr idx_msb = buf_idx / idx_stride;
661  Addr idx_lsb = buf_idx % idx_stride;
662  Addr off_msb = buf_off / elem_size;
663  Addr off_lsb = buf_off % elem_size;
664  DPRINTF(VEGA, "mubuf swizzled lane %d: "
665  "idx_stride = %llx, elem_size = %llx, "
666  "idx_msb = %llx, idx_lsb = %llx, "
667  "off_msb = %llx, off_lsb = %llx\n",
668  lane, idx_stride, elem_size, idx_msb, idx_lsb,
669  off_msb, off_lsb);
670 
671  vaddr += ((idx_msb * stride + off_msb * elem_size)
672  * idx_stride + idx_lsb * elem_size + off_lsb);
673  } else {
674  vaddr += buf_off + stride * buf_idx;
675  }
676 
677  DPRINTF(VEGA, "Calculating mubuf address for lane %d: "
678  "vaddr = %llx, base_addr = %llx, "
679  "stride = %llx, buf_idx = %llx, buf_off = %llx\n",
680  lane, vaddr, base_addr, stride,
681  buf_idx, buf_off);
682  gpuDynInst->addr.at(lane) = vaddr;
683  }
684  }
685  }
686 
687  // first instruction DWORD
689  // second instruction DWORD
691  // Mask of lanes with out-of-bounds accesses. Needs to be tracked
692  // seperately from the exec_mask so that we remember to write zero
693  // to the registers associated with out of bounds lanes.
695  }; // Inst_MUBUF
696 
698  {
699  public:
700  Inst_MTBUF(InFmt_MTBUF*, const std::string &opcode);
701  ~Inst_MTBUF();
702 
703  int instSize() const override;
704  void initOperandInfo() override;
705 
706  protected:
707  // first instruction DWORD
709  // second instruction DWORD
711 
712  private:
713  bool hasSecondDword(InFmt_MTBUF *);
714  }; // Inst_MTBUF
715 
717  {
718  public:
719  Inst_MIMG(InFmt_MIMG*, const std::string &opcode);
720  ~Inst_MIMG();
721 
722  int instSize() const override;
723  void initOperandInfo() override;
724 
725  protected:
726  // first instruction DWORD
728  // second instruction DWORD
730  }; // Inst_MIMG
731 
733  {
734  public:
735  Inst_EXP(InFmt_EXP*, const std::string &opcode);
736  ~Inst_EXP();
737 
738  int instSize() const override;
739  void initOperandInfo() override;
740 
741  protected:
742  // first instruction DWORD
744  // second instruction DWORD
746  }; // Inst_EXP
747 
749  {
750  public:
751  Inst_FLAT(InFmt_FLAT*, const std::string &opcode);
752  ~Inst_FLAT();
753 
754  int instSize() const override;
755  void generateDisassembly() override;
756 
757  void initOperandInfo() override;
758 
759  protected:
760  template<typename T>
761  void
763  {
764  initMemReqHelper<T, 1>(gpuDynInst, MemCmd::ReadReq);
765  }
766 
767  template<int N>
768  void
770  {
771  initMemReqHelper<VecElemU32, N>(gpuDynInst, MemCmd::ReadReq);
772  }
773 
774  template<typename T>
775  void
777  {
778  initMemReqHelper<T, 1>(gpuDynInst, MemCmd::WriteReq);
779  }
780 
781  template<int N>
782  void
784  {
785  initMemReqHelper<VecElemU32, N>(gpuDynInst, MemCmd::WriteReq);
786  }
787 
788  template<typename T>
789  void
791  {
792  initMemReqHelper<T, 1>(gpuDynInst, MemCmd::SwapReq, true);
793  }
794 
795  void
798  {
799  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
800  if (gpuDynInst->exec_mask[lane]) {
801  gpuDynInst->addr.at(lane) = addr[lane] + offset;
802  }
803  }
804  gpuDynInst->resolveFlatSegment(gpuDynInst->exec_mask);
805  }
806 
807  // first instruction DWORD
809  // second instruction DWORD
811  }; // Inst_FLAT
812 } // namespace VegaISA
813 } // namespace gem5
814 
815 #endif // __ARCH_VEGA_INSTS_OP_ENCODINGS_HH__
gem5::VegaISA::Inst_SOPK::extData
InstFormat extData
Definition: op_encodings.hh:111
gem5::VegaISA::Inst_SOP2::instSize
int instSize() const override
Definition: op_encodings.cc:87
gem5::VegaISA::Inst_MUBUF::instSize
int instSize() const override
Definition: op_encodings.cc:1301
gem5::VegaISA::Inst_MUBUF::initMemRead
void initMemRead(GPUDynInstPtr gpuDynInst)
Definition: op_encodings.hh:503
gem5::VegaISA::Inst_MUBUF
Definition: op_encodings.hh:489
gem5::VegaISA::Inst_VOPC::extData
InstFormat extData
Definition: op_encodings.hh:318
gem5::VegaISA::Inst_DS::~Inst_DS
~Inst_DS()
Definition: op_encodings.cc:1164
gem5::VegaISA::InFmt_SMEM
Definition: gpu_decoder.hh:1725
gem5::VegaISA::BufferRsrcDescriptor::baseAddr
uint64_t baseAddr
Definition: op_encodings.hh:52
gem5::VegaISA::Inst_VOP3A::initOperandInfo
void initOperandInfo() override
Definition: op_encodings.cc:941
gem5::VegaISA::Inst_FLAT
Definition: op_encodings.hh:748
gem5::VegaISA::Inst_MIMG::instData
InFmt_MIMG instData
Definition: op_encodings.hh:727
gem5::VegaISA::Inst_MIMG
Definition: op_encodings.hh:716
gem5::VegaISA::Inst_SOP1::Inst_SOP1
Inst_SOP1(InFmt_SOP1 *, const std::string &opcode)
Definition: op_encodings.cc:225
gem5::VegaISA::Inst_SOP2::initOperandInfo
void initOperandInfo() override
Definition: op_encodings.cc:63
gem5::VegaISA::Inst_SOPK::Inst_SOPK
Inst_SOPK(InFmt_SOPK *, const std::string &opcode)
Definition: op_encodings.cc:130
gem5::VegaISA::Inst_MUBUF::instData
InFmt_MUBUF instData
Definition: op_encodings.hh:688
gem5::VegaISA::Inst_SMEM::Inst_SMEM
Inst_SMEM(InFmt_SMEM *, const std::string &opcode)
Definition: op_encodings.cc:481
gem5::VegaISA::Inst_VOP3A::instData
InFmt_VOP3A instData
Definition: op_encodings.hh:351
gem5::VegaISA::Inst_SOPK::instData
InFmt_SOPK instData
Definition: op_encodings.hh:109
gem5::VegaISA::Inst_SOP1::extData
InstFormat extData
Definition: op_encodings.hh:133
gem5::VegaISA::Inst_SOP2
Definition: op_encodings.hh:75
operand.hh
gem5::VegaISA::Inst_SOPK
Definition: op_encodings.hh:96
gem5::VegaISA::VEGAGPUStaticInst
Definition: gpu_static_inst.hh:49
gem5::VegaISA::Inst_VOP2
Definition: op_encodings.hh:259
gpu_static_inst.hh
gem5::MemCmd::SwapReq
@ SwapReq
Definition: packet.hh:115
gem5::VegaISA::Inst_VOP2::initOperandInfo
void initOperandInfo() override
Definition: op_encodings.cc:615
gem5::VegaISA::Inst_VOP3A::sgprDst
const bool sgprDst
the v_cmp and readlane instructions in the VOP3 encoding are unique because they are the only instruc...
Definition: op_encodings.hh:367
gem5::VegaISA::Inst_DS::extData
InFmt_DS_1 extData
Definition: op_encodings.hh:486
gem5::VegaISA::Inst_MIMG::Inst_MIMG
Inst_MIMG(InFmt_MIMG *, const std::string &opcode)
Definition: op_encodings.cc:1399
gem5::VegaISA::Inst_VOP3B::~Inst_VOP3B
~Inst_VOP3B()
Definition: op_encodings.cc:1056
gem5::VegaISA::Inst_DS::calcAddr
void calcAddr(GPUDynInstPtr gpuDynInst, ConstVecOperandU32 &addr)
Definition: op_encodings.hh:472
gem5::VegaISA::Inst_SOP2::instData
InFmt_SOP2 instData
Definition: op_encodings.hh:87
gem5::VegaISA::Inst_SOP2::varSize
uint32_t varSize
Definition: op_encodings.hh:90
gem5::Wavefront::ldsChunk
LdsChunk * ldsChunk
Definition: wavefront.hh:225
gem5::VegaISA::Inst_DS::initMemRead
void initMemRead(GPUDynInstPtr gpuDynInst, Addr offset)
Definition: op_encodings.hh:405
gem5::VegaISA::Inst_VOP2::Inst_VOP2
Inst_VOP2(InFmt_VOP2 *, const std::string &opcode)
Definition: op_encodings.cc:590
gem5::VegaISA::Inst_VINTRP
Definition: op_encodings.hh:325
gem5::Wavefront
Definition: wavefront.hh:62
gem5::VegaISA::Inst_VOPC::Inst_VOPC
Inst_VOPC(InFmt_VOPC *, const std::string &opcode)
Definition: op_encodings.cc:818
gem5::VegaISA::Inst_VOP3A
Definition: op_encodings.hh:338
gem5::VegaISA::Inst_VOP3B::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:1107
gem5::VegaISA::VecOperand
Definition: operand.hh:103
gem5::VegaISA::NumVecElemPerVecReg
const int NumVecElemPerVecReg(64)
gem5::VegaISA::Inst_VOP3B::instSize
int instSize() const override
Definition: op_encodings.cc:1101
gem5::VegaISA::Inst_VOP2::extData
InstFormat extData
Definition: op_encodings.hh:274
gem5::VectorMask
std::bitset< std::numeric_limits< unsigned long long >::digits > VectorMask
Definition: misc.hh:47
gem5::VegaISA::InFmt_SMEM_1
Definition: gpu_decoder.hh:1737
gem5::VegaISA::Inst_SMEM::initMemWrite
void initMemWrite(GPUDynInstPtr gpuDynInst)
initiate a memory write access for N dwords
Definition: op_encodings.hh:206
gem5::VegaISA::ScalarOperand::rawDataPtr
void * rawDataPtr()
Definition: operand.hh:404
gem5::VegaISA::InFmt_VOP3A
Definition: gpu_decoder.hh:1802
gem5::VegaISA::Inst_VOP1::Inst_VOP1
Inst_VOP1(InFmt_VOP1 *, const std::string &opcode)
Definition: op_encodings.cc:725
gem5::VegaISA::Inst_SOPC::hasSecondDword
bool hasSecondDword(InFmt_SOPC *)
Definition: op_encodings.cc:346
gem5::VegaISA::Inst_MIMG::extData
InFmt_MIMG_1 extData
Definition: op_encodings.hh:729
gem5::VegaISA::Inst_VOP3A::Inst_VOP3A
Inst_VOP3A(InFmt_VOP3A *, const std::string &opcode, bool sgpr_dst)
Definition: op_encodings.cc:925
gem5::VegaISA::Inst_SOPC::~Inst_SOPC
~Inst_SOPC()
Definition: op_encodings.cc:318
gem5::VegaISA::InFmt_MIMG
Definition: gpu_decoder.hh:1658
gem5::VegaISA::Inst_MUBUF::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:1307
gem5::VegaISA::Inst_VINTRP::~Inst_VINTRP
~Inst_VINTRP()
Definition: op_encodings.cc:913
gem5::VegaISA::Inst_EXP::instSize
int instSize() const override
Definition: op_encodings.cc:1508
gem5::VegaISA::Inst_VOP3A::instSize
int instSize() const override
Definition: op_encodings.cc:981
gem5::VegaISA::BufferRsrcDescriptor::dstSelW
uint32_t dstSelW
Definition: op_encodings.hh:60
gem5::VegaISA::InFmt_DS
Definition: gpu_decoder.hh:1602
gem5::VegaISA::Inst_SMEM
Definition: op_encodings.hh:178
gem5::VegaISA::Inst_SOPC
Definition: op_encodings.hh:140
gem5::VegaISA::Inst_SOPK::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:203
gem5::VegaISA::Inst_VOP1::~Inst_VOP1
~Inst_VOP1()
Definition: op_encodings.cc:745
gem5::VegaISA::Inst_VOP1::instSize
int instSize() const override
Definition: op_encodings.cc:773
gem5::VegaISA::Inst_VOP3B::initOperandInfo
void initOperandInfo() override
Definition: op_encodings.cc:1061
gem5::VegaISA::Inst_SMEM::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:554
gem5::VegaISA::Inst_SOP1
Definition: op_encodings.hh:118
gem5::VegaISA::Inst_MUBUF::injectGlobalMemFence
void injectGlobalMemFence(GPUDynInstPtr gpuDynInst)
Definition: op_encodings.hh:555
gem5::VegaISA::Inst_VOPC
Definition: op_encodings.hh:303
gem5::VegaISA::Inst_DS
Definition: op_encodings.hh:391
gem5::VegaISA::Inst_SOPP::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:426
gem5::VegaISA::Inst_VOP1
Definition: op_encodings.hh:281
gem5::VegaISA::Inst_VOP2::hasSecondDword
bool hasSecondDword(InFmt_VOP2 *)
Definition: op_encodings.cc:660
gpu_mem_helpers.hh
gem5::VegaISA::Inst_VOP3A::extData
InFmt_VOP3_1 extData
Definition: op_encodings.hh:353
gem5::VegaISA::Inst_FLAT::Inst_FLAT
Inst_FLAT(InFmt_FLAT *, const std::string &opcode)
Definition: op_encodings.cc:1515
gem5::VegaISA::Inst_MUBUF::calcAddr
void calcAddr(GPUDynInstPtr gpuDynInst, VOFF v_off, VIDX v_idx, SRSRC s_rsrc_desc, SOFF s_offset, int inst_offset)
MUBUF insructions calculate their addresses as follows:
Definition: op_encodings.hh:591
gem5::VegaISA::Inst_FLAT::instSize
int instSize() const override
Definition: op_encodings.cc:1574
gem5::VegaISA::BufferRsrcDescriptor::swizzleEn
uint32_t swizzleEn
Definition: op_encodings.hh:55
gem5::VegaISA::Inst_EXP::~Inst_EXP
~Inst_EXP()
Definition: op_encodings.cc:1485
gem5::VegaISA::Inst_SOPC::instData
InFmt_SOPC instData
Definition: op_encodings.hh:153
gem5::VegaISA::Inst_SMEM::initMemRead
void initMemRead(GPUDynInstPtr gpuDynInst)
initiate a memory read access for N dwords
Definition: op_encodings.hh:195
gem5::VegaISA::Inst_MIMG::initOperandInfo
void initOperandInfo() override
Definition: op_encodings.cc:1421
gem5::VegaISA::BufferRsrcDescriptor::hashEn
uint32_t hashEn
Definition: op_encodings.hh:67
gem5::VegaISA::Inst_VINTRP::instData
InFmt_VINTRP instData
Definition: op_encodings.hh:335
gem5::VegaISA::InFmt_MTBUF
Definition: gpu_decoder.hh:1682
gem5::VegaISA::Inst_MTBUF::extData
InFmt_MTBUF_1 extData
Definition: op_encodings.hh:710
gem5::VegaISA::Inst_MUBUF::initMemWrite
void initMemWrite(GPUDynInstPtr gpuDynInst)
Definition: op_encodings.hh:530
gem5::VegaISA::Inst_FLAT::~Inst_FLAT
~Inst_FLAT()
Definition: op_encodings.cc:1532
gem5::GPUStaticInst::opcode
const std::string & opcode() const
Definition: gpu_static_inst.hh:264
gem5::VegaISA::InFmt_SOPP
Definition: gpu_decoder.hh:1772
gem5::VegaISA::InFmt_MUBUF
Definition: gpu_decoder.hh:1703
gem5::VegaISA::BufferRsrcDescriptor::dstSelZ
uint32_t dstSelZ
Definition: op_encodings.hh:59
gem5::VegaISA::Inst_SOPP::Inst_SOPP
Inst_SOPP(InFmt_SOPP *, const std::string &opcode)
Definition: op_encodings.cc:382
gem5::VegaISA::Inst_MIMG::instSize
int instSize() const override
Definition: op_encodings.cc:1468
gem5::VegaISA::Inst_VOPC::~Inst_VOPC
~Inst_VOPC()
Definition: op_encodings.cc:839
gem5::VegaISA::Inst_VOP3A::hasSecondDword
bool hasSecondDword(InFmt_VOP3A *)
gem5::VegaISA::Inst_SOPP::instData
InFmt_SOPP instData
Definition: op_encodings.hh:175
gem5::VegaISA::Inst_SOPK::initOperandInfo
void initOperandInfo() override
Definition: op_encodings.cc:152
gem5::VegaISA::Inst_MTBUF::hasSecondDword
bool hasSecondDword(InFmt_MTBUF *)
gem5::VegaISA::Inst_VOP1::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:798
gem5::VegaISA::BufferRsrcDescriptor::dstSelX
uint32_t dstSelX
Definition: op_encodings.hh:57
gem5::VegaISA::ScalarOperand
Definition: operand.hh:99
gem5::VegaISA::Inst_SOPC::Inst_SOPC
Inst_SOPC(InFmt_SOPC *, const std::string &opcode)
Definition: op_encodings.cc:301
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::VegaISA::InFmt_EXP
Definition: gpu_decoder.hh:1618
gem5::VegaISA::Inst_VOPC::instSize
int instSize() const override
Definition: op_encodings.cc:868
gem5::VegaISA::Inst_VOP2::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:685
gem5::VegaISA::Inst_VOPC::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:893
gem5::VegaISA::Inst_SOP2::Inst_SOP2
Inst_SOP2(InFmt_SOP2 *, const std::string &opcode)
Definition: op_encodings.cc:45
gem5::VegaISA::Inst_SOPC::instSize
int instSize() const override
Definition: op_encodings.cc:340
gem5::VegaISA::Inst_SMEM::calcAddr
void calcAddr(GPUDynInstPtr gpu_dyn_inst, ConstScalarOperandU128 &s_rsrc_desc, ScalarRegU32 offset)
For s_buffer_load_dword/s_buffer_store_dword instruction addresses.
Definition: op_encodings.hh:229
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::VegaISA::Inst_VOP1::extData
InstFormat extData
Definition: op_encodings.hh:296
gem5::VegaISA::InFmt_EXP_1
Definition: gpu_decoder.hh:1628
gem5::VegaISA::Inst_FLAT::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:1580
gem5::MemCmd::ReadReq
@ ReadReq
Definition: packet.hh:86
gem5::VegaISA::BufferRsrcDescriptor::numFmt
uint32_t numFmt
Definition: op_encodings.hh:61
gem5::VegaISA::Inst_DS::initDualMemRead
void initDualMemRead(GPUDynInstPtr gpuDynInst, Addr offset0, Addr offset1)
Definition: op_encodings.hh:421
gem5::VegaISA::BufferRsrcDescriptor::cacheSwizzle
uint32_t cacheSwizzle
Definition: op_encodings.hh:54
gem5::VegaISA::BufferRsrcDescriptor::idxStride
uint32_t idxStride
Definition: op_encodings.hh:64
gem5::VegaISA::InFmt_VINTRP
Definition: gpu_decoder.hh:1778
gem5::VegaISA::Inst_VOP2::instSize
int instSize() const override
Definition: op_encodings.cc:654
gem5::VegaISA::Inst_VOP3A::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:987
gem5::VegaISA::Inst_MUBUF::initOperandInfo
void initOperandInfo() override
Definition: op_encodings.cc:1254
gem5::VegaISA::Inst_MUBUF::Inst_MUBUF
Inst_MUBUF(InFmt_MUBUF *, const std::string &opcode)
Definition: op_encodings.cc:1232
gem5::VegaISA::Inst_FLAT::instData
InFmt_FLAT instData
Definition: op_encodings.hh:808
gem5::ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:144
gem5::VegaISA::Inst_EXP::Inst_EXP
Inst_EXP(InFmt_EXP *, const std::string &opcode)
Definition: op_encodings.cc:1475
gem5::VegaISA::Inst_VOPC::hasSecondDword
bool hasSecondDword(InFmt_VOPC *)
Definition: op_encodings.cc:874
gem5::VegaISA::BufferRsrcDescriptor::elemSize
uint32_t elemSize
Definition: op_encodings.hh:63
gem5::VegaISA::Inst_FLAT::initMemRead
void initMemRead(GPUDynInstPtr gpuDynInst)
Definition: op_encodings.hh:762
gem5::VegaISA::Inst_SOPC::extData
InstFormat extData
Definition: op_encodings.hh:155
gem5::VegaISA::Inst_VOP2::instData
InFmt_VOP2 instData
Definition: op_encodings.hh:272
gem5::VegaISA::Inst_VOP3A::~Inst_VOP3A
~Inst_VOP3A()
Definition: op_encodings.cc:936
gem5::LdsChunk::write
void write(const uint32_t index, const T value)
a write operation
Definition: lds_state.hh:92
gem5::VegaISA::Inst_SMEM::extData
InFmt_SMEM_1 extData
Definition: op_encodings.hh:256
gem5::VegaISA::BufferRsrcDescriptor::addTidEn
uint32_t addTidEn
Definition: op_encodings.hh:65
gem5::VegaISA::Inst_MUBUF::~Inst_MUBUF
~Inst_MUBUF()
Definition: op_encodings.cc:1249
gem5::VegaISA::Inst_FLAT::calcAddr
void calcAddr(GPUDynInstPtr gpuDynInst, ConstVecOperandU64 &addr, ScalarRegU32 offset)
Definition: op_encodings.hh:796
gem5::VegaISA::Inst_VOPC::varSize
uint32_t varSize
Definition: op_encodings.hh:319
gem5::VegaISA::Inst_SOP2::extData
InstFormat extData
Definition: op_encodings.hh:89
gem5::VegaISA::BufferRsrcDescriptor::dataFmt
uint32_t dataFmt
Definition: op_encodings.hh:62
gem5::VegaISA::Inst_VOP2::~Inst_VOP2
~Inst_VOP2()
Definition: op_encodings.cc:610
gem5::VegaISA::Inst_FLAT::initMemWrite
void initMemWrite(GPUDynInstPtr gpuDynInst)
Definition: op_encodings.hh:776
RubySystem.hh
gem5::VegaISA::Inst_VOP3B::instData
InFmt_VOP3B instData
Definition: op_encodings.hh:383
gem5::VegaISA::BufferRsrcDescriptor::numRecords
uint32_t numRecords
Definition: op_encodings.hh:56
gem5::Wavefront::execMask
VectorMask & execMask()
Definition: wavefront.cc:1377
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::VegaISA::BufferRsrcDescriptor
Definition: op_encodings.hh:50
gem5::VegaISA::Inst_EXP
Definition: op_encodings.hh:732
gem5::VegaISA::InFmt_VOP2
Definition: gpu_decoder.hh:1794
gem5::VegaISA::BufferRsrcDescriptor::atc
uint32_t atc
Definition: op_encodings.hh:66
gem5::VegaISA::BufferRsrcDescriptor::dstSelY
uint32_t dstSelY
Definition: op_encodings.hh:58
gem5::VegaISA::Inst_SOP1::initOperandInfo
void initOperandInfo() override
Definition: op_encodings.cc:247
gem5::VegaISA::Inst_SMEM::~Inst_SMEM
~Inst_SMEM()
Definition: op_encodings.cc:497
gem5::GPUDynInstPtr
std::shared_ptr< GPUDynInst > GPUDynInstPtr
Definition: misc.hh:51
gem5::VegaISA::Inst_SOP2::hasSecondDword
bool hasSecondDword(InFmt_SOP2 *)
Definition: op_encodings.cc:93
gpu_decoder.hh
gem5::VegaISA::Inst_SOP2::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:105
gem5::VegaISA::InFmt_SOP2
Definition: gpu_decoder.hh:1750
gem5::VegaISA::Inst_VINTRP::Inst_VINTRP
Inst_VINTRP(InFmt_VINTRP *, const std::string &opcode)
Definition: op_encodings.cc:906
gem5::VegaISA::Inst_SOPK::varSize
uint32_t varSize
Definition: op_encodings.hh:112
gem5::VegaISA::Inst_SOPC::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:358
gem5::VegaISA::Inst_SOP1::instSize
int instSize() const override
Definition: op_encodings.cc:268
gem5::VegaISA::Inst_VOP2::varSize
uint32_t varSize
Definition: op_encodings.hh:275
gem5::VegaISA::Inst_MIMG::~Inst_MIMG
~Inst_MIMG()
Definition: op_encodings.cc:1416
gem5::VegaISA::Inst_MTBUF::instSize
int instSize() const override
Definition: op_encodings.cc:1392
gem5::VegaISA::Inst_FLAT::extData
InFmt_FLAT_1 extData
Definition: op_encodings.hh:810
gem5::VegaISA::Inst_SMEM::calcAddr
void calcAddr(GPUDynInstPtr gpu_dyn_inst, ConstScalarOperandU64 &addr, ScalarRegU32 offset)
For normal s_load_dword/s_store_dword instruction addresses.
Definition: op_encodings.hh:216
gem5::VegaISA::Inst_VOP1::varSize
uint32_t varSize
Definition: op_encodings.hh:297
gem5::VegaISA::Inst_MTBUF::Inst_MTBUF
Inst_MTBUF(InFmt_MTBUF *, const std::string &opcode)
Definition: op_encodings.cc:1326
gem5::VegaISA::Inst_VOP3B::extData
InFmt_VOP3_1 extData
Definition: op_encodings.hh:385
gem5::VegaISA::Inst_SOP1::varSize
uint32_t varSize
Definition: op_encodings.hh:134
gem5::VegaISA::Inst_EXP::instData
InFmt_EXP instData
Definition: op_encodings.hh:743
gem5::VegaISA::InFmt_SOPK
Definition: gpu_decoder.hh:1765
gem5::VegaISA::Inst_SOPP
Definition: op_encodings.hh:162
gem5::VegaISA::Inst_SOPP::~Inst_SOPP
~Inst_SOPP()
Definition: op_encodings.cc:391
gem5::VegaISA::Inst_SOP1::instData
InFmt_SOP1 instData
Definition: op_encodings.hh:131
gem5::VegaISA::InFmt_MUBUF_1
Definition: gpu_decoder.hh:1716
gem5::VegaISA::Inst_VOPC::initOperandInfo
void initOperandInfo() override
Definition: op_encodings.cc:844
gem5::VegaISA::InFmt_MIMG_1
Definition: gpu_decoder.hh:1673
gem5::VegaISA::Inst_FLAT::initAtomicAccess
void initAtomicAccess(GPUDynInstPtr gpuDynInst)
Definition: op_encodings.hh:790
gem5::VegaISA::Inst_VINTRP::instSize
int instSize() const override
Definition: op_encodings.cc:918
gem5::VegaISA::Inst_SOPP::instSize
int instSize() const override
Definition: op_encodings.cc:420
gem5::VegaISA::Inst_SOPC::varSize
uint32_t varSize
Definition: op_encodings.hh:156
gem5::VegaISA::Inst_DS::instSize
int instSize() const override
Definition: op_encodings.cc:1192
gem5::VegaISA::Inst_DS::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:1198
gem5::VegaISA::BufferRsrcDescriptor::mType
uint32_t mType
Definition: op_encodings.hh:69
gem5::VegaISA::Inst_DS::Inst_DS
Inst_DS(InFmt_DS *, const std::string &opcode)
Definition: op_encodings.cc:1152
gem5::VegaISA::Inst_DS::initMemWrite
void initMemWrite(GPUDynInstPtr gpuDynInst, Addr offset)
Definition: op_encodings.hh:440
gem5::VegaISA::InFmt_VOP3_1
Definition: gpu_decoder.hh:1811
gem5::MemCmd::WriteReq
@ WriteReq
Definition: packet.hh:89
gem5::VegaISA::InstFormat
Definition: gpu_decoder.hh:1903
gem5::VegaISA::Inst_SOPK::hasSecondDword
bool hasSecondDword(InFmt_SOPK *)
Definition: op_encodings.cc:186
gem5::VegaISA::Inst_SOPP::initOperandInfo
void initOperandInfo() override
Definition: op_encodings.cc:396
gem5::VegaISA::Inst_MUBUF::oobMask
VectorMask oobMask
Definition: op_encodings.hh:694
gem5::VegaISA::ScalarRegU32
uint32_t ScalarRegU32
Definition: gpu_registers.hh:155
gem5::VegaISA::InFmt_VOP1
Definition: gpu_decoder.hh:1787
gem5::VegaISA::Inst_EXP::extData
InFmt_EXP_1 extData
Definition: op_encodings.hh:745
gem5::VegaISA::BufferRsrcDescriptor::type
uint32_t type
Definition: op_encodings.hh:70
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::VegaISA::Inst_MTBUF::instData
InFmt_MTBUF instData
Definition: op_encodings.hh:708
gem5::VegaISA::InFmt_SOP1
Definition: gpu_decoder.hh:1743
gem5::VegaISA::InFmt_VOPC
Definition: gpu_decoder.hh:1827
gem5::VegaISA::Inst_VOP3B::Inst_VOP3B
Inst_VOP3B(InFmt_VOP3B *, const std::string &opcode)
Definition: op_encodings.cc:1046
gem5::VegaISA::Inst_VOP1::hasSecondDword
bool hasSecondDword(InFmt_VOP1 *)
Definition: op_encodings.cc:779
gem5::VegaISA::Inst_SOP1::hasSecondDword
bool hasSecondDword(InFmt_SOP1 *)
Definition: op_encodings.cc:274
gem5::VegaISA::Inst_VOP1::instData
InFmt_VOP1 instData
Definition: op_encodings.hh:294
gem5::VegaISA::Inst_SOPK::instSize
int instSize() const override
Definition: op_encodings.cc:180
gem5::VegaISA::Inst_MTBUF::~Inst_MTBUF
~Inst_MTBUF()
Definition: op_encodings.cc:1343
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::VegaISA::Inst_SOP1::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:283
gem5::VegaISA::InFmt_DS_1
Definition: gpu_decoder.hh:1611
gem5::VegaISA::InFmt_SOPC
Definition: gpu_decoder.hh:1758
gem5::VegaISA::Inst_DS::instData
InFmt_DS instData
Definition: op_encodings.hh:484
gem5::VegaISA::Inst_VOP1::initOperandInfo
void initOperandInfo() override
Definition: op_encodings.cc:750
gem5::ArmISA::stride
Bitfield< 21, 20 > stride
Definition: misc_types.hh:446
gem5::VegaISA::Inst_SMEM::initOperandInfo
void initOperandInfo() override
Definition: op_encodings.cc:502
gem5::VegaISA::Inst_DS::initDualMemWrite
void initDualMemWrite(GPUDynInstPtr gpuDynInst, Addr offset0, Addr offset1)
Definition: op_encodings.hh:455
gem5::VegaISA::Inst_MUBUF::extData
InFmt_MUBUF_1 extData
Definition: op_encodings.hh:690
gem5::VegaISA::BufferRsrcDescriptor::stride
uint32_t stride
Definition: op_encodings.hh:53
gem5::VegaISA::Inst_VOP3B::hasSecondDword
bool hasSecondDword(InFmt_VOP3B *)
gem5::VegaISA::InFmt_FLAT_1
Definition: gpu_decoder.hh:1646
gem5::VegaISA::Inst_EXP::initOperandInfo
void initOperandInfo() override
Definition: op_encodings.cc:1490
gem5::VegaISA::InFmt_MTBUF_1
Definition: gpu_decoder.hh:1693
gem5::VegaISA::Inst_VOP3B
Definition: op_encodings.hh:370
gem5::VegaISA::Inst_SOPK::~Inst_SOPK
~Inst_SOPK()
Definition: op_encodings.cc:147
gem5::VegaISA::Inst_VOPC::instData
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Definition: op_encodings.hh:316
gem5::VegaISA::Inst_MTBUF::initOperandInfo
void initOperandInfo() override
Definition: op_encodings.cc:1348
gem5::VegaISA::BufferRsrcDescriptor::heap
uint32_t heap
Definition: op_encodings.hh:68
gem5::VegaISA::InFmt_FLAT
Definition: gpu_decoder.hh:1635
gem5::VegaISA::Inst_SOPC::initOperandInfo
void initOperandInfo() override
Definition: op_encodings.cc:323
gem5::VegaISA::Inst_FLAT::initOperandInfo
void initOperandInfo() override
Definition: op_encodings.cc:1537
gem5::VegaISA::Inst_DS::initOperandInfo
void initOperandInfo() override
Definition: op_encodings.cc:1169
gem5::VegaISA::Inst_SMEM::instData
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Definition: op_encodings.hh:254
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Definition: types.hh:84
gem5::VegaISA::InFmt_VOP3B
Definition: gpu_decoder.hh:1819
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Definition: op_encodings.hh:697
gem5::VegaISA::Inst_SMEM::instSize
int instSize() const override
Definition: op_encodings.cc:548
gem5::VegaISA::Inst_SOP1::~Inst_SOP1
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Definition: op_encodings.cc:242
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T read(const uint32_t index)
a read operation
Definition: lds_state.hh:73

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