gem5  v21.2.1.1
op_encodings.hh
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31 
32 #ifndef __ARCH_VEGA_INSTS_OP_ENCODINGS_HH__
33 #define __ARCH_VEGA_INSTS_OP_ENCODINGS_HH__
34 
39 #include "debug/GPUExec.hh"
40 #include "debug/VEGA.hh"
42 
43 namespace gem5
44 {
45 
46 namespace VegaISA
47 {
49  {
50  uint64_t baseAddr : 48;
51  uint32_t stride : 14;
52  uint32_t cacheSwizzle : 1;
53  uint32_t swizzleEn : 1;
54  uint32_t numRecords : 32;
55  uint32_t dstSelX : 3;
56  uint32_t dstSelY : 3;
57  uint32_t dstSelZ : 3;
58  uint32_t dstSelW : 3;
59  uint32_t numFmt : 3;
60  uint32_t dataFmt : 4;
61  uint32_t elemSize : 2;
62  uint32_t idxStride : 2;
63  uint32_t addTidEn : 1;
64  uint32_t atc : 1;
65  uint32_t hashEn : 1;
66  uint32_t heap : 1;
67  uint32_t mType : 3;
68  uint32_t type : 2;
69  };
70 
71  // --- purely virtual instruction classes ---
72 
74  {
75  public:
76  Inst_SOP2(InFmt_SOP2*, const std::string &opcode);
77 
78  int instSize() const override;
79  void generateDisassembly() override;
80 
81  void initOperandInfo() override;
82 
83  protected:
84  // first instruction DWORD
86  // possible second DWORD
88  uint32_t varSize;
89 
90  private:
91  bool hasSecondDword(InFmt_SOP2 *);
92  }; // Inst_SOP2
93 
95  {
96  public:
97  Inst_SOPK(InFmt_SOPK*, const std::string &opcode);
98  ~Inst_SOPK();
99 
100  int instSize() const override;
101  void generateDisassembly() override;
102 
103  void initOperandInfo() override;
104 
105  protected:
106  // first instruction DWORD
108  // possible second DWORD
110  uint32_t varSize;
111 
112  private:
113  bool hasSecondDword(InFmt_SOPK *);
114  }; // Inst_SOPK
115 
117  {
118  public:
119  Inst_SOP1(InFmt_SOP1*, const std::string &opcode);
120  ~Inst_SOP1();
121 
122  int instSize() const override;
123  void generateDisassembly() override;
124 
125  void initOperandInfo() override;
126 
127  protected:
128  // first instruction DWORD
130  // possible second DWORD
132  uint32_t varSize;
133 
134  private:
135  bool hasSecondDword(InFmt_SOP1 *);
136  }; // Inst_SOP1
137 
139  {
140  public:
141  Inst_SOPC(InFmt_SOPC*, const std::string &opcode);
142  ~Inst_SOPC();
143 
144  int instSize() const override;
145  void generateDisassembly() override;
146 
147  void initOperandInfo() override;
148 
149  protected:
150  // first instruction DWORD
152  // possible second DWORD
154  uint32_t varSize;
155 
156  private:
157  bool hasSecondDword(InFmt_SOPC *);
158  }; // Inst_SOPC
159 
161  {
162  public:
163  Inst_SOPP(InFmt_SOPP*, const std::string &opcode);
164  ~Inst_SOPP();
165 
166  int instSize() const override;
167  void generateDisassembly() override;
168 
169  void initOperandInfo() override;
170 
171  protected:
172  // first instruction DWORD
174  }; // Inst_SOPP
175 
177  {
178  public:
179  Inst_SMEM(InFmt_SMEM*, const std::string &opcode);
180  ~Inst_SMEM();
181 
182  int instSize() const override;
183  void generateDisassembly() override;
184 
185  void initOperandInfo() override;
186 
187  protected:
191  template<int N>
192  void
194  {
195  initMemReqScalarHelper<ScalarRegU32, N>(gpuDynInst,
197  }
198 
202  template<int N>
203  void
205  {
206  initMemReqScalarHelper<ScalarRegU32, N>(gpuDynInst,
208  }
209 
213  void
216  {
217  Addr vaddr = ((addr.rawData() + offset) & ~0x3);
218  gpu_dyn_inst->scalarAddr = vaddr;
219  }
220 
226  void
227  calcAddr(GPUDynInstPtr gpu_dyn_inst,
229  {
230  BufferRsrcDescriptor rsrc_desc;
231  ScalarRegU32 clamped_offset(offset);
232  std::memcpy((void*)&rsrc_desc, s_rsrc_desc.rawDataPtr(),
233  sizeof(BufferRsrcDescriptor));
234 
240  if (!rsrc_desc.stride && offset >= rsrc_desc.numRecords) {
241  clamped_offset = rsrc_desc.numRecords;
242  } else if (rsrc_desc.stride && offset
243  > (rsrc_desc.stride * rsrc_desc.numRecords)) {
244  clamped_offset = (rsrc_desc.stride * rsrc_desc.numRecords);
245  }
246 
247  Addr vaddr = ((rsrc_desc.baseAddr + clamped_offset) & ~0x3);
248  gpu_dyn_inst->scalarAddr = vaddr;
249  }
250 
251  // first instruction DWORD
253  // second instruction DWORD
255  }; // Inst_SMEM
256 
258  {
259  public:
260  Inst_VOP2(InFmt_VOP2*, const std::string &opcode);
261  ~Inst_VOP2();
262 
263  int instSize() const override;
264  void generateDisassembly() override;
265 
266  void initOperandInfo() override;
267 
268  protected:
269  // first instruction DWORD
271  // possible second DWORD
273  uint32_t varSize;
274 
275  private:
276  bool hasSecondDword(InFmt_VOP2 *);
277  }; // Inst_VOP2
278 
280  {
281  public:
282  Inst_VOP1(InFmt_VOP1*, const std::string &opcode);
283  ~Inst_VOP1();
284 
285  int instSize() const override;
286  void generateDisassembly() override;
287 
288  void initOperandInfo() override;
289 
290  protected:
291  // first instruction DWORD
293  // possible second DWORD
295  uint32_t varSize;
296 
297  private:
298  bool hasSecondDword(InFmt_VOP1 *);
299  }; // Inst_VOP1
300 
302  {
303  public:
304  Inst_VOPC(InFmt_VOPC*, const std::string &opcode);
305  ~Inst_VOPC();
306 
307  int instSize() const override;
308  void generateDisassembly() override;
309 
310  void initOperandInfo() override;
311 
312  protected:
313  // first instruction DWORD
315  // possible second DWORD
317  uint32_t varSize;
318 
319  private:
320  bool hasSecondDword(InFmt_VOPC *);
321  }; // Inst_VOPC
322 
324  {
325  public:
326  Inst_VINTRP(InFmt_VINTRP*, const std::string &opcode);
327  ~Inst_VINTRP();
328 
329  int instSize() const override;
330 
331  protected:
332  // first instruction DWORD
334  }; // Inst_VINTRP
335 
337  {
338  public:
339  Inst_VOP3A(InFmt_VOP3A*, const std::string &opcode, bool sgpr_dst);
340  ~Inst_VOP3A();
341 
342  int instSize() const override;
343  void generateDisassembly() override;
344 
345  void initOperandInfo() override;
346 
347  protected:
348  // first instruction DWORD
350  // second instruction DWORD
352 
353  private:
354  bool hasSecondDword(InFmt_VOP3A *);
365  const bool sgprDst;
366  }; // Inst_VOP3A
367 
369  {
370  public:
371  Inst_VOP3B(InFmt_VOP3B*, const std::string &opcode);
372  ~Inst_VOP3B();
373 
374  int instSize() const override;
375  void generateDisassembly() override;
376 
377  void initOperandInfo() override;
378 
379  protected:
380  // first instruction DWORD
382  // second instruction DWORD
384 
385  private:
386  bool hasSecondDword(InFmt_VOP3B *);
387  }; // Inst_VOP3B
388 
389  class Inst_DS : public VEGAGPUStaticInst
390  {
391  public:
392  Inst_DS(InFmt_DS*, const std::string &opcode);
393  ~Inst_DS();
394 
395  int instSize() const override;
396  void generateDisassembly() override;
397 
398  void initOperandInfo() override;
399 
400  protected:
401  template<typename T>
402  void
404  {
405  Wavefront *wf = gpuDynInst->wavefront();
406 
407  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
408  if (gpuDynInst->exec_mask[lane]) {
409  Addr vaddr = gpuDynInst->addr[lane] + offset;
410 
411  (reinterpret_cast<T*>(gpuDynInst->d_data))[lane]
412  = wf->ldsChunk->read<T>(vaddr);
413  }
414  }
415  }
416 
417  template<typename T>
418  void
419  initDualMemRead(GPUDynInstPtr gpuDynInst, Addr offset0, Addr offset1)
420  {
421  Wavefront *wf = gpuDynInst->wavefront();
422 
423  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
424  if (gpuDynInst->exec_mask[lane]) {
425  Addr vaddr0 = gpuDynInst->addr[lane] + offset0;
426  Addr vaddr1 = gpuDynInst->addr[lane] + offset1;
427 
428  (reinterpret_cast<T*>(gpuDynInst->d_data))[lane * 2]
429  = wf->ldsChunk->read<T>(vaddr0);
430  (reinterpret_cast<T*>(gpuDynInst->d_data))[lane * 2 + 1]
431  = wf->ldsChunk->read<T>(vaddr1);
432  }
433  }
434  }
435 
436  template<typename T>
437  void
439  {
440  Wavefront *wf = gpuDynInst->wavefront();
441 
442  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
443  if (gpuDynInst->exec_mask[lane]) {
444  Addr vaddr = gpuDynInst->addr[lane] + offset;
445  wf->ldsChunk->write<T>(vaddr,
446  (reinterpret_cast<T*>(gpuDynInst->d_data))[lane]);
447  }
448  }
449  }
450 
451  template<typename T>
452  void
453  initDualMemWrite(GPUDynInstPtr gpuDynInst, Addr offset0, Addr offset1)
454  {
455  Wavefront *wf = gpuDynInst->wavefront();
456 
457  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
458  if (gpuDynInst->exec_mask[lane]) {
459  Addr vaddr0 = gpuDynInst->addr[lane] + offset0;
460  Addr vaddr1 = gpuDynInst->addr[lane] + offset1;
461  wf->ldsChunk->write<T>(vaddr0, (reinterpret_cast<T*>(
462  gpuDynInst->d_data))[lane * 2]);
463  wf->ldsChunk->write<T>(vaddr1, (reinterpret_cast<T*>(
464  gpuDynInst->d_data))[lane * 2 + 1]);
465  }
466  }
467  }
468 
469  void
471  {
472  Wavefront *wf = gpuDynInst->wavefront();
473 
474  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
475  if (wf->execMask(lane)) {
476  gpuDynInst->addr.at(lane) = (Addr)addr[lane];
477  }
478  }
479  }
480 
481  // first instruction DWORD
483  // second instruction DWORD
485  }; // Inst_DS
486 
488  {
489  public:
490  Inst_MUBUF(InFmt_MUBUF*, const std::string &opcode);
491  ~Inst_MUBUF();
492 
493  int instSize() const override;
494  void generateDisassembly() override;
495 
496  void initOperandInfo() override;
497 
498  protected:
499  template<typename T>
500  void
502  {
503  // temporarily modify exec_mask to supress memory accesses to oob
504  // regions. Only issue memory requests for lanes that have their
505  // exec_mask set and are not out of bounds.
506  VectorMask old_exec_mask = gpuDynInst->exec_mask;
507  gpuDynInst->exec_mask &= ~oobMask;
508  initMemReqHelper<T, 1>(gpuDynInst, MemCmd::ReadReq);
509  gpuDynInst->exec_mask = old_exec_mask;
510  }
511 
512 
513  template<int N>
514  void
516  {
517  // temporarily modify exec_mask to supress memory accesses to oob
518  // regions. Only issue memory requests for lanes that have their
519  // exec_mask set and are not out of bounds.
520  VectorMask old_exec_mask = gpuDynInst->exec_mask;
521  gpuDynInst->exec_mask &= ~oobMask;
522  initMemReqHelper<VecElemU32, N>(gpuDynInst, MemCmd::ReadReq);
523  gpuDynInst->exec_mask = old_exec_mask;
524  }
525 
526  template<typename T>
527  void
529  {
530  // temporarily modify exec_mask to supress memory accesses to oob
531  // regions. Only issue memory requests for lanes that have their
532  // exec_mask set and are not out of bounds.
533  VectorMask old_exec_mask = gpuDynInst->exec_mask;
534  gpuDynInst->exec_mask &= ~oobMask;
535  initMemReqHelper<T, 1>(gpuDynInst, MemCmd::WriteReq);
536  gpuDynInst->exec_mask = old_exec_mask;
537  }
538 
539  template<int N>
540  void
542  {
543  // temporarily modify exec_mask to supress memory accesses to oob
544  // regions. Only issue memory requests for lanes that have their
545  // exec_mask set and are not out of bounds.
546  VectorMask old_exec_mask = gpuDynInst->exec_mask;
547  gpuDynInst->exec_mask &= ~oobMask;
548  initMemReqHelper<VecElemU32, N>(gpuDynInst, MemCmd::WriteReq);
549  gpuDynInst->exec_mask = old_exec_mask;
550  }
551 
552  void
554  {
555  // create request and set flags
556  gpuDynInst->resetEntireStatusVector();
557  gpuDynInst->setStatusVector(0, 1);
558  RequestPtr req = std::make_shared<Request>(0, 0, 0,
559  gpuDynInst->computeUnit()->
560  requestorId(), 0,
561  gpuDynInst->wfDynId);
562  gpuDynInst->setRequestFlags(req);
563  gpuDynInst->computeUnit()->
564  injectGlobalMemFence(gpuDynInst, false, req);
565  }
566 
587  template<typename VOFF, typename VIDX, typename SRSRC, typename SOFF>
588  void
589  calcAddr(GPUDynInstPtr gpuDynInst, VOFF v_off, VIDX v_idx,
590  SRSRC s_rsrc_desc, SOFF s_offset, int inst_offset)
591  {
592  Addr vaddr = 0;
593  Addr base_addr = 0;
594  Addr stride = 0;
595  Addr buf_idx = 0;
596  Addr buf_off = 0;
597  BufferRsrcDescriptor rsrc_desc;
598 
599  std::memcpy((void*)&rsrc_desc, s_rsrc_desc.rawDataPtr(),
600  sizeof(BufferRsrcDescriptor));
601 
602  base_addr = rsrc_desc.baseAddr;
603 
604  stride = rsrc_desc.addTidEn ? ((rsrc_desc.dataFmt << 14)
605  + rsrc_desc.stride) : rsrc_desc.stride;
606 
607  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
608  if (gpuDynInst->exec_mask[lane]) {
609  vaddr = base_addr + s_offset.rawData();
615  buf_idx = v_idx[lane] + (rsrc_desc.addTidEn ? lane : 0);
616 
617  buf_off = v_off[lane] + inst_offset;
618 
619 
627  if (stride == 0 || !rsrc_desc.swizzleEn) {
628  if (buf_off + stride * buf_idx >=
629  rsrc_desc.numRecords - s_offset.rawData()) {
630  DPRINTF(VEGA, "mubuf out-of-bounds condition 1: "
631  "lane = %d, buffer_offset = %llx, "
632  "const_stride = %llx, "
633  "const_num_records = %llx\n",
634  lane, buf_off + stride * buf_idx,
635  stride, rsrc_desc.numRecords);
636  oobMask.set(lane);
637  continue;
638  }
639  }
640 
641  if (stride != 0 && rsrc_desc.swizzleEn) {
642  if (buf_idx >= rsrc_desc.numRecords ||
643  buf_off >= stride) {
644  DPRINTF(VEGA, "mubuf out-of-bounds condition 2: "
645  "lane = %d, offset = %llx, "
646  "index = %llx, "
647  "const_num_records = %llx\n",
648  lane, buf_off, buf_idx,
649  rsrc_desc.numRecords);
650  oobMask.set(lane);
651  continue;
652  }
653  }
654 
655  if (rsrc_desc.swizzleEn) {
656  Addr idx_stride = 8 << rsrc_desc.idxStride;
657  Addr elem_size = 2 << rsrc_desc.elemSize;
658  Addr idx_msb = buf_idx / idx_stride;
659  Addr idx_lsb = buf_idx % idx_stride;
660  Addr off_msb = buf_off / elem_size;
661  Addr off_lsb = buf_off % elem_size;
662  DPRINTF(VEGA, "mubuf swizzled lane %d: "
663  "idx_stride = %llx, elem_size = %llx, "
664  "idx_msb = %llx, idx_lsb = %llx, "
665  "off_msb = %llx, off_lsb = %llx\n",
666  lane, idx_stride, elem_size, idx_msb, idx_lsb,
667  off_msb, off_lsb);
668 
669  vaddr += ((idx_msb * stride + off_msb * elem_size)
670  * idx_stride + idx_lsb * elem_size + off_lsb);
671  } else {
672  vaddr += buf_off + stride * buf_idx;
673  }
674 
675  DPRINTF(VEGA, "Calculating mubuf address for lane %d: "
676  "vaddr = %llx, base_addr = %llx, "
677  "stride = %llx, buf_idx = %llx, buf_off = %llx\n",
678  lane, vaddr, base_addr, stride,
679  buf_idx, buf_off);
680  gpuDynInst->addr.at(lane) = vaddr;
681  }
682  }
683  }
684 
685  // first instruction DWORD
687  // second instruction DWORD
689  // Mask of lanes with out-of-bounds accesses. Needs to be tracked
690  // seperately from the exec_mask so that we remember to write zero
691  // to the registers associated with out of bounds lanes.
693  }; // Inst_MUBUF
694 
696  {
697  public:
698  Inst_MTBUF(InFmt_MTBUF*, const std::string &opcode);
699  ~Inst_MTBUF();
700 
701  int instSize() const override;
702  void initOperandInfo() override;
703 
704  protected:
705  // first instruction DWORD
707  // second instruction DWORD
709 
710  private:
711  bool hasSecondDword(InFmt_MTBUF *);
712  }; // Inst_MTBUF
713 
715  {
716  public:
717  Inst_MIMG(InFmt_MIMG*, const std::string &opcode);
718  ~Inst_MIMG();
719 
720  int instSize() const override;
721  void initOperandInfo() override;
722 
723  protected:
724  // first instruction DWORD
726  // second instruction DWORD
728  }; // Inst_MIMG
729 
731  {
732  public:
733  Inst_EXP(InFmt_EXP*, const std::string &opcode);
734  ~Inst_EXP();
735 
736  int instSize() const override;
737  void initOperandInfo() override;
738 
739  protected:
740  // first instruction DWORD
742  // second instruction DWORD
744  }; // Inst_EXP
745 
747  {
748  public:
749  Inst_FLAT(InFmt_FLAT*, const std::string &opcode);
750  ~Inst_FLAT();
751 
752  int instSize() const override;
753  void generateDisassembly() override;
754 
755  void initOperandInfo() override;
756 
757  protected:
758  template<typename T>
759  void
761  {
762  initMemReqHelper<T, 1>(gpuDynInst, MemCmd::ReadReq);
763  }
764 
765  template<int N>
766  void
768  {
769  initMemReqHelper<VecElemU32, N>(gpuDynInst, MemCmd::ReadReq);
770  }
771 
772  template<typename T>
773  void
775  {
776  initMemReqHelper<T, 1>(gpuDynInst, MemCmd::WriteReq);
777  }
778 
779  template<int N>
780  void
782  {
783  initMemReqHelper<VecElemU32, N>(gpuDynInst, MemCmd::WriteReq);
784  }
785 
786  template<typename T>
787  void
789  {
790  initMemReqHelper<T, 1>(gpuDynInst, MemCmd::SwapReq, true);
791  }
792 
793  void
796  {
797  // If saddr = 0x7f there is no scalar reg to read and address will
798  // be a 64-bit address. Otherwise, saddr is the reg index for a
799  // scalar reg used as the base address for a 32-bit address.
800  if ((saddr == 0x7f && isFlatGlobal()) || isFlat()) {
801  calcAddr64(gpuDynInst, vaddr, offset);
802  } else {
803  ConstScalarOperandU32 sbase(gpuDynInst, saddr);
804  sbase.read();
805 
806  calcAddr32(gpuDynInst, vaddr, sbase, offset);
807  }
808 
809  if (isFlat()) {
810  gpuDynInst->resolveFlatSegment(gpuDynInst->exec_mask);
811  }
812  }
813 
814  void
816  {
817  if ((gpuDynInst->executedAs() == enums::SC_GLOBAL && isFlat())
818  || isFlatGlobal()) {
819  gpuDynInst->computeUnit()->globalMemoryPipe
820  .issueRequest(gpuDynInst);
821  } else if (gpuDynInst->executedAs() == enums::SC_GROUP) {
822  assert(isFlat());
823  gpuDynInst->computeUnit()->localMemoryPipe
824  .issueRequest(gpuDynInst);
825  } else {
826  fatal("Unsupported scope for flat instruction.\n");
827  }
828  }
829 
830  // first instruction DWORD
832  // second instruction DWORD
834 
835  private:
836  void initFlatOperandInfo();
837  void initGlobalOperandInfo();
838 
841 
842  void
845  {
846  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
847  if (gpuDynInst->exec_mask[lane]) {
848  gpuDynInst->addr.at(lane) =
849  (vaddr[lane] + saddr.rawData() + offset) & 0xffffffff;
850  }
851  }
852  }
853 
854  void
857  {
858  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
859  if (gpuDynInst->exec_mask[lane]) {
860  gpuDynInst->addr.at(lane) = addr[lane] + offset;
861  }
862  }
863  }
864  }; // Inst_FLAT
865 } // namespace VegaISA
866 } // namespace gem5
867 
868 #endif // __ARCH_VEGA_INSTS_OP_ENCODINGS_HH__
gem5::VegaISA::Inst_SOPK::extData
InstFormat extData
Definition: op_encodings.hh:109
gem5::VegaISA::Inst_SOP2::instSize
int instSize() const override
Definition: op_encodings.cc:85
gem5::VegaISA::Inst_MUBUF::instSize
int instSize() const override
Definition: op_encodings.cc:1298
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:190
gem5::VegaISA::Inst_MUBUF::initMemRead
void initMemRead(GPUDynInstPtr gpuDynInst)
Definition: op_encodings.hh:501
gem5::VegaISA::Inst_MUBUF
Definition: op_encodings.hh:487
gem5::VegaISA::Inst_VOPC::extData
InstFormat extData
Definition: op_encodings.hh:316
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Definition: gpu_decoder.hh:1723
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Definition: op_encodings.hh:50
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Definition: op_encodings.cc:939
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Definition: op_encodings.hh:746
gem5::VegaISA::Inst_MIMG::instData
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Definition: op_encodings.hh:725
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Definition: op_encodings.hh:714
gem5::VegaISA::Inst_SOP1::Inst_SOP1
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Definition: op_encodings.cc:223
gem5::VegaISA::Inst_SOP2::initOperandInfo
void initOperandInfo() override
Definition: op_encodings.cc:61
gem5::VegaISA::Inst_SOPK::Inst_SOPK
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Definition: op_encodings.cc:128
gem5::VegaISA::Inst_MUBUF::instData
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Definition: op_encodings.hh:686
gem5::VegaISA::Inst_SMEM::Inst_SMEM
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Definition: op_encodings.cc:479
gem5::VegaISA::Inst_VOP3A::instData
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Definition: op_encodings.hh:349
gem5::VegaISA::Inst_SOPK::instData
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Definition: op_encodings.hh:107
gem5::VegaISA::Inst_SOP1::extData
InstFormat extData
Definition: op_encodings.hh:131
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Definition: op_encodings.hh:73
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gem5::VegaISA::Inst_FLAT::generateFlatDisassembly
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Definition: op_encodings.hh:94
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Definition: gpu_static_inst.hh:47
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Definition: op_encodings.hh:257
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gem5::GPUStaticInst::isFlat
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Definition: gpu_static_inst.hh:131
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@ SwapReq
Definition: packet.hh:115
gem5::VegaISA::Inst_VOP2::initOperandInfo
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Definition: op_encodings.cc:613
gem5::VegaISA::Inst_VOP3A::sgprDst
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Definition: op_encodings.hh:365
gem5::VegaISA::Inst_DS::extData
InFmt_DS_1 extData
Definition: op_encodings.hh:484
gem5::VegaISA::Inst_MIMG::Inst_MIMG
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Definition: op_encodings.cc:1395
gem5::VegaISA::Inst_VOP3B::~Inst_VOP3B
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Definition: op_encodings.cc:1054
gem5::VegaISA::Inst_DS::calcAddr
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Definition: op_encodings.hh:470
gem5::VegaISA::Inst_SOP2::instData
InFmt_SOP2 instData
Definition: op_encodings.hh:85
gem5::VegaISA::Inst_SOP2::varSize
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Definition: op_encodings.hh:88
gem5::Wavefront::ldsChunk
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Definition: wavefront.hh:223
gem5::VegaISA::Inst_DS::initMemRead
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Definition: op_encodings.hh:403
gem5::VegaISA::Inst_VOP2::Inst_VOP2
Inst_VOP2(InFmt_VOP2 *, const std::string &opcode)
Definition: op_encodings.cc:588
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Definition: op_encodings.hh:323
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Definition: wavefront.hh:60
gem5::VegaISA::Inst_VOPC::Inst_VOPC
Inst_VOPC(InFmt_VOPC *, const std::string &opcode)
Definition: op_encodings.cc:816
gem5::VegaISA::Inst_VOP3A
Definition: op_encodings.hh:336
gem5::VegaISA::Inst_VOP3B::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:1105
gem5::VegaISA::Inst_FLAT::calcAddr
void calcAddr(GPUDynInstPtr gpuDynInst, ConstVecOperandU64 &vaddr, ScalarRegU32 saddr, ScalarRegU32 offset)
Definition: op_encodings.hh:794
gem5::VegaISA::ScalarOperand::rawData
std::enable_if< Condition, DataType >::type rawData() const
we store scalar data in a std::array, however if we need the full operand data we use this method to ...
Definition: operand.hh:391
gem5::VegaISA::VecOperand
Definition: operand.hh:101
gem5::VegaISA::NumVecElemPerVecReg
const int NumVecElemPerVecReg(64)
gem5::VegaISA::Inst_VOP3B::instSize
int instSize() const override
Definition: op_encodings.cc:1099
gem5::VegaISA::Inst_VOP2::extData
InstFormat extData
Definition: op_encodings.hh:272
gem5::VectorMask
std::bitset< std::numeric_limits< unsigned long long >::digits > VectorMask
Definition: misc.hh:45
gem5::VegaISA::InFmt_SMEM_1
Definition: gpu_decoder.hh:1735
gem5::VegaISA::Inst_SMEM::initMemWrite
void initMemWrite(GPUDynInstPtr gpuDynInst)
initiate a memory write access for N dwords
Definition: op_encodings.hh:204
gem5::VegaISA::ScalarOperand::rawDataPtr
void * rawDataPtr()
Definition: operand.hh:402
gem5::VegaISA::InFmt_VOP3A
Definition: gpu_decoder.hh:1800
gem5::VegaISA::Inst_VOP1::Inst_VOP1
Inst_VOP1(InFmt_VOP1 *, const std::string &opcode)
Definition: op_encodings.cc:723
gem5::VegaISA::Inst_SOPC::hasSecondDword
bool hasSecondDword(InFmt_SOPC *)
Definition: op_encodings.cc:344
gem5::VegaISA::Inst_FLAT::initFlatOperandInfo
void initFlatOperandInfo()
Definition: op_encodings.cc:1555
gem5::VegaISA::Inst_MIMG::extData
InFmt_MIMG_1 extData
Definition: op_encodings.hh:727
gem5::VegaISA::Inst_VOP3A::Inst_VOP3A
Inst_VOP3A(InFmt_VOP3A *, const std::string &opcode, bool sgpr_dst)
Definition: op_encodings.cc:923
gem5::VegaISA::Inst_SOPC::~Inst_SOPC
~Inst_SOPC()
Definition: op_encodings.cc:316
gem5::VegaISA::InFmt_MIMG
Definition: gpu_decoder.hh:1656
gem5::VegaISA::Inst_MUBUF::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:1304
gem5::VegaISA::Inst_VINTRP::~Inst_VINTRP
~Inst_VINTRP()
Definition: op_encodings.cc:911
gem5::VegaISA::Inst_EXP::instSize
int instSize() const override
Definition: op_encodings.cc:1503
gem5::VegaISA::Inst_VOP3A::instSize
int instSize() const override
Definition: op_encodings.cc:979
gem5::VegaISA::BufferRsrcDescriptor::dstSelW
uint32_t dstSelW
Definition: op_encodings.hh:58
gem5::VegaISA::InFmt_DS
Definition: gpu_decoder.hh:1600
gem5::GPUStaticInst::isFlatGlobal
bool isFlatGlobal() const
Definition: gpu_static_inst.hh:132
gem5::VegaISA::Inst_SMEM
Definition: op_encodings.hh:176
gem5::VegaISA::Inst_SOPC
Definition: op_encodings.hh:138
gem5::VegaISA::Inst_SOPK::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:201
gem5::VegaISA::Inst_VOP1::~Inst_VOP1
~Inst_VOP1()
Definition: op_encodings.cc:743
gem5::VegaISA::Inst_VOP1::instSize
int instSize() const override
Definition: op_encodings.cc:771
gem5::VegaISA::Inst_VOP3B::initOperandInfo
void initOperandInfo() override
Definition: op_encodings.cc:1059
gem5::VegaISA::Inst_SMEM::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:552
gem5::VegaISA::Inst_SOP1
Definition: op_encodings.hh:116
gem5::VegaISA::Inst_MUBUF::injectGlobalMemFence
void injectGlobalMemFence(GPUDynInstPtr gpuDynInst)
Definition: op_encodings.hh:553
gem5::VegaISA::Inst_VOPC
Definition: op_encodings.hh:301
gem5::VegaISA::Inst_DS
Definition: op_encodings.hh:389
gem5::VegaISA::Inst_SOPP::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:424
gem5::VegaISA::Inst_VOP1
Definition: op_encodings.hh:279
gem5::VegaISA::Inst_VOP2::hasSecondDword
bool hasSecondDword(InFmt_VOP2 *)
Definition: op_encodings.cc:658
gpu_mem_helpers.hh
gem5::VegaISA::Inst_VOP3A::extData
InFmt_VOP3_1 extData
Definition: op_encodings.hh:351
gem5::VegaISA::Inst_FLAT::Inst_FLAT
Inst_FLAT(InFmt_FLAT *, const std::string &opcode)
Definition: op_encodings.cc:1510
gem5::VegaISA::Inst_MUBUF::calcAddr
void calcAddr(GPUDynInstPtr gpuDynInst, VOFF v_off, VIDX v_idx, SRSRC s_rsrc_desc, SOFF s_offset, int inst_offset)
MUBUF insructions calculate their addresses as follows:
Definition: op_encodings.hh:589
gem5::VegaISA::Inst_FLAT::instSize
int instSize() const override
Definition: op_encodings.cc:1652
gem5::VegaISA::BufferRsrcDescriptor::swizzleEn
uint32_t swizzleEn
Definition: op_encodings.hh:53
gem5::VegaISA::Inst_EXP::~Inst_EXP
~Inst_EXP()
Definition: op_encodings.cc:1480
gem5::VegaISA::Inst_SOPC::instData
InFmt_SOPC instData
Definition: op_encodings.hh:151
gem5::VegaISA::Inst_SMEM::initMemRead
void initMemRead(GPUDynInstPtr gpuDynInst)
initiate a memory read access for N dwords
Definition: op_encodings.hh:193
gem5::VegaISA::Inst_MIMG::initOperandInfo
void initOperandInfo() override
Definition: op_encodings.cc:1416
gem5::VegaISA::Inst_FLAT::initGlobalOperandInfo
void initGlobalOperandInfo()
Definition: op_encodings.cc:1592
gem5::VegaISA::BufferRsrcDescriptor::hashEn
uint32_t hashEn
Definition: op_encodings.hh:65
gem5::VegaISA::Inst_VINTRP::instData
InFmt_VINTRP instData
Definition: op_encodings.hh:333
gem5::VegaISA::InFmt_MTBUF
Definition: gpu_decoder.hh:1680
gem5::VegaISA::Inst_MTBUF::extData
InFmt_MTBUF_1 extData
Definition: op_encodings.hh:708
gem5::VegaISA::Inst_MUBUF::initMemWrite
void initMemWrite(GPUDynInstPtr gpuDynInst)
Definition: op_encodings.hh:528
gem5::VegaISA::Inst_FLAT::~Inst_FLAT
~Inst_FLAT()
Definition: op_encodings.cc:1535
gem5::GPUStaticInst::opcode
const std::string & opcode() const
Definition: gpu_static_inst.hh:263
gem5::VegaISA::InFmt_SOPP
Definition: gpu_decoder.hh:1770
gem5::VegaISA::InFmt_MUBUF
Definition: gpu_decoder.hh:1701
gem5::VegaISA::BufferRsrcDescriptor::dstSelZ
uint32_t dstSelZ
Definition: op_encodings.hh:57
gem5::VegaISA::Inst_SOPP::Inst_SOPP
Inst_SOPP(InFmt_SOPP *, const std::string &opcode)
Definition: op_encodings.cc:380
gem5::VegaISA::Inst_MIMG::instSize
int instSize() const override
Definition: op_encodings.cc:1463
gem5::VegaISA::Inst_VOPC::~Inst_VOPC
~Inst_VOPC()
Definition: op_encodings.cc:837
gem5::VegaISA::Inst_VOP3A::hasSecondDword
bool hasSecondDword(InFmt_VOP3A *)
gem5::VegaISA::Inst_SOPP::instData
InFmt_SOPP instData
Definition: op_encodings.hh:173
gem5::VegaISA::Inst_SOPK::initOperandInfo
void initOperandInfo() override
Definition: op_encodings.cc:150
gem5::VegaISA::Inst_MTBUF::hasSecondDword
bool hasSecondDword(InFmt_MTBUF *)
gem5::VegaISA::Inst_VOP1::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:796
gem5::VegaISA::BufferRsrcDescriptor::dstSelX
uint32_t dstSelX
Definition: op_encodings.hh:55
gem5::VegaISA::ScalarOperand
Definition: operand.hh:97
gem5::VegaISA::Inst_SOPC::Inst_SOPC
Inst_SOPC(InFmt_SOPC *, const std::string &opcode)
Definition: op_encodings.cc:299
gem5::VegaISA::Inst_FLAT::calcAddr64
void calcAddr64(GPUDynInstPtr gpuDynInst, ConstVecOperandU64 &addr, ScalarRegU32 offset)
Definition: op_encodings.hh:855
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::VegaISA::InFmt_EXP
Definition: gpu_decoder.hh:1616
gem5::VegaISA::Inst_VOPC::instSize
int instSize() const override
Definition: op_encodings.cc:866
gem5::VegaISA::Inst_VOP2::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:683
gem5::VegaISA::Inst_VOPC::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:891
gem5::VegaISA::Inst_SOP2::Inst_SOP2
Inst_SOP2(InFmt_SOP2 *, const std::string &opcode)
Definition: op_encodings.cc:43
gem5::VegaISA::Inst_SOPC::instSize
int instSize() const override
Definition: op_encodings.cc:338
gem5::VegaISA::Inst_SMEM::calcAddr
void calcAddr(GPUDynInstPtr gpu_dyn_inst, ConstScalarOperandU128 &s_rsrc_desc, ScalarRegU32 offset)
For s_buffer_load_dword/s_buffer_store_dword instruction addresses.
Definition: op_encodings.hh:227
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::VegaISA::Inst_VOP1::extData
InstFormat extData
Definition: op_encodings.hh:294
gem5::VegaISA::InFmt_EXP_1
Definition: gpu_decoder.hh:1626
gem5::VegaISA::Inst_FLAT::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:1658
gem5::MemCmd::ReadReq
@ ReadReq
Definition: packet.hh:86
gem5::VegaISA::BufferRsrcDescriptor::numFmt
uint32_t numFmt
Definition: op_encodings.hh:59
gem5::VegaISA::Inst_DS::initDualMemRead
void initDualMemRead(GPUDynInstPtr gpuDynInst, Addr offset0, Addr offset1)
Definition: op_encodings.hh:419
gem5::VegaISA::BufferRsrcDescriptor::cacheSwizzle
uint32_t cacheSwizzle
Definition: op_encodings.hh:52
gem5::VegaISA::BufferRsrcDescriptor::idxStride
uint32_t idxStride
Definition: op_encodings.hh:62
gem5::VegaISA::InFmt_VINTRP
Definition: gpu_decoder.hh:1776
gem5::VegaISA::Inst_VOP2::instSize
int instSize() const override
Definition: op_encodings.cc:652
gem5::VegaISA::Inst_VOP3A::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:985
gem5::VegaISA::Inst_FLAT::issueRequestHelper
void issueRequestHelper(GPUDynInstPtr gpuDynInst)
Definition: op_encodings.hh:815
gem5::VegaISA::Inst_MUBUF::initOperandInfo
void initOperandInfo() override
Definition: op_encodings.cc:1251
gem5::VegaISA::Inst_MUBUF::Inst_MUBUF
Inst_MUBUF(InFmt_MUBUF *, const std::string &opcode)
Definition: op_encodings.cc:1230
gem5::VegaISA::Inst_FLAT::instData
InFmt_FLAT instData
Definition: op_encodings.hh:831
gem5::ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:144
gem5::VegaISA::Inst_EXP::Inst_EXP
Inst_EXP(InFmt_EXP *, const std::string &opcode)
Definition: op_encodings.cc:1470
gem5::VegaISA::Inst_VOPC::hasSecondDword
bool hasSecondDword(InFmt_VOPC *)
Definition: op_encodings.cc:872
gem5::VegaISA::BufferRsrcDescriptor::elemSize
uint32_t elemSize
Definition: op_encodings.hh:61
gem5::VegaISA::Inst_FLAT::initMemRead
void initMemRead(GPUDynInstPtr gpuDynInst)
Definition: op_encodings.hh:760
gem5::VegaISA::Inst_SOPC::extData
InstFormat extData
Definition: op_encodings.hh:153
gem5::VegaISA::Inst_VOP2::instData
InFmt_VOP2 instData
Definition: op_encodings.hh:270
gem5::VegaISA::Inst_VOP3A::~Inst_VOP3A
~Inst_VOP3A()
Definition: op_encodings.cc:934
gem5::LdsChunk::write
void write(const uint32_t index, const T value)
a write operation
Definition: lds_state.hh:90
gem5::VegaISA::Inst_SMEM::extData
InFmt_SMEM_1 extData
Definition: op_encodings.hh:254
gem5::VegaISA::BufferRsrcDescriptor::addTidEn
uint32_t addTidEn
Definition: op_encodings.hh:63
gem5::VegaISA::Inst_MUBUF::~Inst_MUBUF
~Inst_MUBUF()
Definition: op_encodings.cc:1246
gem5::VegaISA::Inst_VOPC::varSize
uint32_t varSize
Definition: op_encodings.hh:317
gem5::VegaISA::Inst_SOP2::extData
InstFormat extData
Definition: op_encodings.hh:87
gem5::VegaISA::BufferRsrcDescriptor::dataFmt
uint32_t dataFmt
Definition: op_encodings.hh:60
gem5::VegaISA::Inst_VOP2::~Inst_VOP2
~Inst_VOP2()
Definition: op_encodings.cc:608
gem5::VegaISA::Inst_FLAT::initMemWrite
void initMemWrite(GPUDynInstPtr gpuDynInst)
Definition: op_encodings.hh:774
RubySystem.hh
gem5::VegaISA::Inst_VOP3B::instData
InFmt_VOP3B instData
Definition: op_encodings.hh:381
gem5::VegaISA::BufferRsrcDescriptor::numRecords
uint32_t numRecords
Definition: op_encodings.hh:54
gem5::Wavefront::execMask
VectorMask & execMask()
Definition: wavefront.cc:1375
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::VegaISA::BufferRsrcDescriptor
Definition: op_encodings.hh:48
gem5::VegaISA::Inst_EXP
Definition: op_encodings.hh:730
gem5::VegaISA::InFmt_VOP2
Definition: gpu_decoder.hh:1792
gem5::VegaISA::BufferRsrcDescriptor::atc
uint32_t atc
Definition: op_encodings.hh:64
gem5::VegaISA::BufferRsrcDescriptor::dstSelY
uint32_t dstSelY
Definition: op_encodings.hh:56
gem5::VegaISA::Inst_SOP1::initOperandInfo
void initOperandInfo() override
Definition: op_encodings.cc:245
gem5::VegaISA::Inst_SMEM::~Inst_SMEM
~Inst_SMEM()
Definition: op_encodings.cc:495
gem5::GPUDynInstPtr
std::shared_ptr< GPUDynInst > GPUDynInstPtr
Definition: misc.hh:49
gem5::VegaISA::Inst_SOP2::hasSecondDword
bool hasSecondDword(InFmt_SOP2 *)
Definition: op_encodings.cc:91
gpu_decoder.hh
gem5::VegaISA::Inst_SOP2::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:103
gem5::VegaISA::InFmt_SOP2
Definition: gpu_decoder.hh:1748
gem5::VegaISA::Inst_VINTRP::Inst_VINTRP
Inst_VINTRP(InFmt_VINTRP *, const std::string &opcode)
Definition: op_encodings.cc:904
gem5::VegaISA::Inst_SOPK::varSize
uint32_t varSize
Definition: op_encodings.hh:110
gem5::VegaISA::Inst_SOPC::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:356
gem5::VegaISA::Inst_SOP1::instSize
int instSize() const override
Definition: op_encodings.cc:266
gem5::VegaISA::Inst_VOP2::varSize
uint32_t varSize
Definition: op_encodings.hh:273
gem5::VegaISA::Inst_MIMG::~Inst_MIMG
~Inst_MIMG()
Definition: op_encodings.cc:1411
gem5::VegaISA::Inst_MTBUF::instSize
int instSize() const override
Definition: op_encodings.cc:1388
gem5::VegaISA::ScalarOperand::read
void read() override
Definition: operand.hh:408
gem5::VegaISA::Inst_FLAT::extData
InFmt_FLAT_1 extData
Definition: op_encodings.hh:833
gem5::VegaISA::Inst_SMEM::calcAddr
void calcAddr(GPUDynInstPtr gpu_dyn_inst, ConstScalarOperandU64 &addr, ScalarRegU32 offset)
For normal s_load_dword/s_store_dword instruction addresses.
Definition: op_encodings.hh:214
gem5::VegaISA::Inst_VOP1::varSize
uint32_t varSize
Definition: op_encodings.hh:295
gem5::VegaISA::Inst_MTBUF::Inst_MTBUF
Inst_MTBUF(InFmt_MTBUF *, const std::string &opcode)
Definition: op_encodings.cc:1323
gem5::VegaISA::Inst_VOP3B::extData
InFmt_VOP3_1 extData
Definition: op_encodings.hh:383
gem5::VegaISA::Inst_SOP1::varSize
uint32_t varSize
Definition: op_encodings.hh:132
gem5::VegaISA::Inst_EXP::instData
InFmt_EXP instData
Definition: op_encodings.hh:741
gem5::VegaISA::InFmt_SOPK
Definition: gpu_decoder.hh:1763
gem5::VegaISA::Inst_SOPP
Definition: op_encodings.hh:160
gem5::VegaISA::Inst_SOPP::~Inst_SOPP
~Inst_SOPP()
Definition: op_encodings.cc:389
gem5::VegaISA::Inst_FLAT::calcAddr32
void calcAddr32(GPUDynInstPtr gpuDynInst, ConstVecOperandU64 &vaddr, ConstScalarOperandU32 &saddr, ScalarRegU32 offset)
Definition: op_encodings.hh:843
gem5::VegaISA::Inst_SOP1::instData
InFmt_SOP1 instData
Definition: op_encodings.hh:129
gem5::VegaISA::InFmt_MUBUF_1
Definition: gpu_decoder.hh:1714
gem5::VegaISA::Inst_VOPC::initOperandInfo
void initOperandInfo() override
Definition: op_encodings.cc:842
gem5::VegaISA::InFmt_MIMG_1
Definition: gpu_decoder.hh:1671
gem5::VegaISA::Inst_FLAT::initAtomicAccess
void initAtomicAccess(GPUDynInstPtr gpuDynInst)
Definition: op_encodings.hh:788
gem5::VegaISA::Inst_VINTRP::instSize
int instSize() const override
Definition: op_encodings.cc:916
gem5::VegaISA::Inst_SOPP::instSize
int instSize() const override
Definition: op_encodings.cc:418
gem5::VegaISA::Inst_SOPC::varSize
uint32_t varSize
Definition: op_encodings.hh:154
gem5::VegaISA::Inst_DS::instSize
int instSize() const override
Definition: op_encodings.cc:1190
gem5::VegaISA::Inst_DS::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:1196
gem5::VegaISA::BufferRsrcDescriptor::mType
uint32_t mType
Definition: op_encodings.hh:67
gem5::VegaISA::Inst_DS::Inst_DS
Inst_DS(InFmt_DS *, const std::string &opcode)
Definition: op_encodings.cc:1150
gem5::VegaISA::Inst_DS::initMemWrite
void initMemWrite(GPUDynInstPtr gpuDynInst, Addr offset)
Definition: op_encodings.hh:438
gem5::VegaISA::InFmt_VOP3_1
Definition: gpu_decoder.hh:1809
gem5::MemCmd::WriteReq
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Definition: packet.hh:89
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Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
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