gem5  v21.1.0.2
tlb.hh
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37 
38 #ifndef __ARCH_X86_TLB_HH__
39 #define __ARCH_X86_TLB_HH__
40 
41 #include <list>
42 #include <vector>
43 
44 #include "arch/generic/tlb.hh"
45 #include "arch/x86/pagetable.hh"
46 #include "base/trie.hh"
47 #include "mem/request.hh"
48 #include "params/X86TLB.hh"
49 #include "sim/stats.hh"
50 
51 namespace gem5
52 {
53 
54 class ThreadContext;
55 
56 namespace X86ISA
57 {
58  class Walker;
59 
60  class TLB : public BaseTLB
61  {
62  protected:
63  friend class Walker;
64 
66 
67  uint32_t configAddress;
68 
69  public:
70 
71  typedef X86TLBParams Params;
72  TLB(const Params &p);
73 
74  void takeOverFrom(BaseTLB *otlb) override {}
75 
76  TlbEntry *lookup(Addr va, bool update_lru = true);
77 
78  void setConfigAddress(uint32_t addr);
79 
80  protected:
81 
82  EntryList::iterator lookupIt(Addr va, bool update_lru = true);
83 
85 
86  public:
87  Walker *getWalker();
88 
89  void flushAll() override;
90 
91  void flushNonGlobal();
92 
93  void demapPage(Addr va, uint64_t asn) override;
94 
95  protected:
96  uint32_t size;
97 
99 
101 
103  uint64_t lruSeq;
104 
106 
107  struct TlbStats : public statistics::Group
108  {
109  TlbStats(statistics::Group *parent);
110 
115  } stats;
116 
117  Fault translateInt(bool read, RequestPtr req, ThreadContext *tc);
118 
119  Fault translate(const RequestPtr &req, ThreadContext *tc,
121  bool &delayedResponse, bool timing);
122 
123  public:
124 
125  void evictLRU();
126 
127  uint64_t
129  {
130  return ++lruSeq;
131  }
132 
134  const RequestPtr &req, ThreadContext *tc,
135  BaseMMU::Mode mode) override;
137  const RequestPtr &req, ThreadContext *tc,
138  BaseMMU::Mode mode) override;
139  void translateTiming(
140  const RequestPtr &req, ThreadContext *tc,
141  BaseMMU::Translation *translation, BaseMMU::Mode mode) override;
142 
157  BaseMMU::Mode mode) const override;
158 
159  TlbEntry *insert(Addr vpn, const TlbEntry &entry);
160 
161  // Checkpointing
162  void serialize(CheckpointOut &cp) const override;
163  void unserialize(CheckpointIn &cp) override;
164 
175  Port *getTableWalkerPort() override;
176  };
177 
178 } // namespace X86ISA
179 } // namespace gem5
180 
181 #endif // __ARCH_X86_TLB_HH__
gem5::X86ISA::TLB::lookupIt
EntryList::iterator lookupIt(Addr va, bool update_lru=true)
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1927
pagetable.hh
gem5::X86ISA::TLB::tlb
std::vector< TlbEntry > tlb
Definition: tlb.hh:98
gem5::X86ISA::TLB::TLB
TLB(const Params &p)
Definition: tlb.cc:65
gem5::X86ISA::TLB::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: tlb.cc:556
gem5::X86ISA::TLB::TlbStats
Definition: tlb.hh:107
gem5::X86ISA::TLB::translateTiming
void translateTiming(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode) override
Definition: tlb.cc:508
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:53
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::X86ISA::TLB::translateAtomic
Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override
Definition: tlb.cc:465
tlb.hh
gem5::X86ISA::TLB::getWalker
Walker * getWalker()
Definition: tlb.cc:88
gem5::X86ISA::TLB::flushNonGlobal
void flushNonGlobal()
Definition: tlb.cc:152
gem5::X86ISA::TLB::TlbStats::rdMisses
statistics::Scalar rdMisses
Definition: tlb.hh:113
std::vector
STL vector class.
Definition: stl.hh:37
gem5::X86ISA::Walker
Definition: pagetable_walker.hh:60
gem5::X86ISA::TLB::takeOverFrom
void takeOverFrom(BaseTLB *otlb) override
Take over from an old tlb context.
Definition: tlb.hh:74
request.hh
gem5::X86ISA::TLB::translateInt
Fault translateInt(bool read, RequestPtr req, ThreadContext *tc)
Definition: tlb.cc:198
gem5::X86ISA::TLB::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: tlb.cc:541
gem5::X86ISA::TLB::translateFunctional
Fault translateFunctional(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override
Definition: tlb.cc:473
gem5::X86ISA::TlbEntry
Definition: pagetable.hh:65
gem5::X86ISA::TLB::finalizePhysical
Fault finalizePhysical(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) const override
Do post-translation physical address finalization.
Definition: tlb.cc:261
gem5::X86ISA::TLB::freeList
EntryList freeList
Definition: tlb.hh:100
gem5::Trie< Addr, TlbEntry >
stats.hh
gem5::X86ISA::TLB::setConfigAddress
void setConfigAddress(uint32_t addr)
Definition: tlb.cc:146
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::BaseTLB
Definition: tlb.hh:54
gem5::X86ISA::TLB::trie
TlbEntryTrie trie
Definition: tlb.hh:102
gem5::X86ISA::TLB::stats
gem5::X86ISA::TLB::TlbStats stats
gem5::X86ISA::TLB::TlbStats::wrMisses
statistics::Scalar wrMisses
Definition: tlb.hh:114
gem5::X86ISA::TLB::m5opRange
AddrRange m5opRange
Definition: tlb.hh:105
gem5::X86ISA::TLB::translate
Fault translate(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode, bool &delayedResponse, bool timing)
Definition: tlb.cc:310
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::TLB::lookup
TlbEntry * lookup(Addr va, bool update_lru=true)
Definition: tlb.cc:124
gem5::X86ISA::TLB::demapPage
void demapPage(Addr va, uint64_t asn) override
Definition: tlb.cc:165
gem5::ArmISA::va
Bitfield< 8 > va
Definition: misc_types.hh:275
gem5::X86ISA::TLB::insert
TlbEntry * insert(Addr vpn, const TlbEntry &entry)
Definition: tlb.cc:143
gem5::X86ISA::TLB::EntryList
std::list< TlbEntry * > EntryList
Definition: tlb.hh:65
gem5::X86ISA::TLB::evictLRU
void evictLRU()
Definition: tlb.cc:94
gem5::BaseMMU::Translation
Definition: mmu.hh:55
gem5::X86ISA::TLB::TlbStats::rdAccesses
statistics::Scalar rdAccesses
Definition: tlb.hh:111
gem5::X86ISA::TLB::TlbStats::TlbStats
TlbStats(statistics::Group *parent)
Definition: tlb.cc:488
gem5::X86ISA::TLB
Definition: tlb.hh:60
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::X86ISA::TLB::configAddress
uint32_t configAddress
Definition: tlb.hh:67
gem5::X86ISA::TLB::flushAll
void flushAll() override
Remove all entries from the TLB.
Definition: tlb.cc:133
gem5::X86ISA::TLB::Params
X86TLBParams Params
Definition: tlb.hh:71
gem5::X86ISA::TLB::getTableWalkerPort
Port * getTableWalkerPort() override
Get the table walker port.
Definition: tlb.cc:578
gem5::X86ISA::TLB::lruSeq
uint64_t lruSeq
Definition: tlb.hh:103
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::X86ISA::TLB::TlbStats::wrAccesses
statistics::Scalar wrAccesses
Definition: tlb.hh:112
gem5::X86ISA::TLB::walker
Walker * walker
Definition: tlb.hh:84
gem5::X86ISA::p
Bitfield< 0 > p
Definition: pagetable.hh:151
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::AddrRange
The AddrRange class encapsulates an address range, and supports a number of tests to check if two ran...
Definition: addr_range.hh:71
std::list< TlbEntry * >
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::X86ISA::TLB::size
uint32_t size
Definition: tlb.hh:96
gem5::X86ISA::TLB::nextSeq
uint64_t nextSeq()
Definition: tlb.hh:128
trie.hh
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:73
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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