gem5  v21.1.0.2
process.cc
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28 
29 #include "arch/sparc/process.hh"
30 
31 #include "arch/sparc/asi.hh"
32 #include "arch/sparc/handlers.hh"
33 #include "arch/sparc/page_size.hh"
34 #include "arch/sparc/regs/int.hh"
35 #include "arch/sparc/regs/misc.hh"
36 #include "arch/sparc/types.hh"
39 #include "base/logging.hh"
40 #include "cpu/thread_context.hh"
41 #include "debug/Stack.hh"
42 #include "mem/page_table.hh"
43 #include "params/Process.hh"
44 #include "sim/aux_vector.hh"
45 #include "sim/byteswap.hh"
46 #include "sim/process_impl.hh"
47 #include "sim/syscall_return.hh"
48 #include "sim/system.hh"
49 
50 namespace gem5
51 {
52 
53 using namespace SparcISA;
54 
55 SparcProcess::SparcProcess(const ProcessParams &params,
56  loader::ObjectFile *objFile, Addr _StackBias)
57  : Process(params,
58  new EmulationPageTable(params.name, params.pid, PageBytes),
59  objFile),
60  StackBias(_StackBias)
61 {
62  fatal_if(params.useArchPT, "Arch page tables not implemented.");
63  // Initialize these to 0s
64  fillStart = 0;
65  spillStart = 0;
66 }
67 
68 void
70 {
72 
74  // From the SPARC ABI
75 
76  // Setup default FP state
78 
80 
81  /*
82  * Register window management registers
83  */
84 
85  // No windows contain info from other programs
86  tc->setIntReg(INTREG_OTHERWIN, 0);
87  // There are no windows to pop
89  // All windows are available to save into
91  // All windows are "clean"
93  // Start with register window 0
94  tc->setMiscReg(MISCREG_CWP, 0);
95  // Always use spill and fill traps 0
96  tc->setIntReg(INTREG_WSTATE, 0);
97  // Set the trap level to 0
99  // Set the ASI register to something fixed
101 
102  // Set the MMU Primary Context Register to hold the process' pid
104 
105  /*
106  * T1 specific registers
107  */
108  // Turn on the icache, dcache, dtb translation, and itb translation.
110 }
111 
112 void
114 {
116 
118  // The process runs in user mode with 32 bit addresses
119  PSTATE pstate = 0;
120  pstate.ie = 1;
121  pstate.am = 1;
122  tc->setMiscReg(MISCREG_PSTATE, pstate);
123 
124  argsInit(32 / 8, PageBytes);
125 }
126 
127 void
129 {
131 
133  // The process runs in user mode
134  PSTATE pstate = 0;
135  pstate.ie = 1;
136  tc->setMiscReg(MISCREG_PSTATE, pstate);
137 
138  argsInit(sizeof(RegVal), PageBytes);
139 }
140 
141 template<class IntType>
142 void
144 {
145  int intSize = sizeof(IntType);
146 
148 
149  std::string filename;
150  if (argv.size() < 1)
151  filename = "";
152  else
153  filename = argv[0];
154 
155  // Even for a 32 bit process, the ABI says we still need to
156  // maintain double word alignment of the stack pointer.
157  uint64_t align = 16;
158 
159  enum HardwareCaps
160  {
161  HwcapSparcFlush = 1,
162  HwcapSparcStbar = 2,
163  HwcapSparcSwap = 4,
164  HwcapSparcMuldiv = 8,
165  HwcapSparcV9 = 16,
166  // This one should technically only be set
167  // if there is a cheetah or cheetah_plus tlb,
168  // but we'll use it all the time
169  HwcapSparcUltra3 = 32
170  };
171 
172  const int64_t hwcap =
173  HwcapSparcFlush |
174  HwcapSparcStbar |
175  HwcapSparcSwap |
176  HwcapSparcMuldiv |
177  HwcapSparcV9 |
178  HwcapSparcUltra3;
179 
180  // Setup the auxilliary vectors. These will already have endian conversion.
181  // Auxilliary vectors are loaded only for elf formatted executables.
182  auto *elfObject = dynamic_cast<loader::ElfObject *>(objFile);
183  if (elfObject) {
184  // Bits which describe the system hardware capabilities
185  auxv.emplace_back(gem5::auxv::Hwcap, hwcap);
186  // The system page size
187  auxv.emplace_back(gem5::auxv::Pagesz, SparcISA::PageBytes);
188  // Defined to be 100 in the kernel source.
189  // Frequency at which times() increments
190  auxv.emplace_back(gem5::auxv::Clktck, 100);
191  // For statically linked executables, this is the virtual address of
192  // the program header tables if they appear in the executable image
193  auxv.emplace_back(gem5::auxv::Phdr, elfObject->programHeaderTable());
194  // This is the size of a program header entry from the elf file.
195  auxv.emplace_back(gem5::auxv::Phent, elfObject->programHeaderSize());
196  // This is the number of program headers from the original elf file.
197  auxv.emplace_back(gem5::auxv::Phnum, elfObject->programHeaderCount());
198  // This is the base address of the ELF interpreter; it should be
199  // zero for static executables or contain the base address for
200  // dynamic executables.
201  auxv.emplace_back(gem5::auxv::Base, getBias());
202  // This is hardwired to 0 in the elf loading code in the kernel
203  auxv.emplace_back(gem5::auxv::Flags, 0);
204  // The entry point to the program
205  auxv.emplace_back(gem5::auxv::Entry, objFile->entryPoint());
206  // Different user and group IDs
207  auxv.emplace_back(gem5::auxv::Uid, uid());
208  auxv.emplace_back(gem5::auxv::Euid, euid());
209  auxv.emplace_back(gem5::auxv::Gid, gid());
210  auxv.emplace_back(gem5::auxv::Egid, egid());
211  // Whether to enable "secure mode" in the executable
212  auxv.emplace_back(gem5::auxv::Secure, 0);
213  // The address of 16 "random" bytes.
214  auxv.emplace_back(gem5::auxv::Random, 0);
215  }
216 
217  // Figure out how big the initial stack needs to be
218 
219  // The unaccounted for 8 byte 0 at the top of the stack
220  int sentry_size = 8;
221 
222  // This is the name of the file which is present on the initial stack
223  // It's purpose is to let the user space linker examine the original file.
224  int file_name_size = filename.size() + 1;
225 
226  const int numRandomBytes = 16;
227  int aux_data_size = numRandomBytes;
228 
229  int env_data_size = 0;
230  for (int i = 0; i < envp.size(); ++i) {
231  env_data_size += envp[i].size() + 1;
232  }
233  int arg_data_size = 0;
234  for (int i = 0; i < argv.size(); ++i) {
235  arg_data_size += argv[i].size() + 1;
236  }
237 
238  // The info_block.
239  int base_info_block_size =
240  sentry_size + file_name_size + env_data_size + arg_data_size;
241 
242  int info_block_size = roundUp(base_info_block_size, align);
243 
244  int info_block_padding = info_block_size - base_info_block_size;
245 
246  // Each auxilliary vector is two words
247  int aux_array_size = intSize * 2 * (auxv.size() + 1);
248 
249  int envp_array_size = intSize * (envp.size() + 1);
250  int argv_array_size = intSize * (argv.size() + 1);
251 
252  int argc_size = intSize;
253  int window_save_size = intSize * 16;
254 
255  // Figure out the size of the contents of the actual initial frame
256  int frame_size =
257  aux_array_size +
258  envp_array_size +
259  argv_array_size +
260  argc_size +
261  window_save_size;
262 
263  // There needs to be padding after the auxiliary vector data so that the
264  // very bottom of the stack is aligned properly.
265  int aligned_partial_size = roundUp(frame_size, align);
266  int aux_padding = aligned_partial_size - frame_size;
267 
268  int space_needed =
269  info_block_size +
270  aux_data_size +
271  aux_padding +
272  frame_size;
273 
274  memState->setStackMin(memState->getStackBase() - space_needed);
275  memState->setStackMin(roundDown(memState->getStackMin(), align));
276  memState->setStackSize(memState->getStackBase() - memState->getStackMin());
277 
278  // Allocate space for the stack
279  memState->mapRegion(roundDown(memState->getStackMin(), pageSize),
280  roundUp(memState->getStackSize(), pageSize), "stack");
281 
282  // map out initial stack contents
283  IntType sentry_base = memState->getStackBase() - sentry_size;
284  IntType file_name_base = sentry_base - file_name_size;
285  IntType env_data_base = file_name_base - env_data_size;
286  IntType arg_data_base = env_data_base - arg_data_size;
287  IntType aux_data_base = arg_data_base - info_block_padding - aux_data_size;
288  IntType auxv_array_base = aux_data_base - aux_array_size - aux_padding;
289  IntType envp_array_base = auxv_array_base - envp_array_size;
290  IntType argv_array_base = envp_array_base - argv_array_size;
291  IntType argc_base = argv_array_base - argc_size;
292  IntType window_save_base = argc_base - window_save_size;
293 
294  DPRINTF(Stack, "The addresses of items on the initial stack:\n");
295  DPRINTF(Stack, "%#x - sentry NULL\n", sentry_base);
296  DPRINTF(Stack, "filename = %s\n", filename);
297  DPRINTF(Stack, "%#x - file name\n", file_name_base);
298  DPRINTF(Stack, "%#x - env data\n", env_data_base);
299  DPRINTF(Stack, "%#x - arg data\n", arg_data_base);
300  DPRINTF(Stack, "%#x - auxv array\n", auxv_array_base);
301  DPRINTF(Stack, "%#x - envp array\n", envp_array_base);
302  DPRINTF(Stack, "%#x - argv array\n", argv_array_base);
303  DPRINTF(Stack, "%#x - argc \n", argc_base);
304  DPRINTF(Stack, "%#x - window save\n", window_save_base);
305  DPRINTF(Stack, "%#x - stack min\n", memState->getStackMin());
306 
307  assert(window_save_base == memState->getStackMin());
308 
309  // write contents to stack
310 
311  // figure out argc
312  IntType argc = argv.size();
313  IntType guestArgc = htobe(argc);
314 
315  // Write out the sentry void *
316  uint64_t sentry_NULL = 0;
317  initVirtMem->writeBlob(sentry_base, &sentry_NULL, sentry_size);
318 
319  // Write the file name
320  initVirtMem->writeString(file_name_base, filename.c_str());
321 
322  // Fix up the aux vectors which point to data.
323  for (auto &aux: auxv) {
324  if (aux.type == gem5::auxv::Random)
325  aux.val = aux_data_base;
326  }
327 
328  // Copy the aux stuff
329  Addr auxv_array_end = auxv_array_base;
330  for (const auto &aux: auxv) {
331  initVirtMem->write(auxv_array_end, aux, ByteOrder::big);
332  auxv_array_end += sizeof(aux);
333  }
334 
335  // Write out the terminating zeroed auxilliary vector
336  const gem5::auxv::AuxVector<IntType> zero(0, 0);
337  initVirtMem->write(auxv_array_end, zero);
338  auxv_array_end += sizeof(zero);
339 
340  copyStringArray(envp, envp_array_base, env_data_base,
341  ByteOrder::big, *initVirtMem);
342  copyStringArray(argv, argv_array_base, arg_data_base,
343  ByteOrder::big, *initVirtMem);
344 
345  initVirtMem->writeBlob(argc_base, &guestArgc, intSize);
346 
347  // Set up space for the trap handlers into the processes address space.
348  // Since the stack grows down and there is reserved address space abov
349  // it, we can put stuff above it and stay out of the way.
350  fillStart = memState->getStackBase();
352 
354  // Set up the thread context to start running the process
355  // assert(NumArgumentRegs >= 2);
356  // tc->setIntReg(ArgumentReg[0], argc);
357  // tc->setIntReg(ArgumentReg[1], argv_array_base);
358  tc->setIntReg(StackPointerReg, memState->getStackMin() - StackBias);
359 
360  // %g1 is a pointer to a function that should be run at exit. Since we
361  // don't have anything like that, it should be set to 0.
362  tc->setIntReg(1, 0);
363 
364  tc->pcState(getStartPC());
365 
366  // Align the "stack_min" to a page boundary.
367  memState->setStackMin(roundDown(memState->getStackMin(), pageSize));
368 }
369 
370 void
371 Sparc64Process::argsInit(int intSize, int pageSize)
372 {
373  SparcProcess::argsInit<uint64_t>(pageSize);
374 
375  // Stuff the trap handlers into the process address space
376  initVirtMem->writeBlob(fillStart,
377  fillHandler64, sizeof(MachInst) * numFillInsts);
378  initVirtMem->writeBlob(spillStart,
380 }
381 
382 void
383 Sparc32Process::argsInit(int intSize, int pageSize)
384 {
385  SparcProcess::argsInit<uint32_t>(pageSize);
386 
387  // Stuff the trap handlers into the process address space
388  initVirtMem->writeBlob(fillStart,
389  fillHandler32, sizeof(MachInst) * numFillInsts);
390  initVirtMem->writeBlob(spillStart,
392 }
393 
394 } // namespace gem5
gem5::ThreadContext::setIntReg
virtual void setIntReg(RegIndex reg_idx, RegVal val)=0
gem5::SparcISA::MISCREG_ASI
@ MISCREG_ASI
Ancillary State Registers.
Definition: misc.hh:45
gem5::Process::euid
uint64_t euid()
Definition: process.hh:83
misc.hh
gem5::EmulationPageTable
Definition: page_table.hh:52
gem5::loader::ObjectFile
Definition: object_file.hh:85
gem5::auxv::Gid
@ Gid
Definition: aux_vector.hh:82
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::Gcn3ISA::MachInst
InstFormat * MachInst
used to represent the encoding of a GCN3 inst.
Definition: gpu_types.hh:63
process.hh
system.hh
gem5::SparcISA::INTREG_WSTATE
@ INTREG_WSTATE
Definition: int.hh:64
gem5::Process::getStartPC
Addr getStartPC()
Definition: process.cc:490
gem5::Process::initVirtMem
std::unique_ptr< SETranslatingPortProxy > initVirtMem
Definition: process.hh:174
gem5::loader::ObjectFile::entryPoint
Addr entryPoint() const
Definition: object_file.hh:125
gem5::auxv::Random
@ Random
Definition: aux_vector.hh:89
gem5::SparcISA::INTREG_CANSAVE
@ INTREG_CANSAVE
Definition: int.hh:60
gem5::Process::getBias
Addr getBias()
Definition: process.cc:482
handlers.hh
gem5::SparcISA::spillHandler64
const MachInst spillHandler64[numSpillInsts]
Definition: handlers.hh:117
gem5::auxv::Hwcap
@ Hwcap
Definition: aux_vector.hh:85
gem5::SparcISA::INTREG_CLEANWIN
@ INTREG_CLEANWIN
Definition: int.hh:62
gem5::loader::ElfObject
Definition: elf_object.hh:64
gem5::Process::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: process.cc:287
process_impl.hh
gem5::Process::_pid
uint64_t _pid
Definition: process.hh:265
gem5::Process::egid
uint64_t egid()
Definition: process.hh:85
std::vector
STL vector class.
Definition: stl.hh:37
gem5::SparcProcess::SparcProcess
SparcProcess(const ProcessParams &params, loader::ObjectFile *objFile, Addr _StackBias)
Definition: process.cc:55
gem5::htobe
T htobe(T value)
Definition: byteswap.hh:174
gem5::auxv::Phent
@ Phent
Definition: aux_vector.hh:73
gem5::SparcISA::fillHandler32
const MachInst fillHandler32[numFillInsts]
Definition: handlers.hh:81
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::Process::gid
uint64_t gid()
Definition: process.hh:84
gem5::Process::memState
std::shared_ptr< MemState > memState
Definition: process.hh:276
sc_dt::align
void align(const scfx_rep &lhs, const scfx_rep &rhs, int &new_wp, int &len_mant, scfx_mant_ref &lhs_mant, scfx_mant_ref &rhs_mant)
Definition: scfx_rep.cc:2083
gem5::SparcProcess::fillStart
Addr fillStart
Definition: process.hh:51
gem5::SparcISA::spillHandler32
const MachInst spillHandler32[numSpillInsts]
Definition: handlers.hh:153
gem5::Process::uid
uint64_t uid()
Definition: process.hh:82
gem5::auxv::Base
@ Base
Definition: aux_vector.hh:76
gem5::auxv::Pagesz
@ Pagesz
Definition: aux_vector.hh:75
elf_object.hh
syscall_return.hh
gem5::auxv::Secure
@ Secure
Definition: aux_vector.hh:87
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
gem5::auxv::Clktck
@ Clktck
Definition: aux_vector.hh:86
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::SparcISA::MISCREG_TL
@ MISCREG_TL
Definition: misc.hh:66
asi.hh
gem5::ArmISA::MachInst
uint32_t MachInst
Definition: types.hh:55
gem5::Sparc32Process::argsInit
void argsInit(int intSize, int pageSize)
Definition: process.cc:383
gem5::Sparc64Process::argsInit
void argsInit(int intSize, int pageSize)
Definition: process.cc:371
gem5::copyStringArray
void copyStringArray(std::vector< std::string > &strings, AddrType array_ptr, AddrType data_ptr, const ByteOrder bo, PortProxy &memProxy)
Definition: process_impl.hh:43
gem5::auxv::AuxVector
Definition: aux_vector.hh:45
gem5::auxv::Phdr
@ Phdr
Definition: aux_vector.hh:72
gem5::SparcProcess::argsInit
void argsInit(int pageSize)
Definition: process.cc:143
gem5::SparcISA::INTREG_OTHERWIN
@ INTREG_OTHERWIN
Definition: int.hh:63
gem5::Sparc32Process::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: process.cc:113
gem5::Process::argv
std::vector< std::string > argv
Definition: process.hh:213
gem5::SparcISA::INTREG_CANRESTORE
@ INTREG_CANRESTORE
Definition: int.hh:61
int.hh
gem5::roundDown
static constexpr T roundDown(const T &val, const U &align)
This function is used to align addresses in memory.
Definition: intmath.hh:279
gem5::auxv::Egid
@ Egid
Definition: aux_vector.hh:83
types.hh
gem5::auxv::Entry
@ Entry
Definition: aux_vector.hh:78
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::Process::envp
std::vector< std::string > envp
Definition: process.hh:214
gem5::auxv::Phnum
@ Phnum
Definition: aux_vector.hh:74
name
const std::string & name()
Definition: trace.cc:49
gem5::ArmISA::StackPointerReg
const int StackPointerReg
Definition: int.hh:545
gem5::SparcProcess::spillStart
Addr spillStart
Definition: process.hh:51
gem5::Process
Definition: process.hh:67
gem5::SparcISA::ASI_PRIMARY
@ ASI_PRIMARY
Definition: asi.hh:167
gem5::SparcISA::numSpillInsts
const int numSpillInsts
Definition: handlers.hh:43
gem5::SparcISA::fillHandler64
const MachInst fillHandler64[numFillInsts]
Definition: handlers.hh:45
gem5::SparcISA::NWindows
const int NWindows
Definition: sparc_traits.hh:44
aux_vector.hh
gem5::SparcISA::MISCREG_TICK
@ MISCREG_TICK
Definition: misc.hh:46
gem5::System::threads
Threads threads
Definition: system.hh:316
gem5::SparcISA::MISCREG_FSR
@ MISCREG_FSR
Floating Point Status Register.
Definition: misc.hh:86
page_size.hh
gem5::SparcISA::PageBytes
const Addr PageBytes
Definition: page_size.hh:41
gem5::ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
gem5::SparcProcess::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: process.cc:69
gem5::auxv::Uid
@ Uid
Definition: aux_vector.hh:80
gem5::ArmISA::PageBytes
const Addr PageBytes
Definition: page_size.hh:53
gem5::SparcISA::MISCREG_PSTATE
@ MISCREG_PSTATE
Definition: misc.hh:65
gem5::roundUp
static constexpr T roundUp(const T &val, const U &align)
This function is used to align addresses in memory.
Definition: intmath.hh:260
logging.hh
gem5::Process::system
System * system
Definition: process.hh:162
gem5::SparcProcess::StackBias
const Addr StackBias
Definition: process.hh:48
gem5::SparcISA::numFillInsts
const int numFillInsts
Definition: handlers.hh:42
gem5::auxv::Euid
@ Euid
Definition: aux_vector.hh:81
gem5::Process::contextIds
std::vector< ContextID > contextIds
Definition: process.hh:159
gem5::SparcISA::MISCREG_CWP
@ MISCREG_CWP
Definition: misc.hh:68
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:225
gem5::SparcISA::MISCREG_MMU_LSU_CTRL
@ MISCREG_MMU_LSU_CTRL
Definition: misc.hh:92
page_table.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::auxv::Flags
@ Flags
Definition: aux_vector.hh:77
object_file.hh
gem5::SparcISA::MISCREG_MMU_P_CONTEXT
@ MISCREG_MMU_P_CONTEXT
MMU Internal Registers.
Definition: misc.hh:89
thread_context.hh
gem5::Process::objFile
loader::ObjectFile * objFile
Definition: process.hh:210
gem5::Sparc64Process::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: process.cc:128
byteswap.hh
gem5::ThreadContext::setMiscRegNoEffect
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0

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