gem5  v21.1.0.2
Public Member Functions | List of all members
gem5::DummyChecker Class Reference

Specific non-templated derived class used for SimObject configuration. More...

#include <dummy_checker.hh>

Inheritance diagram for gem5::DummyChecker:
gem5::CheckerCPU gem5::BaseCPU gem5::ExecContext gem5::ClockedObject gem5::SimObject gem5::Clocked gem5::EventManager gem5::Serializable gem5::Drainable gem5::statistics::Group gem5::Named

Public Member Functions

 DummyChecker (const Params &p)
 
- Public Member Functions inherited from gem5::CheckerCPU
void init () override
 init() is called after all C++ SimObjects have been created and all ports are connected. More...
 
 PARAMS (CheckerCPU)
 
 CheckerCPU (const Params &p)
 
virtual ~CheckerCPU ()
 
void setSystem (System *system)
 
void setIcachePort (RequestPort *icache_port)
 
void setDcachePort (RequestPort *dcache_port)
 
PortgetDataPort () override
 Purely virtual method that returns a reference to the data port. More...
 
PortgetInstPort () override
 Purely virtual method that returns a reference to the instruction port. More...
 
BaseMMUgetMMUPtr ()
 
virtual Counter totalInsts () const override
 
virtual Counter totalOps () const override
 
void serialize (CheckpointOut &cp) const override
 Serialize this object to the given output stream. More...
 
void unserialize (CheckpointIn &cp) override
 Reconstruct the state of this object from a checkpoint. More...
 
RegVal readIntRegOperand (const StaticInst *si, int idx) override
 Reads an integer register. More...
 
RegVal readFloatRegOperandBits (const StaticInst *si, int idx) override
 Reads a floating point register in its binary format, instead of by value. More...
 
const TheISA::VecRegContainer & readVecRegOperand (const StaticInst *si, int idx) const override
 Read source vector register operand. More...
 
TheISA::VecRegContainer & getWritableVecRegOperand (const StaticInst *si, int idx) override
 Read destination vector register operand for modification. More...
 
TheISA::VecElem readVecElemOperand (const StaticInst *si, int idx) const override
 Vector Elem Interfaces. More...
 
const TheISA::VecPredRegContainer & readVecPredRegOperand (const StaticInst *si, int idx) const override
 Predicate registers interface. More...
 
TheISA::VecPredRegContainer & getWritableVecPredRegOperand (const StaticInst *si, int idx) override
 Gets destination predicate register operand for modification. More...
 
RegVal readCCRegOperand (const StaticInst *si, int idx) override
 
template<typename T >
void setScalarResult (T &&t)
 
template<typename T >
void setVecResult (T &&t)
 
template<typename T >
void setVecElemResult (T &&t)
 
template<typename T >
void setVecPredResult (T &&t)
 
void setIntRegOperand (const StaticInst *si, int idx, RegVal val) override
 Sets an integer register to a value. More...
 
void setFloatRegOperandBits (const StaticInst *si, int idx, RegVal val) override
 Sets the bits of a floating point register of single width to a binary value. More...
 
void setCCRegOperand (const StaticInst *si, int idx, RegVal val) override
 
void setVecRegOperand (const StaticInst *si, int idx, const TheISA::VecRegContainer &val) override
 Sets a destination vector register operand to a value. More...
 
void setVecElemOperand (const StaticInst *si, int idx, const TheISA::VecElem val) override
 Sets a vector register to a value. More...
 
void setVecPredRegOperand (const StaticInst *si, int idx, const TheISA::VecPredRegContainer &val) override
 Sets a destination predicate register operand to a value. More...
 
bool readPredicate () const override
 
void setPredicate (bool val) override
 
bool readMemAccPredicate () const override
 
void setMemAccPredicate (bool val) override
 
uint64_t getHtmTransactionUid () const override
 
uint64_t newHtmTransactionUid () const override
 
Fault initiateHtmCmd (Request::Flags flags) override
 Initiate an HTM command, e.g. More...
 
bool inHtmTransactionalState () const override
 
uint64_t getHtmTransactionalDepth () const override
 
TheISA::PCState pcState () const override
 
void pcState (const TheISA::PCState &val) override
 
Addr instAddr ()
 
Addr nextInstAddr ()
 
MicroPC microPC ()
 
RegVal readMiscRegNoEffect (int misc_reg) const
 
RegVal readMiscReg (int misc_reg) override
 Reads a miscellaneous register, handling any architectural side effects due to reading that register. More...
 
void setMiscRegNoEffect (int misc_reg, RegVal val)
 
void setMiscReg (int misc_reg, RegVal val) override
 Sets a miscellaneous register, handling any architectural side effects due to writing that register. More...
 
RegVal readMiscRegOperand (const StaticInst *si, int idx) override
 
void setMiscRegOperand (const StaticInst *si, int idx, RegVal val) override
 
void recordPCChange (const TheISA::PCState &val)
 
void demapPage (Addr vaddr, uint64_t asn) override
 Invalidate a page in the DTLB and ITLB. More...
 
void armMonitor (Addr address) override
 
bool mwait (PacketPtr pkt) override
 
void mwaitAtomic (ThreadContext *tc) override
 
AddressMonitorgetAddrMonitor () override
 
RequestPtr genMemFragmentRequest (Addr frag_addr, int size, Request::Flags flags, const std::vector< bool > &byte_enable, int &frag_size, int &size_left) const
 Helper function used to generate the request for a single fragment of a memory access. More...
 
Fault readMem (Addr addr, uint8_t *data, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable) override
 
Fault writeMem (uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable) override
 
Fault amoMem (Addr addr, uint8_t *data, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override
 
unsigned int readStCondFailures () const override
 Returns the number of consecutive store conditional failures. More...
 
void setStCondFailures (unsigned int sc_failures) override
 Sets the number of consecutive store conditional failures. More...
 
void wakeup (ThreadID tid) override
 
void handleError ()
 
bool checkFlags (const RequestPtr &unverified_req, Addr vAddr, Addr pAddr, int flags)
 Checks if the flags set by the Checker and Checkee match. More...
 
void dumpAndExit ()
 
ThreadContexttcBase () const override
 Returns a pointer to the ThreadContext. More...
 
SimpleThreadthreadBase ()
 
- Public Member Functions inherited from gem5::BaseCPU
int cpuId () const
 Reads this CPU's ID. More...
 
uint32_t socketId () const
 Reads this CPU's Socket ID. More...
 
RequestorID dataRequestorId () const
 Reads this CPU's unique data requestor ID. More...
 
RequestorID instRequestorId () const
 Reads this CPU's unique instruction requestor ID. More...
 
PortgetPort (const std::string &if_name, PortID idx=InvalidPortID) override
 Get a port on this CPU. More...
 
uint32_t taskId () const
 Get cpu task id. More...
 
void taskId (uint32_t id)
 Set cpu task id. More...
 
uint32_t getPid () const
 
void setPid (uint32_t pid)
 
void workItemBegin ()
 
void workItemEnd ()
 
Tick instCount ()
 
BaseInterruptsgetInterruptController (ThreadID tid)
 
void postInterrupt (ThreadID tid, int int_num, int index)
 
void clearInterrupt (ThreadID tid, int int_num, int index)
 
void clearInterrupts (ThreadID tid)
 
bool checkInterrupts (ThreadID tid) const
 
Trace::InstTracergetTracer ()
 Provide access to the tracer pointer. More...
 
virtual void activateContext (ThreadID thread_num)
 Notify the CPU that the indicated context is now active. More...
 
virtual void suspendContext (ThreadID thread_num)
 Notify the CPU that the indicated context is now suspended. More...
 
virtual void haltContext (ThreadID thread_num)
 Notify the CPU that the indicated context is now halted. More...
 
int findContext (ThreadContext *tc)
 Given a Thread Context pointer return the thread num. More...
 
virtual ThreadContextgetContext (int tn)
 Given a thread num get tho thread context for it. More...
 
unsigned numContexts ()
 Get the number of thread contexts available. More...
 
ThreadID contextToThread (ContextID cid)
 Convert ContextID to threadID. More...
 
 PARAMS (BaseCPU)
 
 BaseCPU (const Params &params, bool is_checker=false)
 
virtual ~BaseCPU ()
 
void startup () override
 startup() is the final initialization call before simulation. More...
 
void regStats () override
 Callback to set stat parameters. More...
 
void regProbePoints () override
 Register probe points for this object. More...
 
void registerThreadContexts ()
 
void deschedulePowerGatingEvent ()
 
void schedulePowerGatingEvent ()
 
virtual void switchOut ()
 Prepare for another CPU to take over execution. More...
 
virtual void takeOverFrom (BaseCPU *cpu)
 Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be switched in. More...
 
void flushTLBs ()
 Flush all TLBs in the CPU. More...
 
bool switchedOut () const
 Determine if the CPU is switched out. More...
 
virtual void verifyMemoryMode () const
 Verify that the system is in a memory mode supported by the CPU. More...
 
unsigned int cacheLineSize () const
 Get the cache line size of the system. More...
 
virtual void serializeThread (CheckpointOut &cp, ThreadID tid) const
 Serialize a single thread. More...
 
virtual void unserializeThread (CheckpointIn &cp, ThreadID tid)
 Unserialize one thread. More...
 
void scheduleInstStop (ThreadID tid, Counter insts, const char *cause)
 Schedule an event that exits the simulation loops after a predefined number of instructions. More...
 
uint64_t getCurrentInstCount (ThreadID tid)
 Get the number of instructions executed by the specified thread on this CPU. More...
 
void traceFunctions (Addr pc)
 
void armMonitor (ThreadID tid, Addr address)
 
bool mwait (ThreadID tid, PacketPtr pkt)
 
void mwaitAtomic (ThreadID tid, ThreadContext *tc, BaseMMU *mmu)
 
AddressMonitorgetCpuAddrMonitor (ThreadID tid)
 
virtual void probeInstCommit (const StaticInstPtr &inst, Addr pc)
 Helper method to trigger PMU probes for a committed instruction. More...
 
- Public Member Functions inherited from gem5::ClockedObject
 ClockedObject (const ClockedObjectParams &p)
 
void serialize (CheckpointOut &cp) const override
 Serialize an object. More...
 
void unserialize (CheckpointIn &cp) override
 Unserialize an object. More...
 
- Public Member Functions inherited from gem5::SimObject
const Paramsparams () const
 
 SimObject (const Params &p)
 
virtual ~SimObject ()
 
virtual void loadState (CheckpointIn &cp)
 loadState() is called on each SimObject when restoring from a checkpoint. More...
 
virtual void initState ()
 initState() is called on each SimObject when not restoring from a checkpoint. More...
 
virtual void regProbeListeners ()
 Register probe listeners for this object. More...
 
ProbeManagergetProbeManager ()
 Get the probe manager for this object. More...
 
DrainState drain () override
 Provide a default implementation of the drain interface for objects that don't need draining. More...
 
virtual void memWriteback ()
 Write back dirty buffers to memory using functional writes. More...
 
virtual void memInvalidate ()
 Invalidate the contents of memory buffers. More...
 
void serialize (CheckpointOut &cp) const override
 Serialize an object. More...
 
void unserialize (CheckpointIn &cp) override
 Unserialize an object. More...
 
- Public Member Functions inherited from gem5::EventManager
EventQueueeventQueue () const
 
void schedule (Event &event, Tick when)
 
void deschedule (Event &event)
 
void reschedule (Event &event, Tick when, bool always=false)
 
void schedule (Event *event, Tick when)
 
void deschedule (Event *event)
 
void reschedule (Event *event, Tick when, bool always=false)
 
void wakeupEventQueue (Tick when=(Tick) -1)
 This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. More...
 
void setCurTick (Tick newVal)
 
 EventManager (EventManager &em)
 Event manger manages events in the event queue. More...
 
 EventManager (EventManager *em)
 
 EventManager (EventQueue *eq)
 
- Public Member Functions inherited from gem5::Serializable
 Serializable ()
 
virtual ~Serializable ()
 
void serializeSection (CheckpointOut &cp, const char *name) const
 Serialize an object into a new section. More...
 
void serializeSection (CheckpointOut &cp, const std::string &name) const
 
void unserializeSection (CheckpointIn &cp, const char *name)
 Unserialize an a child object. More...
 
void unserializeSection (CheckpointIn &cp, const std::string &name)
 
- Public Member Functions inherited from gem5::Drainable
DrainState drainState () const
 Return the current drain state of an object. More...
 
virtual void notifyFork ()
 Notify a child process of a fork. More...
 
- Public Member Functions inherited from gem5::statistics::Group
 Group (Group *parent, const char *name=nullptr)
 Construct a new statistics group. More...
 
virtual ~Group ()
 
virtual void resetStats ()
 Callback to reset stats. More...
 
virtual void preDumpStats ()
 Callback before stats are dumped. More...
 
void addStat (statistics::Info *info)
 Register a stat with this group. More...
 
const std::map< std::string, Group * > & getStatGroups () const
 Get all child groups associated with this object. More...
 
const std::vector< Info * > & getStats () const
 Get all stats associated with this object. More...
 
void addStatGroup (const char *name, Group *block)
 Add a stat block as a child of this block. More...
 
const InforesolveStat (std::string name) const
 Resolve a stat by its name within this group. More...
 
void mergeStatGroup (Group *block)
 Merge the contents (stats & children) of a block to this block. More...
 
 Group ()=delete
 
 Group (const Group &)=delete
 
Groupoperator= (const Group &)=delete
 
- Public Member Functions inherited from gem5::Named
 Named (const std::string &name_)
 
virtual ~Named ()=default
 
virtual std::string name () const
 
- Public Member Functions inherited from gem5::Clocked
void updateClockPeriod ()
 Update the tick to the current tick. More...
 
Tick clockEdge (Cycles cycles=Cycles(0)) const
 Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle. More...
 
Cycles curCycle () const
 Determine the current cycle, corresponding to a tick aligned to a clock edge. More...
 
Tick nextCycle () const
 Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future. More...
 
uint64_t frequency () const
 
Tick clockPeriod () const
 
double voltage () const
 
Cycles ticksToCycles (Tick t) const
 
Tick cyclesToTicks (Cycles c) const
 
- Public Member Functions inherited from gem5::ExecContext
virtual Fault readMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable)
 Perform an atomic memory read operation. More...
 
virtual Fault initiateMemRead (Addr addr, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable)
 Initiate a timing memory read operation. More...
 
virtual Fault writeMem (uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable)=0
 For atomic-mode contexts, perform an atomic memory write operation. More...
 
virtual Fault amoMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
 For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic Read-Modify-Write Memory Operation) More...
 
virtual Fault initiateMemAMO (Addr addr, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
 For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation) More...
 

Additional Inherited Members

- Public Types inherited from gem5::ClockedObject
using Params = ClockedObjectParams
 Parameters of ClockedObject. More...
 
- Public Types inherited from gem5::SimObject
typedef SimObjectParams Params
 
- Static Public Member Functions inherited from gem5::BaseCPU
static int numSimulatedCPUs ()
 
static Counter numSimulatedInsts ()
 
static Counter numSimulatedOps ()
 
- Static Public Member Functions inherited from gem5::SimObject
static void serializeAll (const std::string &cpt_dir)
 Create a checkpoint by serializing all SimObjects in the system. More...
 
static SimObjectfind (const char *name)
 Find the SimObject with the given name and return a pointer to it. More...
 
static void setSimObjectResolver (SimObjectResolver *resolver)
 There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...
 
static SimObjectResolvergetSimObjectResolver ()
 There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...
 
- Static Public Member Functions inherited from gem5::Serializable
static const std::string & currentSection ()
 Gets the fully-qualified name of the active section. More...
 
static void generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
 Generate a checkpoint file so that the serialization can be routed to it. More...
 
- Public Attributes inherited from gem5::CheckerCPU
SimpleThreadthread
 
Counter numLoad
 
Counter startNumLoad
 
InstResult unverifiedResult
 
RequestPtr unverifiedReq
 
uint8_t * unverifiedMemData
 
bool changedPC
 
bool willChangePC
 
TheISA::PCState newPCState
 
bool exitOnError
 
bool updateOnError
 
bool warnOnlyOnLoadError
 
InstSeqNum youngestSN
 
- Public Attributes inherited from gem5::BaseCPU
ThreadID numThreads
 Number of threads we're actually simulating (<= SMT_MAX_THREADS). More...
 
Systemsystem
 
gem5::BaseCPU::BaseCPUStats baseStats
 
Cycles syscallRetryLatency
 
- Public Attributes inherited from gem5::ClockedObject
PowerStatepowerState
 
- Static Public Attributes inherited from gem5::BaseCPU
static const uint32_t invldPid = std::numeric_limits<uint32_t>::max()
 Invalid or unknown Pid. More...
 
- Protected Types inherited from gem5::BaseCPU
enum  CPUState { CPU_STATE_ON, CPU_STATE_SLEEP, CPU_STATE_WAKEUP }
 
- Protected Member Functions inherited from gem5::BaseCPU
void updateCycleCounters (CPUState state)
 base method keeping track of cycle progression More...
 
void enterPwrGating ()
 
probing::PMUUPtr pmuProbePoint (const char *name)
 Helper method to instantiate probe points belonging to this object. More...
 
- Protected Member Functions inherited from gem5::Drainable
 Drainable ()
 
virtual ~Drainable ()
 
virtual void drainResume ()
 Resume execution after a successful drain. More...
 
void signalDrainDone () const
 Signal that an object is drained. More...
 
- Protected Member Functions inherited from gem5::Clocked
 Clocked (ClockDomain &clk_domain)
 Create a clocked object and set the clock domain based on the parameters. More...
 
 Clocked (Clocked &)=delete
 
Clockedoperator= (Clocked &)=delete
 
virtual ~Clocked ()
 Virtual destructor due to inheritance. More...
 
void resetClock () const
 Reset the object's clock using the current global tick value. More...
 
virtual void clockPeriodUpdated ()
 A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed. More...
 
- Protected Attributes inherited from gem5::CheckerCPU
RequestorID requestorId
 id attached to all issued requests More...
 
const RegIndex zeroReg
 
std::vector< Process * > workload
 
SystemsystemPtr
 
RequestPorticachePort
 
RequestPortdcachePort
 
ThreadContexttc
 
BaseMMUmmu
 
std::queue< InstResultresult
 
StaticInstPtr curStaticInst
 
StaticInstPtr curMacroStaticInst
 
Counter numInst
 
Counter startNumInst
 
std::queue< int > miscRegIdxs
 
- Protected Attributes inherited from gem5::BaseCPU
Tick instCnt
 Instruction count used for SPARC misc register. More...
 
int _cpuId
 
const uint32_t _socketId
 Each cpu will have a socket ID that corresponds to its physical location in the system. More...
 
RequestorID _instRequestorId
 instruction side request id that must be placed in all requests More...
 
RequestorID _dataRequestorId
 data side request id that must be placed in all requests More...
 
uint32_t _taskId
 An intrenal representation of a task identifier within gem5. More...
 
uint32_t _pid
 The current OS process ID that is executing on this processor. More...
 
bool _switchedOut
 Is the CPU switched out or active? More...
 
const unsigned int _cacheLineSize
 Cache the cache line size that we get from the system. More...
 
std::vector< BaseInterrupts * > interrupts
 
std::vector< ThreadContext * > threadContexts
 
Trace::InstTracertracer
 
Cycles previousCycle
 
CPUState previousState
 
const Cycles pwrGatingLatency
 
const bool powerGatingOnIdle
 
EventFunctionWrapper enterPwrGatingEvent
 
probing::PMUUPtr ppRetiredInsts
 Instruction commit probe point. More...
 
probing::PMUUPtr ppRetiredInstsPC
 
probing::PMUUPtr ppRetiredLoads
 Retired load instructions. More...
 
probing::PMUUPtr ppRetiredStores
 Retired store instructions. More...
 
probing::PMUUPtr ppRetiredBranches
 Retired branches (any type) More...
 
probing::PMUUPtr ppAllCycles
 CPU cycle counter even if any thread Context is suspended. More...
 
probing::PMUUPtr ppActiveCycles
 CPU cycle counter, only counts if any thread contexts is active. More...
 
ProbePointArg< bool > * ppSleeping
 ProbePoint that signals transitions of threadContexts sets. More...
 
- Protected Attributes inherited from gem5::SimObject
const SimObjectParams & _params
 Cached copy of the object parameters. More...
 
- Protected Attributes inherited from gem5::EventManager
EventQueueeventq
 A pointer to this object's event queue. More...
 
- Static Protected Attributes inherited from gem5::BaseCPU
static std::unique_ptr< GlobalStatsglobalStats
 Pointer to the global stat structure. More...
 

Detailed Description

Specific non-templated derived class used for SimObject configuration.

Definition at line 50 of file dummy_checker.hh.

Constructor & Destructor Documentation

◆ DummyChecker()

gem5::DummyChecker::DummyChecker ( const Params p)
inline

Definition at line 53 of file dummy_checker.hh.

References fatal_if, and gem5::MipsISA::p.


The documentation for this class was generated from the following file:

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