gem5  v21.2.0.0
RubyPort.cc
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1 /*
2  * Copyright (c) 2012-2013,2020 ARM Limited
3  * All rights reserved.
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14  * Copyright (c) 2009-2013 Advanced Micro Devices, Inc.
15  * Copyright (c) 2011 Mark D. Hill and David A. Wood
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41 
43 
44 #include "base/compiler.hh"
46 #include "debug/Config.hh"
47 #include "debug/Drain.hh"
48 #include "debug/Ruby.hh"
49 #include "mem/ruby/protocol/AccessPermission.hh"
51 #include "mem/simple_mem.hh"
52 #include "sim/full_system.hh"
53 #include "sim/system.hh"
54 
55 namespace gem5
56 {
57 
58 namespace ruby
59 {
60 
62  : ClockedObject(p), m_ruby_system(p.ruby_system), m_version(p.version),
63  m_controller(NULL), m_mandatory_q_ptr(NULL),
64  m_usingRubyTester(p.using_ruby_tester), system(p.system),
65  pioRequestPort(csprintf("%s.pio-request-port", name()), this),
66  pioResponsePort(csprintf("%s.pio-response-port", name()), this),
67  memRequestPort(csprintf("%s.mem-request-port", name()), this),
68  memResponsePort(csprintf("%s-mem-response-port", name()), this,
69  p.ruby_system->getAccessBackingStore(), -1,
70  p.no_retry_on_stall),
71  gotAddrRanges(p.port_interrupt_out_port_connection_count),
72  m_isCPUSequencer(p.is_cpu_sequencer)
73 {
74  assert(m_version != -1);
75 
76  // create the response ports based on the number of connected ports
77  for (size_t i = 0; i < p.port_in_ports_connection_count; ++i) {
79  ("%s.response_ports%d", name(), i), this,
80  p.ruby_system->getAccessBackingStore(),
81  i, p.no_retry_on_stall));
82  }
83 
84  // create the request ports based on the number of connected ports
85  for (size_t i = 0; i < p.port_interrupt_out_port_connection_count; ++i) {
87  "%s.request_ports%d", name(), i), this));
88  }
89 }
90 
91 void
93 {
94  assert(m_controller != NULL);
96  for (const auto &response_port : response_ports)
97  response_port->sendRangeChange();
98  if (gotAddrRanges == 0 && FullSystem) {
100  }
101 }
102 
103 Port &
104 RubyPort::getPort(const std::string &if_name, PortID idx)
105 {
106  if (if_name == "mem_request_port") {
107  return memRequestPort;
108  } else if (if_name == "pio_request_port") {
109  return pioRequestPort;
110  } else if (if_name == "mem_response_port") {
111  return memResponsePort;
112  } else if (if_name == "pio_response_port") {
113  return pioResponsePort;
114  } else if (if_name == "interrupt_out_port") {
115  // used by the x86 CPUs to connect the interrupt PIO and interrupt
116  // response port
117  if (idx >= static_cast<PortID>(request_ports.size())) {
118  panic("%s: unknown %s index (%d)\n", __func__, if_name, idx);
119  }
120 
121  return *request_ports[idx];
122  } else if (if_name == "in_ports") {
123  // used by the CPUs to connect the caches to the interconnect, and
124  // for the x86 case also the interrupt request port
125  if (idx >= static_cast<PortID>(response_ports.size())) {
126  panic("%s: unknown %s index (%d)\n", __func__, if_name, idx);
127  }
128 
129  return *response_ports[idx];
130  }
131 
132  // pass it along to our super class
133  return ClockedObject::getPort(if_name, idx);
134 }
135 
137  RubyPort *_port)
138  : QueuedRequestPort(_name, _port, reqQueue, snoopRespQueue),
139  reqQueue(*_port, *this), snoopRespQueue(*_port, *this)
140 {
141  DPRINTF(RubyPort, "Created request pioport on sequencer %s\n", _name);
142 }
143 
145  RubyPort *_port)
146  : QueuedResponsePort(_name, _port, queue), queue(*_port, *this)
147 {
148  DPRINTF(RubyPort, "Created response pioport on sequencer %s\n", _name);
149 }
150 
152  RubyPort *_port)
153  : QueuedRequestPort(_name, _port, reqQueue, snoopRespQueue),
154  reqQueue(*_port, *this), snoopRespQueue(*_port, *this)
155 {
156  DPRINTF(RubyPort, "Created request memport on ruby sequencer %s\n", _name);
157 }
158 
161  bool _access_backing_store, PortID id,
162  bool _no_retry_on_stall)
163  : QueuedResponsePort(_name, _port, queue, id), queue(*_port, *this),
164  access_backing_store(_access_backing_store),
165  no_retry_on_stall(_no_retry_on_stall)
166 {
167  DPRINTF(RubyPort, "Created response memport on ruby sequencer %s\n",
168  _name);
169 }
170 
171 bool
173 {
174  RubyPort *rp = static_cast<RubyPort *>(&owner);
175  DPRINTF(RubyPort, "Response for address: 0x%#x\n", pkt->getAddr());
176 
177  // send next cycle
179  pkt, curTick() + rp->m_ruby_system->clockPeriod());
180  return true;
181 }
182 
184 {
185  // got a response from a device
186  assert(pkt->isResponse());
187  assert(!pkt->htmTransactionFailedInCache());
188 
189  // First we must retrieve the request port from the sender State
190  RubyPort::SenderState *senderState =
191  safe_cast<RubyPort::SenderState *>(pkt->popSenderState());
192  MemResponsePort *port = senderState->port;
193  assert(port != NULL);
194  delete senderState;
195 
196  // In FS mode, ruby memory will receive pio responses from devices
197  // and it must forward these responses back to the particular CPU.
198  DPRINTF(RubyPort, "Pio response for address %#x, going to %s\n",
199  pkt->getAddr(), port->name());
200 
201  // attempt to send the response in the next cycle
202  RubyPort *rp = static_cast<RubyPort *>(&owner);
203  port->schedTimingResp(pkt, curTick() + rp->m_ruby_system->clockPeriod());
204 
205  return true;
206 }
207 
208 bool
210 {
211  RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
212 
213  for (size_t i = 0; i < ruby_port->request_ports.size(); ++i) {
214  AddrRangeList l = ruby_port->request_ports[i]->getAddrRanges();
215  for (auto it = l.begin(); it != l.end(); ++it) {
216  if (it->contains(pkt->getAddr())) {
217  // generally it is not safe to assume success here as
218  // the port could be blocked
219  [[maybe_unused]] bool success =
220  ruby_port->request_ports[i]->sendTimingReq(pkt);
221  assert(success);
222  return true;
223  }
224  }
225  }
226  panic("Should never reach here!\n");
227 }
228 
229 Tick
231 {
232  RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
233  // Only atomic_noncaching mode supported!
234  if (!ruby_port->system->bypassCaches()) {
235  panic("Ruby supports atomic accesses only in noncaching mode\n");
236  }
237 
238  for (size_t i = 0; i < ruby_port->request_ports.size(); ++i) {
239  AddrRangeList l = ruby_port->request_ports[i]->getAddrRanges();
240  for (auto it = l.begin(); it != l.end(); ++it) {
241  if (it->contains(pkt->getAddr())) {
242  return ruby_port->request_ports[i]->sendAtomic(pkt);
243  }
244  }
245  }
246  panic("Could not find address in Ruby PIO address ranges!\n");
247 }
248 
249 bool
251 {
252  DPRINTF(RubyPort, "Timing request for address %#x on port %d\n",
253  pkt->getAddr(), id);
254  RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
255 
256  if (pkt->cacheResponding())
257  panic("RubyPort should never see request with the "
258  "cacheResponding flag set\n");
259 
260  // ruby doesn't support cache maintenance operations at the
261  // moment, as a workaround, we respond right away
262  if (pkt->req->isCacheMaintenance()) {
263  warn_once("Cache maintenance operations are not supported in Ruby.\n");
264  pkt->makeResponse();
265  schedTimingResp(pkt, curTick());
266  return true;
267  }
268  // Check for pio requests and directly send them to the dedicated
269  // pio port.
270  if (pkt->cmd != MemCmd::MemSyncReq) {
271  if (!isPhysMemAddress(pkt)) {
272  assert(!pkt->req->isHTMCmd());
273  assert(ruby_port->memRequestPort.isConnected());
274  DPRINTF(RubyPort, "Request address %#x assumed to be a "
275  "pio address\n", pkt->getAddr());
276 
277  // Save the port in the sender state object to be used later to
278  // route the response
279  pkt->pushSenderState(new SenderState(this));
280 
281  // send next cycle
282  RubySystem *rs = ruby_port->m_ruby_system;
283  ruby_port->memRequestPort.schedTimingReq(pkt,
284  curTick() + rs->clockPeriod());
285  return true;
286  }
287  }
288 
289  // Save the port in the sender state object to be used later to
290  // route the response
291  pkt->pushSenderState(new SenderState(this));
292 
293  // Submit the ruby request
294  RequestStatus requestStatus = ruby_port->makeRequest(pkt);
295 
296  // If the request successfully issued then we should return true.
297  // Otherwise, we need to tell the port to retry at a later point
298  // and return false.
299  if (requestStatus == RequestStatus_Issued) {
300  DPRINTF(RubyPort, "Request %s 0x%x issued\n", pkt->cmdString(),
301  pkt->getAddr());
302  return true;
303  }
304 
305  // pop off sender state as this request failed to issue
306  SenderState *ss = safe_cast<SenderState *>(pkt->popSenderState());
307  delete ss;
308 
309  if (pkt->cmd != MemCmd::MemSyncReq) {
311  "Request %s for address %#x did not issue because %s\n",
312  pkt->cmdString(), pkt->getAddr(),
313  RequestStatus_to_string(requestStatus));
314  }
315 
316  addToRetryList();
317 
318  return false;
319 }
320 
321 Tick
323 {
324  RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
325  // Only atomic_noncaching mode supported!
326  if (!ruby_port->system->bypassCaches()) {
327  panic("Ruby supports atomic accesses only in noncaching mode\n");
328  }
329 
330  // Check for pio requests and directly send them to the dedicated
331  // pio port.
332  if (pkt->cmd != MemCmd::MemSyncReq) {
333  if (!isPhysMemAddress(pkt)) {
334  assert(ruby_port->memRequestPort.isConnected());
335  DPRINTF(RubyPort, "Request address %#x assumed to be a "
336  "pio address\n", pkt->getAddr());
337 
338  // Save the port in the sender state object to be used later to
339  // route the response
340  pkt->pushSenderState(new SenderState(this));
341 
342  // send next cycle
343  Tick req_ticks = ruby_port->memRequestPort.sendAtomic(pkt);
344  return ruby_port->ticksToCycles(req_ticks);
345  }
346 
347  assert(getOffset(pkt->getAddr()) + pkt->getSize() <=
349  }
350 
351  // Find the machine type of memory controller interface
352  RubySystem *rs = ruby_port->m_ruby_system;
353  static int mem_interface_type = -1;
354  if (mem_interface_type == -1) {
355  if (rs->m_abstract_controls[MachineType_Directory].size() != 0) {
356  mem_interface_type = MachineType_Directory;
357  }
358  else if (rs->m_abstract_controls[MachineType_Memory].size() != 0) {
359  mem_interface_type = MachineType_Memory;
360  }
361  else {
362  panic("Can't find the memory controller interface\n");
363  }
364  }
365 
366  // Find the controller for the target address
367  MachineID id = ruby_port->m_controller->mapAddressToMachine(
368  pkt->getAddr(), (MachineType)mem_interface_type);
369  AbstractController *mem_interface =
370  rs->m_abstract_controls[mem_interface_type][id.getNum()];
371  Tick latency = mem_interface->recvAtomic(pkt);
372  if (access_backing_store)
373  rs->getPhysMem()->access(pkt);
374  return latency;
375 }
376 
377 void
379 {
380  RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
381 
382  //
383  // Unless the request port do not want retries (e.g., the Ruby tester),
384  // record the stalled M5 port for later retry when the sequencer
385  // becomes free.
386  //
387  if (!no_retry_on_stall && !ruby_port->onRetryList(this)) {
388  ruby_port->addToRetryList(this);
389  }
390 }
391 
392 void
394 {
395  DPRINTF(RubyPort, "Functional access for address: %#x\n", pkt->getAddr());
396 
397  [[maybe_unused]] RubyPort *rp = static_cast<RubyPort *>(&owner);
398  RubySystem *rs = rp->m_ruby_system;
399 
400  // Check for pio requests and directly send them to the dedicated
401  // pio port.
402  if (!isPhysMemAddress(pkt)) {
403  DPRINTF(RubyPort, "Pio Request for address: 0x%#x\n", pkt->getAddr());
404  assert(rp->pioRequestPort.isConnected());
406  return;
407  }
408 
409  assert(pkt->getAddr() + pkt->getSize() <=
411 
412  if (access_backing_store) {
413  // The attached physmem contains the official version of data.
414  // The following command performs the real functional access.
415  // This line should be removed once Ruby supplies the official version
416  // of data.
417  rs->getPhysMem()->functionalAccess(pkt);
418  } else {
419  bool accessSucceeded = false;
420  bool needsResponse = pkt->needsResponse();
421 
422  // Do the functional access on ruby memory
423  if (pkt->isRead()) {
424  accessSucceeded = rs->functionalRead(pkt);
425  } else if (pkt->isWrite()) {
426  accessSucceeded = rs->functionalWrite(pkt);
427  } else {
428  panic("Unsupported functional command %s\n", pkt->cmdString());
429  }
430 
431  // Unless the request port explicitly said otherwise, generate an error
432  // if the functional request failed
433  if (!accessSucceeded && !pkt->suppressFuncError()) {
434  fatal("Ruby functional %s failed for address %#x\n",
435  pkt->isWrite() ? "write" : "read", pkt->getAddr());
436  }
437 
438  // turn packet around to go back to request port if response expected
439  if (needsResponse) {
440  // The pkt is already turned into a reponse if the directory
441  // forwarded the request to the memory controller (see
442  // AbstractController::functionalMemoryWrite and
443  // AbstractMemory::functionalAccess)
444  if (!pkt->isResponse())
445  pkt->makeResponse();
446  pkt->setFunctionalResponseStatus(accessSucceeded);
447  }
448 
449  DPRINTF(RubyPort, "Functional access %s!\n",
450  accessSucceeded ? "successful":"failed");
451  }
452 }
453 
454 void
456 {
457  DPRINTF(RubyPort, "Hit callback for %s 0x%x\n", pkt->cmdString(),
458  pkt->getAddr());
459 
460  // The packet was destined for memory and has not yet been turned
461  // into a response
462  assert(system->isMemAddr(pkt->getAddr()) || system->isDeviceMemAddr(pkt));
463  assert(pkt->isRequest());
464 
465  // First we must retrieve the request port from the sender State
466  RubyPort::SenderState *senderState =
467  safe_cast<RubyPort::SenderState *>(pkt->popSenderState());
468  MemResponsePort *port = senderState->port;
469  assert(port != NULL);
470  delete senderState;
471 
472  port->hitCallback(pkt);
473 
474  trySendRetries();
475 }
476 
477 void
479 {
480  //
481  // If we had to stall the MemResponsePorts, wake them up because the
482  // sequencer likely has free resources now.
483  //
484  if (!retryList.empty()) {
485  // Record the current list of ports to retry on a temporary list
486  // before calling sendRetryReq on those ports. sendRetryReq will cause
487  // an immediate retry, which may result in the ports being put back on
488  // the list. Therefore we want to clear the retryList before calling
489  // sendRetryReq.
491 
492  retryList.clear();
493 
494  for (auto i = curRetryList.begin(); i != curRetryList.end(); ++i) {
496  "Sequencer may now be free. SendRetry to port %s\n",
497  (*i)->name());
498  (*i)->sendRetryReq();
499  }
500  }
501 }
502 
503 void
505 {
506  //If we weren't able to drain before, we might be able to now.
507  if (drainState() == DrainState::Draining) {
508  unsigned int drainCount = outstandingCount();
509  DPRINTF(Drain, "Drain count: %u\n", drainCount);
510  if (drainCount == 0) {
511  DPRINTF(Drain, "RubyPort done draining, signaling drain done\n");
512  signalDrainDone();
513  }
514  }
515 }
516 
519 {
520  if (isDeadlockEventScheduled()) {
522  }
523 
524  //
525  // If the RubyPort is not empty, then it needs to clear all outstanding
526  // requests before it should call signalDrainDone()
527  //
528  DPRINTF(Config, "outstanding count %d\n", outstandingCount());
529  if (outstandingCount() > 0) {
530  DPRINTF(Drain, "RubyPort not drained\n");
531  return DrainState::Draining;
532  } else {
533  return DrainState::Drained;
534  }
535 }
536 
537 void
539 {
540  bool needsResponse = pkt->needsResponse();
541 
542  // Unless specified at configuration, all responses except failed SC
543  // and Flush operations access M5 physical memory.
544  bool accessPhysMem = access_backing_store;
545 
546  if (pkt->isLLSC()) {
547  if (pkt->isWrite()) {
548  if (pkt->req->getExtraData() != 0) {
549  //
550  // Successful SC packets convert to normal writes
551  //
552  pkt->convertScToWrite();
553  } else {
554  //
555  // Failed SC packets don't access physical memory and thus
556  // the RubyPort itself must convert it to a response.
557  //
558  accessPhysMem = false;
559  }
560  } else {
561  //
562  // All LL packets convert to normal loads so that M5 PhysMem does
563  // not lock the blocks.
564  //
565  pkt->convertLlToRead();
566  }
567  }
568 
569  // Flush, acquire, release requests don't access physical memory
570  if (pkt->isFlush() || pkt->cmd == MemCmd::MemSyncReq
571  || pkt->cmd == MemCmd::WriteCompleteResp) {
572  accessPhysMem = false;
573  }
574 
575  if (pkt->req->isKernel()) {
576  accessPhysMem = false;
577  needsResponse = true;
578  }
579 
580  DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse);
581 
582  RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
583  RubySystem *rs = ruby_port->m_ruby_system;
584  if (accessPhysMem) {
585  // We must check device memory first in case it overlaps with the
586  // system memory range.
587  if (ruby_port->system->isDeviceMemAddr(pkt)) {
588  auto dmem = ruby_port->system->getDeviceMemory(pkt);
589  dmem->access(pkt);
590  } else if (ruby_port->system->isMemAddr(pkt->getAddr())) {
591  rs->getPhysMem()->access(pkt);
592  } else {
593  panic("Packet is in neither device nor system memory!");
594  }
595  } else if (needsResponse) {
596  pkt->makeResponse();
597  }
598 
599  // turn packet around to go back to request port if response expected
600  if (needsResponse || pkt->isResponse()) {
601  DPRINTF(RubyPort, "Sending packet back over port\n");
602  // Send a response in the same cycle. There is no need to delay the
603  // response because the response latency is already incurred in the
604  // Ruby protocol.
605  schedTimingResp(pkt, curTick());
606  } else {
607  delete pkt;
608  }
609 
610  DPRINTF(RubyPort, "Hit callback done!\n");
611 }
612 
615 {
616  // at the moment the assumption is that the request port does not care
617  AddrRangeList ranges;
618  RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
619 
620  for (size_t i = 0; i < ruby_port->request_ports.size(); ++i) {
621  ranges.splice(ranges.begin(),
622  ruby_port->request_ports[i]->getAddrRanges());
623  }
624  for ([[maybe_unused]] const auto &r : ranges)
625  DPRINTF(RubyPort, "%s\n", r.to_string());
626  return ranges;
627 }
628 
629 bool
631 {
632  RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
633  AddrRangeList ranges = ruby_port->system->getShadowRomRanges();
634 
635  for (auto it = ranges.begin(); it != ranges.end(); ++it) {
636  if (it->contains(addr)) {
637  return true;
638  }
639  }
640 
641  return false;
642 }
643 
644 bool
646 {
647  RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
648  Addr addr = pkt->getAddr();
649  return (ruby_port->system->isMemAddr(addr) && !isShadowRomAddress(addr))
650  || ruby_port->system->isDeviceMemAddr(pkt);
651 }
652 
653 void
655 {
656  DPRINTF(RubyPort, "Sending invalidations.\n");
657  // Allocate the invalidate request and packet on the stack, as it is
658  // assumed they will not be modified or deleted by receivers.
659  // TODO: should this really be using funcRequestorId?
660  auto request = std::make_shared<Request>(
661  address, RubySystem::getBlockSizeBytes(), 0,
663 
664  // Use a single packet to signal all snooping ports of the invalidation.
665  // This assumes that snooping ports do NOT modify the packet/request
666  Packet pkt(request, MemCmd::InvalidateReq);
667  for (CpuPortIter p = response_ports.begin(); p != response_ports.end();
668  ++p) {
669  // check if the connected request port is snooping
670  if ((*p)->isSnooping()) {
671  // send as a snoop request
672  (*p)->sendTimingSnoopReq(&pkt);
673  }
674  }
675 }
676 
677 void
679 {
680  RubyPort &r = static_cast<RubyPort &>(owner);
681  r.gotAddrRanges--;
682  if (r.gotAddrRanges == 0 && FullSystem) {
683  r.pioResponsePort.sendRangeChange();
684  }
685 }
686 
687 int
689 {
690  int num_written = 0;
691  for (auto port : response_ports) {
692  if (port->trySatisfyFunctional(func_pkt)) {
693  num_written += 1;
694  }
695  }
696  return num_written;
697 }
698 
699 } // namespace ruby
700 } // namespace gem5
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:190
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::Packet::cmdString
const std::string & cmdString() const
Return the string name of the cmd field (for debugging and tracing).
Definition: packet.hh:577
gem5::SimObject::getPort
virtual Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a port with a given name and index.
Definition: sim_object.cc:126
gem5::ruby::RubyPort::m_version
uint32_t m_version
Definition: RubyPort.hh:196
gem5::ruby::RubyPort::SenderState::port
MemResponsePort * port
Definition: RubyPort.hh:148
gem5::ruby::RubyPort::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: RubyPort.cc:104
gem5::Packet::isRequest
bool isRequest() const
Definition: packet.hh:586
gem5::Packet::setFunctionalResponseStatus
void setFunctionalResponseStatus(bool success)
Definition: packet.hh:1055
gem5::Port::name
const std::string name() const
Return port name (for DPRINTF).
Definition: port.hh:111
system.hh
gem5::ruby::RubyPort::descheduleDeadlockEvent
virtual void descheduleDeadlockEvent()=0
gem5::Drainable::drainState
DrainState drainState() const
Return the current drain state of an object.
Definition: drain.hh:324
gem5::ruby::RubyPort::PioRequestPort::recvRangeChange
void recvRangeChange()
Called to receive an address range change from the peer response port.
Definition: RubyPort.cc:678
warn_once
#define warn_once(...)
Definition: logging.hh:250
gem5::ruby::RubyPort::MemResponsePort::recvFunctional
void recvFunctional(PacketPtr pkt)
Receive a functional request packet from the peer.
Definition: RubyPort.cc:393
gem5::QueuedRequestPort
The QueuedRequestPort combines two queues, a request queue and a snoop response queue,...
Definition: qport.hh:109
gem5::Packet::pushSenderState
void pushSenderState(SenderState *sender_state)
Push a new sender state to the packet and make the current sender state the predecessor of the new on...
Definition: packet.cc:316
gem5::Packet::req
RequestPtr req
A pointer to the original request.
Definition: packet.hh:366
gem5::Packet::convertScToWrite
void convertScToWrite()
It has been determined that the SC packet should successfully update memory.
Definition: packet.hh:827
gem5::ruby::RubyPort::CpuPortIter
std::vector< MemResponsePort * >::iterator CpuPortIter
Vector of M5 Ports attached to this Ruby port.
Definition: RubyPort.hh:223
gem5::ruby::RubyPort::system
System * system
Definition: RubyPort.hh:200
gem5::ruby::RubyPort::memResponsePort
MemResponsePort memResponsePort
Definition: RubyPort.hh:219
gem5::ruby::RubyPort::response_ports
std::vector< MemResponsePort * > response_ports
Definition: RubyPort.hh:202
gem5::RequestPort::sendAtomic
Tick sendAtomic(PacketPtr pkt)
Send an atomic request packet, where the data is moved and the state is updated in zero time,...
Definition: port.hh:464
gem5::ruby::RubyPort::pioResponsePort
PioResponsePort pioResponsePort
Definition: RubyPort.hh:217
gem5::ruby::RubyPort::MemResponsePort
Definition: RubyPort.hh:81
gem5::ruby::RubyPort::MemRequestPort::recvTimingResp
bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
Definition: RubyPort.cc:183
gem5::ruby::RubyPort::MemResponsePort::recvAtomic
Tick recvAtomic(PacketPtr pkt)
Receive an atomic request packet from the peer.
Definition: RubyPort.cc:322
gem5::System::bypassCaches
bool bypassCaches() const
Should caches be bypassed?
Definition: system.hh:283
gem5::Packet::cacheResponding
bool cacheResponding() const
Definition: packet.hh:646
AbstractController.hh
gem5::ruby::RubyPort::ruby_hit_callback
void ruby_hit_callback(PacketPtr pkt)
Definition: RubyPort.cc:455
gem5::System::getShadowRomRanges
AddrRangeList getShadowRomRanges() const
Definition: system.hh:383
gem5::Packet::isWrite
bool isWrite() const
Definition: packet.hh:583
gem5::ruby::RubySystem::getBlockSizeBytes
static uint32_t getBlockSizeBytes()
Definition: RubySystem.hh:72
gem5::X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:1003
std::vector
STL vector class.
Definition: stl.hh:37
gem5::ruby::RubyPort::retryList
std::vector< MemResponsePort * > retryList
Definition: RubyPort.hh:230
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::ruby::RubyPort::trySendRetries
void trySendRetries()
Definition: RubyPort.cc:478
gem5::System::getDeviceMemory
memory::AbstractMemory * getDeviceMemory(const PacketPtr &pkt) const
Return a pointer to the device memory.
Definition: system.cc:367
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::ruby::RubyPort::MemResponsePort::isShadowRomAddress
bool isShadowRomAddress(Addr addr) const
Definition: RubyPort.cc:630
gem5::ruby::makeLineAddress
Addr makeLineAddress(Addr addr)
Definition: Address.cc:60
gem5::ruby::AbstractController
Definition: AbstractController.hh:82
gem5::ruby::RubyPort::SenderState
Definition: RubyPort.hh:146
gem5::Request::funcRequestorId
@ funcRequestorId
This requestor id is used for functional requests that don't come from a particular device.
Definition: request.hh:262
gem5::ruby::RubyPort::MemResponsePort::hitCallback
void hitCallback(PacketPtr pkt)
Definition: RubyPort.cc:538
gem5::ruby::RubyPort::m_mandatory_q_ptr
MessageBuffer * m_mandatory_q_ptr
Definition: RubyPort.hh:198
gem5::Packet::convertLlToRead
void convertLlToRead()
When ruby is in use, Ruby will monitor the cache line and the phys memory should treat LL ops as norm...
Definition: packet.hh:839
gem5::ruby::RubyPort::gotAddrRanges
unsigned int gotAddrRanges
Definition: RubyPort.hh:220
gem5::ruby::RubyPort::MemResponsePort::MemResponsePort
MemResponsePort(const std::string &_name, RubyPort *_port, bool _access_backing_store, PortID id, bool _no_retry_on_stall)
Definition: RubyPort.cc:160
gem5::DrainState
DrainState
Object drain/handover states.
Definition: drain.hh:74
gem5::ruby::RubyPort::MemResponsePort::isPhysMemAddress
bool isPhysMemAddress(PacketPtr pkt) const
Definition: RubyPort.cc:645
gem5::ruby::RubyPort::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: RubyPort.cc:92
gem5::RequestPort::sendFunctional
void sendFunctional(PacketPtr pkt) const
Send a functional request packet, where the data is instantly updated everywhere in the memory system...
Definition: port.hh:485
gem5::Packet::isRead
bool isRead() const
Definition: packet.hh:582
gem5::ruby::RubyPort::makeRequest
virtual RequestStatus makeRequest(PacketPtr pkt)=0
gem5::ruby::RubyPort::ruby_eviction_callback
void ruby_eviction_callback(Addr address)
Definition: RubyPort.cc:654
gem5::System::isMemAddr
bool isMemAddr(Addr addr) const
Check if a physical address is within a range of a memory that is part of the global address map.
Definition: system.cc:344
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::ruby::RubyPort::PioResponsePort::PioResponsePort
PioResponsePort(const std::string &_name, RubyPort *_port)
Definition: RubyPort.cc:144
gem5::QueuedResponsePort
A queued port is a port that has an infinite queue for outgoing packets and thus decouples the module...
Definition: qport.hh:61
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::Packet::htmTransactionFailedInCache
bool htmTransactionFailedInCache() const
Returns whether or not this packet/request has returned from the cache hierarchy in a failed transact...
Definition: packet.cc:508
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::ruby::AbstractController::mapAddressToMachine
MachineID mapAddressToMachine(Addr addr, MachineType mtype) const
Map an address to the correct MachineID.
Definition: AbstractController.cc:405
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::ruby::RubyPort::request_ports
std::vector< PioRequestPort * > request_ports
Definition: RubyPort.hh:224
RubyTester.hh
gem5::MemCmd::MemSyncReq
@ MemSyncReq
Definition: packet.hh:119
gem5::ruby::RubyPort::isDeadlockEventScheduled
virtual bool isDeadlockEventScheduled() const =0
gem5::ruby::AbstractController::recvAtomic
Tick recvAtomic(PacketPtr pkt)
Definition: AbstractController.cc:399
gem5::Packet::suppressFuncError
bool suppressFuncError() const
Definition: packet.hh:745
gem5::Packet::isLLSC
bool isLLSC() const
Definition: packet.hh:609
gem5::ruby::RubyPort::PioRequestPort::PioRequestPort
PioRequestPort(const std::string &_name, RubyPort *_port)
Definition: RubyPort.cc:136
gem5::ruby::RubyPort::RubyPort
RubyPort(const Params &p)
Definition: RubyPort.cc:61
gem5::ruby::getOffset
Addr getOffset(Addr addr)
Definition: Address.cc:54
gem5::ruby::RubyPort::outstandingCount
virtual int outstandingCount() const =0
gem5::MipsISA::l
Bitfield< 5 > l
Definition: pra_constants.hh:323
gem5::ruby::RubyPort::memRequestPort
MemRequestPort memRequestPort
Definition: RubyPort.hh:218
gem5::Port::isConnected
bool isConnected() const
Is this port currently connected to a peer?
Definition: port.hh:133
ss
std::stringstream ss
Definition: trace.test.cc:45
compiler.hh
gem5::DrainState::Drained
@ Drained
Buffers drained, ready for serialization/handover.
gem5::Packet::cmd
MemCmd cmd
The command field of the packet.
Definition: packet.hh:361
gem5::Packet::needsResponse
bool needsResponse() const
Definition: packet.hh:597
gem5::ruby::RubyPort::testDrainComplete
void testDrainComplete()
Definition: RubyPort.cc:504
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
name
const std::string & name()
Definition: trace.cc:49
gem5::ruby::RubyPort::PioRequestPort
Definition: RubyPort.hh:112
gem5::ruby::RubyPort::m_ruby_system
RubySystem * m_ruby_system
Definition: RubyPort.hh:195
gem5::ClockedObject
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
Definition: clocked_object.hh:234
gem5::ResponsePort::sendRangeChange
void sendRangeChange() const
Called by the owner to send a range change.
Definition: port.hh:296
full_system.hh
gem5::Packet::popSenderState
SenderState * popSenderState()
Pop the top of the state stack and return a pointer to it.
Definition: packet.cc:324
gem5::Drainable::signalDrainDone
void signalDrainDone() const
Signal that an object is drained.
Definition: drain.hh:305
gem5::MemCmd::WriteCompleteResp
@ WriteCompleteResp
Definition: packet.hh:91
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:220
gem5::System::isDeviceMemAddr
bool isDeviceMemAddr(const PacketPtr &pkt) const
Similar to isMemAddr but for devices.
Definition: system.cc:357
gem5::ruby::RubySystem
Definition: RubySystem.hh:63
gem5::ruby::RubyPort::functionalWrite
virtual int functionalWrite(Packet *func_pkt)
Definition: RubyPort.cc:688
gem5::ruby::RubyPort::PioResponsePort::getAddrRanges
AddrRangeList getAddrRanges() const
Get a list of the non-overlapping address ranges the owner is responsible for.
Definition: RubyPort.cc:614
gem5::Packet::isFlush
bool isFlush() const
Definition: packet.hh:612
gem5::ruby::RubyPort::PioResponsePort::recvAtomic
Tick recvAtomic(PacketPtr pkt)
Receive an atomic request packet from the peer.
Definition: RubyPort.cc:230
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::ruby::RubyPort::Params
RubyPortParams Params
Definition: RubyPort.hh:153
gem5::ruby::RubyPort::m_controller
AbstractController * m_controller
Definition: RubyPort.hh:197
gem5::Packet::makeResponse
void makeResponse()
Take a request packet and modify it in place to be suitable for returning as a response to that reque...
Definition: packet.hh:1031
gem5::ruby::RubyPort::addToRetryList
void addToRetryList(MemResponsePort *port)
Definition: RubyPort.hh:210
gem5::MemCmd::InvalidateReq
@ InvalidateReq
Definition: packet.hh:137
gem5::ArmISA::id
Bitfield< 33 > id
Definition: misc_types.hh:251
gem5::MipsISA::r
r
Definition: pra_constants.hh:98
gem5::QueuedRequestPort::schedTimingReq
void schedTimingReq(PacketPtr pkt, Tick when)
Schedule the sending of a timing request.
Definition: qport.hh:149
gem5::ruby::RubyPort::onRetryList
bool onRetryList(MemResponsePort *port)
Definition: RubyPort.hh:205
gem5::Clocked::ticksToCycles
Cycles ticksToCycles(Tick t) const
Definition: clocked_object.hh:222
gem5::ruby::AbstractController::getMandatoryQueue
virtual MessageBuffer * getMandatoryQueue() const =0
std::list< AddrRange >
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:781
gem5::QueuedResponsePort::schedTimingResp
void schedTimingResp(PacketPtr pkt, Tick when)
Schedule the sending of a timing response.
Definition: qport.hh:93
gem5::memory::AbstractMemory::access
void access(PacketPtr pkt)
Perform an untimed memory access and update all the state (e.g.
Definition: abstract_mem.cc:379
gem5::ruby::RubyPort::PioResponsePort::recvTimingReq
bool recvTimingReq(PacketPtr pkt)
Receive a timing request from the peer.
Definition: RubyPort.cc:209
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::ruby::RubyPort::MemResponsePort::addToRetryList
void addToRetryList()
Definition: RubyPort.cc:378
RubyPort.hh
gem5::ruby::RubyPort
Definition: RubyPort.hh:64
gem5::ruby::MachineID
Definition: MachineID.hh:56
gem5::ruby::RubyPort::drain
DrainState drain() override
Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are pa...
Definition: RubyPort.cc:518
gem5::Packet::isResponse
bool isResponse() const
Definition: packet.hh:587
gem5::ruby::RubyPort::MemRequestPort::MemRequestPort
MemRequestPort(const std::string &_name, RubyPort *_port)
Definition: RubyPort.cc:151
gem5::Packet::getSize
unsigned getSize() const
Definition: packet.hh:791
gem5::Named::_name
const std::string _name
Definition: named.hh:41
gem5::ArmISA::rs
Bitfield< 9, 8 > rs
Definition: misc_types.hh:377
gem5::DrainState::Draining
@ Draining
Draining buffers pending serialization/handover.
gem5::ruby::RubyPort::MemResponsePort::recvTimingReq
bool recvTimingReq(PacketPtr pkt)
Receive a timing request from the peer.
Definition: RubyPort.cc:250
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::Clocked::clockPeriod
Tick clockPeriod() const
Definition: clocked_object.hh:217
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
simple_mem.hh
gem5::SenderState
RubyTester::SenderState SenderState
Definition: Check.cc:40
gem5::ruby::RubyPort::PioRequestPort::recvTimingResp
bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
Definition: RubyPort.cc:172
gem5::ruby::RubyPort::pioRequestPort
PioRequestPort pioRequestPort
Definition: RubyPort.hh:216

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