gem5  v21.1.0.2
cpu_impl.hh
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41 
42 #ifndef __CPU_CHECKER_CPU_IMPL_HH__
43 #define __CPU_CHECKER_CPU_IMPL_HH__
44 
45 #include <list>
46 #include <string>
47 
48 #include "base/refcnt.hh"
49 #include "config/the_isa.hh"
50 #include "cpu/exetrace.hh"
51 #include "cpu/null_static_inst.hh"
52 #include "cpu/reg_class.hh"
53 #include "cpu/simple_thread.hh"
54 #include "cpu/static_inst.hh"
55 #include "cpu/thread_context.hh"
56 #include "cpu/checker/cpu.hh"
57 #include "debug/Checker.hh"
58 #include "sim/full_system.hh"
59 #include "sim/sim_object.hh"
60 #include "sim/stats.hh"
61 
62 namespace gem5
63 {
64 
65 template <class DynInstPtr>
66 void
68 {
69  if (fault != NoFault) {
70  curMacroStaticInst = nullStaticInstPtr;
71  fault->invoke(tc, curStaticInst);
72  thread->decoder.reset();
73  } else {
74  if (curStaticInst) {
75  if (curStaticInst->isLastMicroop())
76  curMacroStaticInst = nullStaticInstPtr;
77  TheISA::PCState pcState = thread->pcState();
78  curStaticInst->advancePC(pcState);
79  thread->pcState(pcState);
80  DPRINTF(Checker, "Advancing PC to %s.\n", thread->pcState());
81  }
82  }
83 }
85 
86 template <class DynInstPtr>
87 void
89 {
90  DPRINTF(Checker, "IRQ detected at PC: %s with %d insts in buffer\n",
91  thread->pcState(), instList.size());
92  DynInstPtr boundaryInst = NULL;
93  if (!instList.empty()) {
94  // Set the instructions as completed and verify as much as possible.
95  DynInstPtr inst;
97 
98  for (itr = instList.begin(); itr != instList.end(); itr++) {
99  (*itr)->setCompleted();
100  }
101 
102  inst = instList.front();
103  boundaryInst = instList.back();
104  verify(inst); // verify the instructions
105  inst = NULL;
106  }
107  if ((!boundaryInst && curMacroStaticInst &&
108  curStaticInst->isDelayedCommit() &&
109  !curStaticInst->isLastMicroop()) ||
110  (boundaryInst && boundaryInst->isDelayedCommit() &&
111  !boundaryInst->isLastMicroop())) {
112  panic("%lli: Trying to take an interrupt in middle of "
113  "a non-interuptable instruction!", curTick());
114  }
115  boundaryInst = NULL;
116  thread->decoder.reset();
117  curMacroStaticInst = nullStaticInstPtr;
118 }
119 
120 template <class DynInstPtr>
121 void
123 {
124  DynInstPtr inst;
125 
126  // Make sure serializing instructions are actually
127  // seen as serializing to commit. instList should be
128  // empty in these cases.
129  if ((completed_inst->isSerializing() ||
130  completed_inst->isSerializeBefore()) &&
131  (!instList.empty() ?
132  (instList.front()->seqNum != completed_inst->seqNum) : 0)) {
133  panic("%lli: Instruction sn:%lli at PC %s is serializing before but is"
134  " entering instList with other instructions\n", curTick(),
135  completed_inst->seqNum, completed_inst->pcState());
136  }
137 
138  // Either check this instruction, or add it to a list of
139  // instructions waiting to be checked. Instructions must be
140  // checked in program order, so if a store has committed yet not
141  // completed, there may be some instructions that are waiting
142  // behind it that have completed and must be checked.
143  if (!instList.empty()) {
144  if (youngestSN < completed_inst->seqNum) {
145  DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%s to list\n",
146  completed_inst->seqNum, completed_inst->pcState());
147  instList.push_back(completed_inst);
148  youngestSN = completed_inst->seqNum;
149  }
150 
151  if (!instList.front()->isCompleted()) {
152  return;
153  } else {
154  inst = instList.front();
155  instList.pop_front();
156  }
157  } else {
158  if (!completed_inst->isCompleted()) {
159  if (youngestSN < completed_inst->seqNum) {
160  DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%s to list\n",
161  completed_inst->seqNum, completed_inst->pcState());
162  instList.push_back(completed_inst);
163  youngestSN = completed_inst->seqNum;
164  }
165  return;
166  } else {
167  if (youngestSN < completed_inst->seqNum) {
168  inst = completed_inst;
169  youngestSN = completed_inst->seqNum;
170  } else {
171  return;
172  }
173  }
174  }
175 
176  // Make sure a serializing instruction is actually seen as
177  // serializing. instList should be empty here
178  if (inst->isSerializeAfter() && !instList.empty()) {
179  panic("%lli: Instruction sn:%lli at PC %s is serializing after but is"
180  " exiting instList with other instructions\n", curTick(),
181  completed_inst->seqNum, completed_inst->pcState());
182  }
183  unverifiedInst = inst;
184  inst = NULL;
185 
186  auto &decoder = thread->decoder;
187  const Addr pc_mask = decoder.pcMask();
188 
189  // Try to check all instructions that are completed, ending if we
190  // run out of instructions to check or if an instruction is not
191  // yet completed.
192  while (1) {
193  DPRINTF(Checker, "Processing instruction [sn:%lli] PC:%s.\n",
194  unverifiedInst->seqNum, unverifiedInst->pcState());
195  unverifiedReq = NULL;
196  unverifiedReq = unverifiedInst->reqToVerify;
197  unverifiedMemData = unverifiedInst->memData;
198  // Make sure results queue is empty
199  while (!result.empty()) {
200  result.pop();
201  }
202  baseStats.numCycles++;
203 
204  Fault fault = NoFault;
205 
206  // maintain $r0 semantics
207  thread->setIntReg(zeroReg, 0);
208 
209  // Check if any recent PC changes match up with anything we
210  // expect to happen. This is mostly to check if traps or
211  // PC-based events have occurred in both the checker and CPU.
212  if (changedPC) {
213  DPRINTF(Checker, "Changed PC recently to %s\n",
214  thread->pcState());
215  if (willChangePC) {
216  if (newPCState == thread->pcState()) {
217  DPRINTF(Checker, "Changed PC matches expected PC\n");
218  } else {
219  warn("%lli: Changed PC does not match expected PC, "
220  "changed: %s, expected: %s",
221  curTick(), thread->pcState(), newPCState);
223  }
224  willChangePC = false;
225  }
226  changedPC = false;
227  }
228 
229  // Try to fetch the instruction
230  uint64_t fetchOffset = 0;
231  bool fetchDone = false;
232  while (!fetchDone) {
233  Addr fetch_PC = thread->instAddr();
234  fetch_PC = (fetch_PC & pc_mask) + fetchOffset;
235 
236  // If not in the middle of a macro instruction
237  if (!curMacroStaticInst) {
238  // set up memory request for instruction fetch
239  auto mem_req = std::make_shared<Request>(
240  fetch_PC, decoder.moreBytesSize(), 0, requestorId,
241  fetch_PC, thread->contextId());
242 
243  mem_req->setVirt(fetch_PC, decoder.moreBytesSize(),
244  Request::INST_FETCH, requestorId,
245  thread->instAddr());
246 
247  fault = mmu->translateFunctional(
248  mem_req, tc, BaseMMU::Execute);
249 
250  if (fault != NoFault) {
251  if (unverifiedInst->getFault() == NoFault) {
252  // In this case the instruction was not a dummy
253  // instruction carrying an ITB fault. In the single
254  // threaded case the ITB should still be able to
255  // translate this instruction; in the SMT case it's
256  // possible that its ITB entry was kicked out.
257  warn("%lli: Instruction PC %s was not found in the "
258  "ITB!", curTick(), thread->pcState());
259  handleError(unverifiedInst);
260 
261  // go to the next instruction
262  advancePC(NoFault);
263 
264  // Give up on an ITB fault..
265  unverifiedInst = NULL;
266  return;
267  } else {
268  // The instruction is carrying an ITB fault. Handle
269  // the fault and see if our results match the CPU on
270  // the next tick().
271  fault = unverifiedInst->getFault();
272  break;
273  }
274  } else {
275  PacketPtr pkt = new Packet(mem_req, MemCmd::ReadReq);
276 
277  pkt->dataStatic(decoder.moreBytesPtr());
278  icachePort->sendFunctional(pkt);
279 
280  delete pkt;
281  }
282  }
283 
284  if (fault == NoFault) {
285  TheISA::PCState pcState = thread->pcState();
286 
287  if (isRomMicroPC(pcState.microPC())) {
288  fetchDone = true;
289  curStaticInst = decoder.fetchRomMicroop(
290  pcState.microPC(), nullptr);
291  } else if (!curMacroStaticInst) {
292  //We're not in the middle of a macro instruction
293  StaticInstPtr instPtr = nullptr;
294 
295  //Predecode, ie bundle up an ExtMachInst
296  //If more fetch data is needed, pass it in.
297  Addr fetchPC =
298  (pcState.instAddr() & pc_mask) + fetchOffset;
299  decoder.moreBytes(pcState, fetchPC);
300 
301  //If an instruction is ready, decode it.
302  //Otherwise, we'll have to fetch beyond the
303  //memory chunk at the current pc.
304  if (decoder.instReady()) {
305  fetchDone = true;
306  instPtr = decoder.decode(pcState);
307  thread->pcState(pcState);
308  } else {
309  fetchDone = false;
310  fetchOffset += decoder.moreBytesSize();
311  }
312 
313  //If we decoded an instruction and it's microcoded,
314  //start pulling out micro ops
315  if (instPtr && instPtr->isMacroop()) {
316  curMacroStaticInst = instPtr;
317  curStaticInst =
318  instPtr->fetchMicroop(pcState.microPC());
319  } else {
320  curStaticInst = instPtr;
321  }
322  } else {
323  // Read the next micro op from the macro-op
324  curStaticInst =
325  curMacroStaticInst->fetchMicroop(pcState.microPC());
326  fetchDone = true;
327  }
328  }
329  }
330  // reset decoder on Checker
331  decoder.reset();
332 
333  // Check Checker and CPU get same instruction, and record
334  // any faults the CPU may have had.
335  Fault unverifiedFault;
336  if (fault == NoFault) {
337  unverifiedFault = unverifiedInst->getFault();
338 
339  // Checks that the instruction matches what we expected it to be.
340  // Checks both the machine instruction and the PC.
341  validateInst(unverifiedInst);
342  }
343 
344  // keep an instruction count
345  numInst++;
346 
347 
348  // Either the instruction was a fault and we should process the fault,
349  // or we should just go ahead execute the instruction. This assumes
350  // that the instruction is properly marked as a fault.
351  if (fault == NoFault) {
352  // Execute Checker instruction and trace
353  if (!unverifiedInst->isUnverifiable()) {
354  Trace::InstRecord *traceData = tracer->getInstRecord(curTick(),
355  tc,
356  curStaticInst,
357  pcState(),
358  curMacroStaticInst);
359  fault = curStaticInst->execute(this, traceData);
360  if (traceData) {
361  traceData->dump();
362  delete traceData;
363  }
364  }
365 
366  if (fault == NoFault && unverifiedFault == NoFault) {
367  // Checks to make sure instrution results are correct.
368  validateExecution(unverifiedInst);
369 
370  if (curStaticInst->isLoad()) {
371  ++numLoad;
372  }
373  } else if (fault != NoFault && unverifiedFault == NoFault) {
374  panic("%lli: sn: %lli at PC: %s took a fault in checker "
375  "but not in driver CPU\n", curTick(),
376  unverifiedInst->seqNum, unverifiedInst->pcState());
377  } else if (fault == NoFault && unverifiedFault != NoFault) {
378  panic("%lli: sn: %lli at PC: %s took a fault in driver "
379  "CPU but not in checker\n", curTick(),
380  unverifiedInst->seqNum, unverifiedInst->pcState());
381  }
382  }
383 
384  // Take any faults here
385  if (fault != NoFault) {
386  if (FullSystem) {
387  fault->invoke(tc, curStaticInst);
388  willChangePC = true;
389  newPCState = thread->pcState();
390  DPRINTF(Checker, "Fault, PC is now %s\n", newPCState);
391  curMacroStaticInst = nullStaticInstPtr;
392  }
393  } else {
394  advancePC(fault);
395  }
396 
397  if (FullSystem) {
398  // @todo: Determine if these should happen only if the
399  // instruction hasn't faulted. In the SimpleCPU case this may
400  // not be true, but in the O3 case this may be true.
401  Addr oldpc;
402  int count = 0;
403  do {
404  oldpc = thread->instAddr();
405  thread->pcEventQueue.service(oldpc, tc);
406  count++;
407  } while (oldpc != thread->instAddr());
408  if (count > 1) {
409  willChangePC = true;
410  newPCState = thread->pcState();
411  DPRINTF(Checker, "PC Event, PC is now %s\n", newPCState);
412  }
413  }
414 
415  // @todo: Optionally can check all registers. (Or just those
416  // that have been modified).
417  validateState();
418 
419  // Continue verifying instructions if there's another completed
420  // instruction waiting to be verified.
421  if (instList.empty()) {
422  break;
423  } else if (instList.front()->isCompleted()) {
424  unverifiedInst = NULL;
425  unverifiedInst = instList.front();
426  instList.pop_front();
427  } else {
428  break;
429  }
430  }
431  unverifiedInst = NULL;
432 }
433 
434 template <class DynInstPtr>
435 void
437 {
438  instList.clear();
439 }
440 
441 template <class DynInstPtr>
443 
444 template <class DynInstPtr>
445 void
447 {
448  if (inst->instAddr() != thread->instAddr()) {
449  warn("%lli: PCs do not match! Inst: %s, checker: %s",
450  curTick(), inst->pcState(), thread->pcState());
451  if (changedPC) {
452  warn("%lli: Changed PCs recently, may not be an error",
453  curTick());
454  } else {
455  handleError(inst);
456  }
457  }
458 
459  if (curStaticInst != inst->staticInst) {
460  warn("%lli: StaticInstPtrs don't match. (%s, %s).\n", curTick(),
461  curStaticInst->getName(), inst->staticInst->getName());
462  }
463 }
464 
465 template <class DynInstPtr>
466 void
468 {
469  InstResult checker_val;
470  InstResult inst_val;
471  int idx = -1;
472  bool result_mismatch = false;
473  bool scalar_mismatch = false;
474  bool vector_mismatch = false;
475 
476  if (inst->isUnverifiable()) {
477  // Unverifiable instructions assume they were executed
478  // properly by the CPU. Grab the result from the
479  // instruction and write it to the register.
480  copyResult(inst, InstResult(0ul, InstResult::ResultType::Scalar), idx);
481  } else if (inst->numDestRegs() > 0 && !result.empty()) {
482  DPRINTF(Checker, "Dest regs %d, number of checker dest regs %d\n",
483  inst->numDestRegs(), result.size());
484  for (int i = 0; i < inst->numDestRegs() && !result.empty(); i++) {
485  checker_val = result.front();
486  result.pop();
487  inst_val = inst->popResult(
489  if (checker_val != inst_val) {
490  result_mismatch = true;
491  idx = i;
492  scalar_mismatch = checker_val.isScalar();
493  vector_mismatch = checker_val.isVector();
494  panic_if(!(scalar_mismatch || vector_mismatch),
495  "Unknown type of result\n");
496  }
497  }
498  } // Checker CPU checks all the saved results in the dyninst passed by
499  // the cpu model being checked against the saved results present in
500  // the static inst executed in the Checker. Sometimes the number
501  // of saved results differs between the dyninst and static inst, but
502  // this is ok and not a bug. May be worthwhile to try and correct this.
503 
504  if (result_mismatch) {
505  if (scalar_mismatch) {
506  warn("%lli: Instruction results (%i) do not match! (Values may"
507  " not actually be integers) Inst: %#x, checker: %#x",
508  curTick(), idx, inst_val.asIntegerNoAssert(),
509  checker_val.asInteger());
510  }
511 
512  // It's useful to verify load values from memory, but in MP
513  // systems the value obtained at execute may be different than
514  // the value obtained at completion. Similarly DMA can
515  // present the same problem on even UP systems. Thus there is
516  // the option to only warn on loads having a result error.
517  // The load/store queue in Detailed CPU can also cause problems
518  // if load/store forwarding is allowed.
519  if (inst->isLoad() && warnOnlyOnLoadError) {
520  copyResult(inst, inst_val, idx);
521  } else {
522  handleError(inst);
523  }
524  }
525 
526  if (inst->nextInstAddr() != thread->nextInstAddr()) {
527  warn("%lli: Instruction next PCs do not match! Inst: %#x, "
528  "checker: %#x",
529  curTick(), inst->nextInstAddr(), thread->nextInstAddr());
530  handleError(inst);
531  }
532 
533  // Checking side effect registers can be difficult if they are not
534  // checked simultaneously with the execution of the instruction.
535  // This is because other valid instructions may have modified
536  // these registers in the meantime, and their values are not
537  // stored within the DynInst.
538  while (!miscRegIdxs.empty()) {
539  int misc_reg_idx = miscRegIdxs.front();
540  miscRegIdxs.pop();
541 
542  if (inst->tcBase()->readMiscRegNoEffect(misc_reg_idx) !=
543  thread->readMiscRegNoEffect(misc_reg_idx)) {
544  warn("%lli: Misc reg idx %i (side effect) does not match! "
545  "Inst: %#x, checker: %#x",
546  curTick(), misc_reg_idx,
547  inst->tcBase()->readMiscRegNoEffect(misc_reg_idx),
548  thread->readMiscRegNoEffect(misc_reg_idx));
549  handleError(inst);
550  }
551  }
552 }
553 
554 
555 // This function is weird, if it is called it means the Checker and
556 // O3 have diverged, so panic is called for now. It may be useful
557 // to resynch states and continue if the divergence is a false positive
558 template <class DynInstPtr>
559 void
561 {
562  if (updateThisCycle) {
563  // Change this back to warn if divergences end up being false positives
564  panic("%lli: Instruction PC %#x results didn't match up, copying all "
565  "registers from main CPU", curTick(), unverifiedInst->instAddr());
566 
567  // Terribly convoluted way to make sure O3 model does not implode
568  bool no_squash_from_TC = unverifiedInst->thread->noSquashFromTC;
569  unverifiedInst->thread->noSquashFromTC = true;
570 
571  // Heavy-weight copying of all registers
572  thread->copyArchRegs(unverifiedInst->tcBase());
573  unverifiedInst->thread->noSquashFromTC = no_squash_from_TC;
574 
575  // Set curStaticInst to unverifiedInst->staticInst
576  curStaticInst = unverifiedInst->staticInst;
577  // Also advance the PC. Hopefully no PC-based events happened.
578  advancePC(NoFault);
579  updateThisCycle = false;
580  }
581 }
582 
583 template <class DynInstPtr>
584 void
586  const DynInstPtr &inst, const InstResult& mismatch_val, int start_idx)
587 {
588  // We've already popped one dest off the queue,
589  // so do the fix-up then start with the next dest reg;
590  if (start_idx >= 0) {
591  const RegId& idx = inst->destRegIdx(start_idx);
592  switch (idx.classValue()) {
593  case IntRegClass:
594  panic_if(!mismatch_val.isScalar(), "Unexpected type of result");
595  thread->setIntReg(idx.index(), mismatch_val.asInteger());
596  break;
597  case FloatRegClass:
598  panic_if(!mismatch_val.isScalar(), "Unexpected type of result");
599  thread->setFloatReg(idx.index(), mismatch_val.asInteger());
600  break;
601  case VecRegClass:
602  panic_if(!mismatch_val.isVector(), "Unexpected type of result");
603  thread->setVecReg(idx, mismatch_val.asVector());
604  break;
605  case VecElemClass:
606  panic_if(!mismatch_val.isVecElem(),
607  "Unexpected type of result");
608  thread->setVecElem(idx, mismatch_val.asVectorElem());
609  break;
610  case CCRegClass:
611  panic_if(!mismatch_val.isScalar(), "Unexpected type of result");
612  thread->setCCReg(idx.index(), mismatch_val.asInteger());
613  break;
614  case MiscRegClass:
615  panic_if(!mismatch_val.isScalar(), "Unexpected type of result");
616  thread->setMiscReg(idx.index(), mismatch_val.asInteger());
617  break;
618  default:
619  panic("Unknown register class: %d", (int)idx.classValue());
620  }
621  }
622  start_idx++;
623  InstResult res;
624  for (int i = start_idx; i < inst->numDestRegs(); i++) {
625  const RegId& idx = inst->destRegIdx(i);
626  res = inst->popResult();
627  switch (idx.classValue()) {
628  case IntRegClass:
629  panic_if(!res.isScalar(), "Unexpected type of result");
630  thread->setIntReg(idx.index(), res.asInteger());
631  break;
632  case FloatRegClass:
633  panic_if(!res.isScalar(), "Unexpected type of result");
634  thread->setFloatReg(idx.index(), res.asInteger());
635  break;
636  case VecRegClass:
637  panic_if(!res.isVector(), "Unexpected type of result");
638  thread->setVecReg(idx, res.asVector());
639  break;
640  case VecElemClass:
641  panic_if(!res.isVecElem(), "Unexpected type of result");
642  thread->setVecElem(idx, res.asVectorElem());
643  break;
644  case CCRegClass:
645  panic_if(!res.isScalar(), "Unexpected type of result");
646  thread->setCCReg(idx.index(), res.asInteger());
647  break;
648  case MiscRegClass:
649  panic_if(res.isValid(), "MiscReg expecting invalid result");
650  // Try to get the proper misc register index for ARM here...
651  thread->setMiscReg(idx.index(), 0);
652  break;
653  // else Register is out of range...
654  default:
655  panic("Unknown register class: %d", (int)idx.classValue());
656  }
657  }
658 }
659 
660 template <class DynInstPtr>
661 void
663 {
664  cprintf("Error detected, instruction information:\n");
665  cprintf("PC:%s, nextPC:%#x\n[sn:%lli]\n[tid:%i]\n"
666  "Completed:%i\n",
667  inst->pcState(),
668  inst->nextInstAddr(),
669  inst->seqNum,
670  inst->threadNumber,
671  inst->isCompleted());
672  inst->dump();
674 }
675 
676 template <class DynInstPtr>
677 void
679 {
680  int num = 0;
681 
682  InstListIt inst_list_it = --(instList.end());
683 
684  cprintf("Inst list size: %i\n", instList.size());
685 
686  while (inst_list_it != instList.end())
687  {
688  cprintf("Instruction:%i\n",
689  num);
690 
691  cprintf("PC:%s\n[sn:%lli]\n[tid:%i]\n"
692  "Completed:%i\n",
693  (*inst_list_it)->pcState(),
694  (*inst_list_it)->seqNum,
695  (*inst_list_it)->threadNumber,
696  (*inst_list_it)->isCompleted());
697 
698  cprintf("\n");
699 
700  inst_list_it--;
701  ++num;
702  }
703 
704 }
705 
706 } // namespace gem5
707 
708 #endif//__CPU_CHECKER_CPU_IMPL_HH__
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
refcnt.hh
gem5::VecElemClass
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:62
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:64
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::Checker::validateInst
void validateInst(const DynInstPtr &inst)
Definition: cpu_impl.hh:446
gem5::InstResult::isVector
bool isVector() const
Is this a vector result?.
Definition: inst_res.hh:158
warn
#define warn(...)
Definition: logging.hh:245
gem5::Checker::verify
void verify(const DynInstPtr &inst)
Definition: cpu_impl.hh:122
gem5::cprintf
void cprintf(const char *format, const Args &...args)
Definition: cprintf.hh:155
gem5::CheckerCPU::pcState
TheISA::PCState pcState() const override
Definition: cpu.hh:395
gem5::Checker::advancePC
void advancePC(const Fault &fault)
Definition: cpu_impl.hh:67
gem5::isRomMicroPC
static bool isRomMicroPC(MicroPC upc)
Definition: types.hh:166
gem5::InstResult::ResultType::Scalar
@ Scalar
gem5::o3::DynInstPtr
RefCountingPtr< DynInst > DynInstPtr
Definition: dyn_inst_ptr.hh:55
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:58
gem5::InstResult::isScalar
bool isScalar() const
Checks.
Definition: inst_res.hh:156
exetrace.hh
gem5::MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:65
gem5::InstResult::asVectorElem
const TheISA::VecElem & asVectorElem() const
Definition: inst_res.hh:192
gem5::RegId::classValue
RegClass classValue() const
Class accessor.
Definition: reg_class.hh:180
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::Checker::copyResult
void copyResult(const DynInstPtr &inst, const InstResult &mismatch_val, int start_idx)
Definition: cpu_impl.hh:585
gem5::RegId::index
RegIndex index() const
Index accessors.
Definition: reg_class.hh:154
gem5::Checker::handlePendingInt
void handlePendingInt()
Definition: cpu_impl.hh:88
gem5::BaseMMU::Execute
@ Execute
Definition: mmu.hh:53
gem5::RefCountingPtr< StaticInst >
gem5::StaticInst::fetchMicroop
virtual StaticInstPtr fetchMicroop(MicroPC upc) const
Return the microop that goes with a particular micropc.
Definition: static_inst.cc:54
gem5::CheckerCPU::dumpAndExit
void dumpAndExit()
Definition: cpu.cc:373
gem5::Packet::dataStatic
void dataStatic(T *p)
Set the data pointer to the following value that should not be freed.
Definition: packet.hh:1134
stats.hh
gem5::nullStaticInstPtr
const StaticInstPtr nullStaticInstPtr
Statically allocated null StaticInstPtr.
Definition: null_static_inst.cc:36
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
sim_object.hh
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::X86ISA::count
count
Definition: misc.hh:709
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::InstResult::isValid
bool isValid() const
Is this a valid result?.
Definition: inst_res.hh:164
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::probing::Packet
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:109
cpu.hh
gem5::Request::INST_FETCH
@ INST_FETCH
The request was an instruction fetch.
Definition: request.hh:115
gem5::MemCmd::ReadReq
@ ReadReq
Definition: packet.hh:86
gem5::BaseCPU
Definition: base.hh:107
static_inst.hh
gem5::Checker::validateExecution
void validateExecution(const DynInstPtr &inst)
Definition: cpu_impl.hh:467
null_static_inst.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::InstResult::asInteger
const uint64_t & asInteger() const
Explicit cast-like operations.
Definition: inst_res.hh:170
full_system.hh
gem5::Trace::InstRecord::dump
virtual void dump()=0
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:223
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:60
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
gem5::CheckerCPU::handleError
void handleError()
Definition: cpu.hh:530
simple_thread.hh
gem5::Checker::takeOverFrom
void takeOverFrom(BaseCPU *oldCPU)
Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be sw...
Definition: cpu_impl.hh:442
gem5::InstResult::asIntegerNoAssert
const uint64_t & asIntegerNoAssert() const
Cast to integer without checking type.
Definition: inst_res.hh:181
gem5::Checker< gem5::RefCountingPtr >::InstListIt
std::list< gem5::RefCountingPtr >::iterator InstListIt
Definition: cpu.hh:604
gem5::InstResult::asVector
const TheISA::VecRegContainer & asVector() const
Definition: inst_res.hh:186
gem5::StaticInst::isMacroop
bool isMacroop() const
Definition: static_inst.hh:207
reg_class.hh
gem5::Checker::switchOut
void switchOut()
Prepare for another CPU to take over execution.
Definition: cpu_impl.hh:436
gem5::Checker::validateState
void validateState()
Definition: cpu_impl.hh:560
decoder
output decoder
Definition: nop.cc:61
gem5::Trace::InstRecord
Definition: insttracer.hh:58
std::list
STL list class.
Definition: stl.hh:51
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:57
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::InstResult::isVecElem
bool isVecElem() const
Is this a vector element result?.
Definition: inst_res.hh:160
gem5::Checker
Templated Checker class.
Definition: cpu.hh:565
thread_context.hh
gem5::Checker::dumpInsts
void dumpInsts()
Definition: cpu_impl.hh:678
gem5::InstResult
Definition: inst_res.hh:49
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177

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