gem5  v21.2.1.1
cpu_impl.hh
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41 
42 #ifndef __CPU_CHECKER_CPU_IMPL_HH__
43 #define __CPU_CHECKER_CPU_IMPL_HH__
44 
45 #include <list>
46 #include <string>
47 
48 #include "base/refcnt.hh"
49 #include "config/the_isa.hh"
50 #include "cpu/exetrace.hh"
51 #include "cpu/null_static_inst.hh"
52 #include "cpu/reg_class.hh"
53 #include "cpu/simple_thread.hh"
54 #include "cpu/static_inst.hh"
55 #include "cpu/thread_context.hh"
56 #include "cpu/checker/cpu.hh"
57 #include "debug/Checker.hh"
58 #include "sim/full_system.hh"
59 #include "sim/sim_object.hh"
60 #include "sim/stats.hh"
61 
62 namespace gem5
63 {
64 
65 template <class DynInstPtr>
66 void
68 {
69  if (fault != NoFault) {
70  curMacroStaticInst = nullStaticInstPtr;
71  fault->invoke(tc, curStaticInst);
72  thread->decoder->reset();
73  } else {
74  if (curStaticInst) {
75  if (curStaticInst->isLastMicroop())
76  curMacroStaticInst = nullStaticInstPtr;
77  curStaticInst->advancePC(thread);
78  DPRINTF(Checker, "Advancing PC to %s.\n", thread->pcState());
79  }
80  }
81 }
83 
84 template <class DynInstPtr>
85 void
87 {
88  DPRINTF(Checker, "IRQ detected at PC: %s with %d insts in buffer\n",
89  thread->pcState(), instList.size());
90  DynInstPtr boundaryInst = NULL;
91  if (!instList.empty()) {
92  // Set the instructions as completed and verify as much as possible.
93  DynInstPtr inst;
95 
96  for (itr = instList.begin(); itr != instList.end(); itr++) {
97  (*itr)->setCompleted();
98  }
99 
100  inst = instList.front();
101  boundaryInst = instList.back();
102  verify(inst); // verify the instructions
103  inst = NULL;
104  }
105  if ((!boundaryInst && curMacroStaticInst &&
106  curStaticInst->isDelayedCommit() &&
107  !curStaticInst->isLastMicroop()) ||
108  (boundaryInst && boundaryInst->isDelayedCommit() &&
109  !boundaryInst->isLastMicroop())) {
110  panic("%lli: Trying to take an interrupt in middle of "
111  "a non-interuptable instruction!", curTick());
112  }
113  boundaryInst = NULL;
114  thread->decoder->reset();
115  curMacroStaticInst = nullStaticInstPtr;
116 }
117 
118 template <class DynInstPtr>
119 void
121 {
122  DynInstPtr inst;
123 
124  // Make sure serializing instructions are actually
125  // seen as serializing to commit. instList should be
126  // empty in these cases.
127  if ((completed_inst->isSerializing() ||
128  completed_inst->isSerializeBefore()) &&
129  (!instList.empty() ?
130  (instList.front()->seqNum != completed_inst->seqNum) : 0)) {
131  panic("%lli: Instruction sn:%lli at PC %s is serializing before but is"
132  " entering instList with other instructions\n", curTick(),
133  completed_inst->seqNum, completed_inst->pcState());
134  }
135 
136  // Either check this instruction, or add it to a list of
137  // instructions waiting to be checked. Instructions must be
138  // checked in program order, so if a store has committed yet not
139  // completed, there may be some instructions that are waiting
140  // behind it that have completed and must be checked.
141  if (!instList.empty()) {
142  if (youngestSN < completed_inst->seqNum) {
143  DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%s to list\n",
144  completed_inst->seqNum, completed_inst->pcState());
145  instList.push_back(completed_inst);
146  youngestSN = completed_inst->seqNum;
147  }
148 
149  if (!instList.front()->isCompleted()) {
150  return;
151  } else {
152  inst = instList.front();
153  instList.pop_front();
154  }
155  } else {
156  if (!completed_inst->isCompleted()) {
157  if (youngestSN < completed_inst->seqNum) {
158  DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%s to list\n",
159  completed_inst->seqNum, completed_inst->pcState());
160  instList.push_back(completed_inst);
161  youngestSN = completed_inst->seqNum;
162  }
163  return;
164  } else {
165  if (youngestSN < completed_inst->seqNum) {
166  inst = completed_inst;
167  youngestSN = completed_inst->seqNum;
168  } else {
169  return;
170  }
171  }
172  }
173 
174  // Make sure a serializing instruction is actually seen as
175  // serializing. instList should be empty here
176  if (inst->isSerializeAfter() && !instList.empty()) {
177  panic("%lli: Instruction sn:%lli at PC %s is serializing after but is"
178  " exiting instList with other instructions\n", curTick(),
179  completed_inst->seqNum, completed_inst->pcState());
180  }
181  unverifiedInst = inst;
182  inst = NULL;
183 
184  auto &decoder = thread->decoder;
185  const Addr pc_mask = decoder->pcMask();
186 
187  // Try to check all instructions that are completed, ending if we
188  // run out of instructions to check or if an instruction is not
189  // yet completed.
190  while (1) {
191  DPRINTF(Checker, "Processing instruction [sn:%lli] PC:%s.\n",
192  unverifiedInst->seqNum, unverifiedInst->pcState());
193  unverifiedReq = NULL;
194  unverifiedReq = unverifiedInst->reqToVerify;
195  unverifiedMemData = unverifiedInst->memData;
196  // Make sure results queue is empty
197  while (!result.empty()) {
198  result.pop();
199  }
200  baseStats.numCycles++;
201 
202  Fault fault = NoFault;
203 
204  // maintain $r0 semantics
205  thread->setIntReg(zeroReg, 0);
206 
207  // Check if any recent PC changes match up with anything we
208  // expect to happen. This is mostly to check if traps or
209  // PC-based events have occurred in both the checker and CPU.
210  if (changedPC) {
211  DPRINTF(Checker, "Changed PC recently to %s\n",
212  thread->pcState());
213  if (willChangePC) {
214  if (*newPCState == thread->pcState()) {
215  DPRINTF(Checker, "Changed PC matches expected PC\n");
216  } else {
217  warn("%lli: Changed PC does not match expected PC, "
218  "changed: %s, expected: %s",
219  curTick(), thread->pcState(), *newPCState);
221  }
222  willChangePC = false;
223  }
224  changedPC = false;
225  }
226 
227  // Try to fetch the instruction
228  uint64_t fetchOffset = 0;
229  bool fetchDone = false;
230  while (!fetchDone) {
231  Addr fetch_PC = thread->pcState().instAddr();
232  fetch_PC = (fetch_PC & pc_mask) + fetchOffset;
233 
234  // If not in the middle of a macro instruction
235  if (!curMacroStaticInst) {
236  // set up memory request for instruction fetch
237  auto mem_req = std::make_shared<Request>(
238  fetch_PC, decoder->moreBytesSize(), 0, requestorId,
239  fetch_PC, thread->contextId());
240 
241  mem_req->setVirt(fetch_PC, decoder->moreBytesSize(),
242  Request::INST_FETCH, requestorId,
243  thread->pcState().instAddr());
244 
245  fault = mmu->translateFunctional(
246  mem_req, tc, BaseMMU::Execute);
247 
248  if (fault != NoFault) {
249  if (unverifiedInst->getFault() == NoFault) {
250  // In this case the instruction was not a dummy
251  // instruction carrying an ITB fault. In the single
252  // threaded case the ITB should still be able to
253  // translate this instruction; in the SMT case it's
254  // possible that its ITB entry was kicked out.
255  warn("%lli: Instruction PC %s was not found in the "
256  "ITB!", curTick(), thread->pcState());
257  handleError(unverifiedInst);
258 
259  // go to the next instruction
260  advancePC(NoFault);
261 
262  // Give up on an ITB fault..
263  unverifiedInst = NULL;
264  return;
265  } else {
266  // The instruction is carrying an ITB fault. Handle
267  // the fault and see if our results match the CPU on
268  // the next tick().
269  fault = unverifiedInst->getFault();
270  break;
271  }
272  } else {
273  PacketPtr pkt = new Packet(mem_req, MemCmd::ReadReq);
274 
275  pkt->dataStatic(decoder->moreBytesPtr());
276  icachePort->sendFunctional(pkt);
277 
278  delete pkt;
279  }
280  }
281 
282  if (fault == NoFault) {
283  std::unique_ptr<PCStateBase> pc_state(
284  thread->pcState().clone());
285 
286  if (isRomMicroPC(pc_state->microPC())) {
287  fetchDone = true;
288  curStaticInst = decoder->fetchRomMicroop(
289  pc_state->microPC(), nullptr);
290  } else if (!curMacroStaticInst) {
291  //We're not in the middle of a macro instruction
292  StaticInstPtr instPtr = nullptr;
293 
294  //Predecode, ie bundle up an ExtMachInst
295  //If more fetch data is needed, pass it in.
296  Addr fetch_pc =
297  (pc_state->instAddr() & pc_mask) + fetchOffset;
298  decoder->moreBytes(*pc_state, fetch_pc);
299 
300  //If an instruction is ready, decode it.
301  //Otherwise, we'll have to fetch beyond the
302  //memory chunk at the current pc.
303  if (decoder->instReady()) {
304  fetchDone = true;
305  instPtr = decoder->decode(*pc_state);
306  thread->pcState(*pc_state);
307  } else {
308  fetchDone = false;
309  fetchOffset += decoder->moreBytesSize();
310  }
311 
312  //If we decoded an instruction and it's microcoded,
313  //start pulling out micro ops
314  if (instPtr && instPtr->isMacroop()) {
315  curMacroStaticInst = instPtr;
316  curStaticInst =
317  instPtr->fetchMicroop(pc_state->microPC());
318  } else {
319  curStaticInst = instPtr;
320  }
321  } else {
322  // Read the next micro op from the macro-op
323  curStaticInst =
324  curMacroStaticInst->fetchMicroop(pc_state->microPC());
325  fetchDone = true;
326  }
327  }
328  }
329  // reset decoder on Checker
330  decoder->reset();
331 
332  // Check Checker and CPU get same instruction, and record
333  // any faults the CPU may have had.
334  Fault unverifiedFault;
335  if (fault == NoFault) {
336  unverifiedFault = unverifiedInst->getFault();
337 
338  // Checks that the instruction matches what we expected it to be.
339  // Checks both the machine instruction and the PC.
340  validateInst(unverifiedInst);
341  }
342 
343  // keep an instruction count
344  numInst++;
345 
346 
347  // Either the instruction was a fault and we should process the fault,
348  // or we should just go ahead execute the instruction. This assumes
349  // that the instruction is properly marked as a fault.
350  if (fault == NoFault) {
351  // Execute Checker instruction and trace
352  if (!unverifiedInst->isUnverifiable()) {
353  Trace::InstRecord *traceData = tracer->getInstRecord(curTick(),
354  tc,
355  curStaticInst,
356  pcState(),
357  curMacroStaticInst);
358  fault = curStaticInst->execute(this, traceData);
359  if (traceData) {
360  traceData->dump();
361  delete traceData;
362  }
363  }
364 
365  if (fault == NoFault && unverifiedFault == NoFault) {
366  // Checks to make sure instrution results are correct.
367  validateExecution(unverifiedInst);
368 
369  if (curStaticInst->isLoad()) {
370  ++numLoad;
371  }
372  } else if (fault != NoFault && unverifiedFault == NoFault) {
373  panic("%lli: sn: %lli at PC: %s took a fault in checker "
374  "but not in driver CPU\n", curTick(),
375  unverifiedInst->seqNum, unverifiedInst->pcState());
376  } else if (fault == NoFault && unverifiedFault != NoFault) {
377  panic("%lli: sn: %lli at PC: %s took a fault in driver "
378  "CPU but not in checker\n", curTick(),
379  unverifiedInst->seqNum, unverifiedInst->pcState());
380  }
381  }
382 
383  // Take any faults here
384  if (fault != NoFault) {
385  if (FullSystem) {
386  fault->invoke(tc, curStaticInst);
387  willChangePC = true;
388  set(newPCState, thread->pcState());
389  DPRINTF(Checker, "Fault, PC is now %s\n", *newPCState);
390  curMacroStaticInst = nullStaticInstPtr;
391  }
392  } else {
393  advancePC(fault);
394  }
395 
396  if (FullSystem) {
397  // @todo: Determine if these should happen only if the
398  // instruction hasn't faulted. In the SimpleCPU case this may
399  // not be true, but in the O3 case this may be true.
400  Addr oldpc;
401  int count = 0;
402  do {
403  oldpc = thread->pcState().instAddr();
404  thread->pcEventQueue.service(oldpc, tc);
405  count++;
406  } while (oldpc != thread->pcState().instAddr());
407  if (count > 1) {
408  willChangePC = true;
409  set(newPCState, thread->pcState());
410  DPRINTF(Checker, "PC Event, PC is now %s\n", *newPCState);
411  }
412  }
413 
414  // @todo: Optionally can check all registers. (Or just those
415  // that have been modified).
416  validateState();
417 
418  // Continue verifying instructions if there's another completed
419  // instruction waiting to be verified.
420  if (instList.empty()) {
421  break;
422  } else if (instList.front()->isCompleted()) {
423  unverifiedInst = NULL;
424  unverifiedInst = instList.front();
425  instList.pop_front();
426  } else {
427  break;
428  }
429  }
430  unverifiedInst = NULL;
431 }
432 
433 template <class DynInstPtr>
434 void
436 {
437  instList.clear();
438 }
439 
440 template <class DynInstPtr>
441 void Checker<DynInstPtr>::takeOverFrom(BaseCPU *oldCPU) {}
442 
443 template <class DynInstPtr>
444 void
446 {
447  if (inst->pcState().instAddr() != thread->pcState().instAddr()) {
448  warn("%lli: PCs do not match! Inst: %s, checker: %s",
449  curTick(), inst->pcState(), thread->pcState());
450  if (changedPC) {
451  warn("%lli: Changed PCs recently, may not be an error",
452  curTick());
453  } else {
454  handleError(inst);
455  }
456  }
457 
458  if (curStaticInst != inst->staticInst) {
459  warn("%lli: StaticInstPtrs don't match. (%s, %s).\n", curTick(),
460  curStaticInst->getName(), inst->staticInst->getName());
461  }
462 }
463 
464 template <class DynInstPtr>
465 void
467 {
468  InstResult checker_val;
469  InstResult inst_val;
470  int idx = -1;
471  bool result_mismatch = false;
472  bool scalar_mismatch = false;
473 
474  if (inst->isUnverifiable()) {
475  // Unverifiable instructions assume they were executed
476  // properly by the CPU. Grab the result from the
477  // instruction and write it to the register.
478  copyResult(inst, InstResult((RegVal)0), idx);
479  } else if (inst->numDestRegs() > 0 && !result.empty()) {
480  DPRINTF(Checker, "Dest regs %d, number of checker dest regs %d\n",
481  inst->numDestRegs(), result.size());
482  for (int i = 0; i < inst->numDestRegs() && !result.empty(); i++) {
483  checker_val = result.front();
484  result.pop();
485  inst_val = inst->popResult(InstResult((RegVal)0));
486  if (checker_val != inst_val) {
487  result_mismatch = true;
488  idx = i;
489  scalar_mismatch = checker_val.is<RegVal>();
490  }
491  }
492  } // Checker CPU checks all the saved results in the dyninst passed by
493  // the cpu model being checked against the saved results present in
494  // the static inst executed in the Checker. Sometimes the number
495  // of saved results differs between the dyninst and static inst, but
496  // this is ok and not a bug. May be worthwhile to try and correct this.
497 
498  if (result_mismatch) {
499  if (scalar_mismatch) {
500  warn("%lli: Instruction results (%i) do not match! (Values may"
501  " not actually be integers) Inst: %#x, checker: %#x",
502  curTick(), idx, inst_val.asNoAssert<RegVal>(),
503  checker_val.as<RegVal>());
504  }
505 
506  // It's useful to verify load values from memory, but in MP
507  // systems the value obtained at execute may be different than
508  // the value obtained at completion. Similarly DMA can
509  // present the same problem on even UP systems. Thus there is
510  // the option to only warn on loads having a result error.
511  // The load/store queue in Detailed CPU can also cause problems
512  // if load/store forwarding is allowed.
513  if (inst->isLoad() && warnOnlyOnLoadError) {
514  copyResult(inst, inst_val, idx);
515  } else {
516  handleError(inst);
517  }
518  }
519 
520  if (inst->pcState() != thread->pcState()) {
521  warn("%lli: Instruction PCs do not match! Inst: %s, checker: %s",
522  curTick(), inst->pcState(), thread->pcState());
523  handleError(inst);
524  }
525 
526  // Checking side effect registers can be difficult if they are not
527  // checked simultaneously with the execution of the instruction.
528  // This is because other valid instructions may have modified
529  // these registers in the meantime, and their values are not
530  // stored within the DynInst.
531  while (!miscRegIdxs.empty()) {
532  int misc_reg_idx = miscRegIdxs.front();
533  miscRegIdxs.pop();
534 
535  if (inst->tcBase()->readMiscRegNoEffect(misc_reg_idx) !=
536  thread->readMiscRegNoEffect(misc_reg_idx)) {
537  warn("%lli: Misc reg idx %i (side effect) does not match! "
538  "Inst: %#x, checker: %#x",
539  curTick(), misc_reg_idx,
540  inst->tcBase()->readMiscRegNoEffect(misc_reg_idx),
541  thread->readMiscRegNoEffect(misc_reg_idx));
542  handleError(inst);
543  }
544  }
545 }
546 
547 
548 // This function is weird, if it is called it means the Checker and
549 // O3 have diverged, so panic is called for now. It may be useful
550 // to resynch states and continue if the divergence is a false positive
551 template <class DynInstPtr>
552 void
554 {
555  if (updateThisCycle) {
556  // Change this back to warn if divergences end up being false positives
557  panic("%lli: Instruction PC %#x results didn't match up, copying all "
558  "registers from main CPU", curTick(),
559  unverifiedInst->pcState().instAddr());
560 
561  // Terribly convoluted way to make sure O3 model does not implode
562  bool no_squash_from_TC = unverifiedInst->thread->noSquashFromTC;
563  unverifiedInst->thread->noSquashFromTC = true;
564 
565  // Heavy-weight copying of all registers
566  thread->copyArchRegs(unverifiedInst->tcBase());
567  unverifiedInst->thread->noSquashFromTC = no_squash_from_TC;
568 
569  // Set curStaticInst to unverifiedInst->staticInst
570  curStaticInst = unverifiedInst->staticInst;
571  // Also advance the PC. Hopefully no PC-based events happened.
572  advancePC(NoFault);
573  updateThisCycle = false;
574  }
575 }
576 
577 template <class DynInstPtr>
578 void
580  const DynInstPtr &inst, const InstResult& mismatch_val, int start_idx)
581 {
582  // We've already popped one dest off the queue,
583  // so do the fix-up then start with the next dest reg;
584  if (start_idx >= 0) {
585  const RegId& idx = inst->destRegIdx(start_idx);
586  switch (idx.classValue()) {
587  case IntRegClass:
588  thread->setIntReg(idx.index(), mismatch_val.as<RegVal>());
589  break;
590  case FloatRegClass:
591  thread->setFloatReg(idx.index(), mismatch_val.as<RegVal>());
592  break;
593  case VecRegClass:
594  thread->setVecReg(idx, mismatch_val.as<TheISA::VecRegContainer>());
595  break;
596  case VecElemClass:
597  thread->setVecElem(idx, mismatch_val.as<RegVal>());
598  break;
599  case CCRegClass:
600  thread->setCCReg(idx.index(), mismatch_val.as<RegVal>());
601  break;
602  case MiscRegClass:
603  thread->setMiscReg(idx.index(), mismatch_val.as<RegVal>());
604  break;
605  default:
606  panic("Unknown register class: %d", (int)idx.classValue());
607  }
608  }
609  start_idx++;
610  InstResult res;
611  for (int i = start_idx; i < inst->numDestRegs(); i++) {
612  const RegId& idx = inst->destRegIdx(i);
613  res = inst->popResult();
614  switch (idx.classValue()) {
615  case IntRegClass:
616  thread->setIntReg(idx.index(), res.as<RegVal>());
617  break;
618  case FloatRegClass:
619  thread->setFloatReg(idx.index(), res.as<RegVal>());
620  break;
621  case VecRegClass:
622  thread->setVecReg(idx, res.as<TheISA::VecRegContainer>());
623  break;
624  case VecElemClass:
625  thread->setVecElem(idx, res.as<RegVal>());
626  break;
627  case CCRegClass:
628  thread->setCCReg(idx.index(), res.as<RegVal>());
629  break;
630  case MiscRegClass:
631  // Try to get the proper misc register index for ARM here...
632  thread->setMiscReg(idx.index(), 0);
633  break;
634  // else Register is out of range...
635  default:
636  panic("Unknown register class: %d", (int)idx.classValue());
637  }
638  }
639 }
640 
641 template <class DynInstPtr>
642 void
644 {
645  cprintf("Error detected, instruction information:\n");
646  cprintf("PC:%s\n[sn:%lli]\n[tid:%i]\n"
647  "Completed:%i\n",
648  inst->pcState(),
649  inst->seqNum,
650  inst->threadNumber,
651  inst->isCompleted());
652  inst->dump();
654 }
655 
656 template <class DynInstPtr>
657 void
659 {
660  int num = 0;
661 
662  InstListIt inst_list_it = --(instList.end());
663 
664  cprintf("Inst list size: %i\n", instList.size());
665 
666  while (inst_list_it != instList.end())
667  {
668  cprintf("Instruction:%i\n",
669  num);
670 
671  cprintf("PC:%s\n[sn:%lli]\n[tid:%i]\n"
672  "Completed:%i\n",
673  (*inst_list_it)->pcState(),
674  (*inst_list_it)->seqNum,
675  (*inst_list_it)->threadNumber,
676  (*inst_list_it)->isCompleted());
677 
678  cprintf("\n");
679 
680  inst_list_it--;
681  ++num;
682  }
683 
684 }
685 
686 } // namespace gem5
687 
688 #endif//__CPU_CHECKER_CPU_IMPL_HH__
gem5::CheckerCPU::pcState
const PCStateBase & pcState() const override
Definition: cpu.hh:358
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
refcnt.hh
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::Checker::validateInst
void validateInst(const DynInstPtr &inst)
Definition: cpu_impl.hh:445
warn
#define warn(...)
Definition: logging.hh:246
gem5::Checker::verify
void verify(const DynInstPtr &inst)
Definition: cpu_impl.hh:120
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::cprintf
void cprintf(const char *format, const Args &...args)
Definition: cprintf.hh:155
gem5::Request::INST_FETCH
@ INST_FETCH
The request was an instruction fetch.
Definition: request.hh:115
gem5::VecElemClass
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:63
gem5::Checker::advancePC
void advancePC(const Fault &fault)
Definition: cpu_impl.hh:67
gem5::isRomMicroPC
static bool isRomMicroPC(MicroPC upc)
Definition: types.hh:166
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:65
gem5::o3::DynInstPtr
RefCountingPtr< DynInst > DynInstPtr
Definition: dyn_inst_ptr.hh:55
exetrace.hh
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::Checker::copyResult
void copyResult(const DynInstPtr &inst, const InstResult &mismatch_val, int start_idx)
Definition: cpu_impl.hh:579
gem5::RegId::index
RegIndex index() const
Index accessors.
Definition: reg_class.hh:180
gem5::StaticInst::advancePC
virtual void advancePC(PCStateBase &pc_state) const =0
gem5::Checker::handlePendingInt
void handlePendingInt()
Definition: cpu_impl.hh:86
gem5::BaseMMU::Execute
@ Execute
Definition: mmu.hh:56
gem5::RefCountingPtr< StaticInst >
gem5::StaticInst::fetchMicroop
virtual StaticInstPtr fetchMicroop(MicroPC upc) const
Return the microop that goes with a particular micropc.
Definition: static_inst.cc:39
gem5::InstResult::is
bool is() const
Checks.
Definition: inst_res.hh:136
gem5::CheckerCPU::dumpAndExit
void dumpAndExit()
Definition: cpu.cc:374
gem5::Packet::dataStatic
void dataStatic(T *p)
Set the data pointer to the following value that should not be freed.
Definition: packet.hh:1134
stats.hh
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:59
gem5::InstResult::as
T as() const
Explicit cast-like operations.
Definition: inst_res.hh:158
gem5::nullStaticInstPtr
const StaticInstPtr nullStaticInstPtr
Statically allocated null StaticInstPtr.
Definition: null_static_inst.cc:36
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
sim_object.hh
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::X86ISA::count
count
Definition: misc.hh:709
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::probing::Packet
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:109
cpu.hh
gem5::MemCmd::ReadReq
@ ReadReq
Definition: packet.hh:86
gem5::ArmISA::VecRegContainer
gem5::VecRegContainer< NumVecElemPerVecReg *sizeof(VecElem)> VecRegContainer
Definition: vec.hh:62
static_inst.hh
gem5::Checker::validateExecution
void validateExecution(const DynInstPtr &inst)
Definition: cpu_impl.hh:466
gem5::RegId::classValue
RegClassType classValue() const
Class accessor.
Definition: reg_class.hh:206
null_static_inst.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
full_system.hh
gem5::Trace::InstRecord::dump
virtual void dump()=0
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:220
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:58
gem5::CheckerCPU::handleError
void handleError()
Definition: cpu.hh:496
simple_thread.hh
gem5::Checker::takeOverFrom
void takeOverFrom(BaseCPU *oldCPU)
Definition: cpu_impl.hh:441
gem5::MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:66
gem5::Checker< gem5::RefCountingPtr >::InstListIt
std::list< gem5::RefCountingPtr >::iterator InstListIt
Definition: cpu.hh:571
gem5::StaticInst::isMacroop
bool isMacroop() const
Definition: static_inst.hh:206
reg_class.hh
gem5::Checker::switchOut
void switchOut()
Definition: cpu_impl.hh:435
gem5::Checker::validateState
void validateState()
Definition: cpu_impl.hh:553
gem5::InstResult::asNoAssert
T asNoAssert() const
Cast to integer without checking type.
Definition: inst_res.hh:178
decoder
output decoder
Definition: nop.cc:61
gem5::Trace::InstRecord
Definition: insttracer.hh:61
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:61
std::list
STL list class.
Definition: stl.hh:51
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::Checker
Templated Checker class.
Definition: cpu.hh:531
thread_context.hh
gem5::Checker::dumpInsts
void dumpInsts()
Definition: cpu_impl.hh:658
gem5::InstResult
Definition: inst_res.hh:50
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:113
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178

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