gem5  v21.1.0.2
process.cc
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40 
41 #include "arch/arm/process.hh"
42 
43 #include "arch/arm/page_size.hh"
44 #include "arch/arm/regs/cc.hh"
45 #include "arch/arm/regs/misc.hh"
46 #include "arch/arm/types.hh"
49 #include "base/logging.hh"
50 #include "cpu/thread_context.hh"
51 #include "debug/Stack.hh"
52 #include "mem/page_table.hh"
53 #include "params/Process.hh"
54 #include "sim/aux_vector.hh"
55 #include "sim/byteswap.hh"
56 #include "sim/process_impl.hh"
57 #include "sim/syscall_return.hh"
58 #include "sim/system.hh"
59 
60 namespace gem5
61 {
62 
63 using namespace ArmISA;
64 
65 ArmProcess::ArmProcess(const ProcessParams &params,
66  loader::ObjectFile *objFile, loader::Arch _arch)
67  : Process(params,
68  new EmulationPageTable(params.name, params.pid, PageBytes),
69  objFile),
70  arch(_arch)
71 {
72  fatal_if(params.useArchPT, "Arch page tables not implemented.");
73 }
74 
75 ArmProcess32::ArmProcess32(const ProcessParams &params,
76  loader::ObjectFile *objFile, loader::Arch _arch)
77  : ArmProcess(params, objFile, _arch)
78 {
79  Addr brk_point = roundUp(image.maxAddr(), PageBytes);
80  Addr stack_base = 0xbf000000L;
81  Addr max_stack_size = 8 * 1024 * 1024;
82  Addr next_thread_stack_base = stack_base - max_stack_size;
83  Addr mmap_end = 0x40000000L;
84 
85  memState = std::make_shared<MemState>(
86  this, brk_point, stack_base, max_stack_size,
87  next_thread_stack_base, mmap_end);
88 }
89 
91  const ProcessParams &params, loader::ObjectFile *objFile,
92  loader::Arch _arch)
93  : ArmProcess(params, objFile, _arch)
94 {
95  Addr brk_point = roundUp(image.maxAddr(), PageBytes);
96  Addr stack_base = 0x7fffff0000L;
97  Addr max_stack_size = 8 * 1024 * 1024;
98  Addr next_thread_stack_base = stack_base - max_stack_size;
99  Addr mmap_end = 0x4000000000L;
100 
101  memState = std::make_shared<MemState>(
102  this, brk_point, stack_base, max_stack_size,
103  next_thread_stack_base, mmap_end);
104 }
105 
106 void
108 {
110  argsInit<uint32_t>(PageBytes, INTREG_SP);
111  for (auto id: contextIds) {
112  ThreadContext *tc = system->threads[id];
113  CPACR cpacr = tc->readMiscReg(MISCREG_CPACR);
114  // Enable the floating point coprocessors.
115  cpacr.cp10 = 0x3;
116  cpacr.cp11 = 0x3;
117  tc->setMiscReg(MISCREG_CPACR, cpacr);
118  // Generically enable floating point support.
119  FPEXC fpexc = tc->readMiscReg(MISCREG_FPEXC);
120  fpexc.en = 1;
121  tc->setMiscReg(MISCREG_FPEXC, fpexc);
122  }
123 }
124 
125 void
127 {
129  argsInit<uint64_t>(PageBytes, INTREG_SP0);
130  for (auto id: contextIds) {
131  ThreadContext *tc = system->threads[id];
132  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
133  cpsr.mode = MODE_EL0T;
134  tc->setMiscReg(MISCREG_CPSR, cpsr);
135  CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
136  // Enable the floating point coprocessors.
137  cpacr.cp10 = 0x3;
138  cpacr.cp11 = 0x3;
139  // Enable SVE.
140  cpacr.zen = 0x3;
141  tc->setMiscReg(MISCREG_CPACR_EL1, cpacr);
142  // Generically enable floating point support.
143  FPEXC fpexc = tc->readMiscReg(MISCREG_FPEXC);
144  fpexc.en = 1;
145  tc->setMiscReg(MISCREG_FPEXC, fpexc);
146  }
147 }
148 
149 uint32_t
151 {
152  enum ArmCpuFeature
153  {
154  Arm_Swp = 1 << 0,
155  Arm_Half = 1 << 1,
156  Arm_Thumb = 1 << 2,
157  Arm_26Bit = 1 << 3,
158  Arm_FastMult = 1 << 4,
159  Arm_Fpa = 1 << 5,
160  Arm_Vfp = 1 << 6,
161  Arm_Edsp = 1 << 7,
162  Arm_Java = 1 << 8,
163  Arm_Iwmmxt = 1 << 9,
164  Arm_Crunch = 1 << 10,
165  Arm_ThumbEE = 1 << 11,
166  Arm_Neon = 1 << 12,
167  Arm_Vfpv3 = 1 << 13,
168  Arm_Vfpv3d16 = 1 << 14
169  };
170 
171  return Arm_Swp | Arm_Half | Arm_Thumb | Arm_FastMult |
172  Arm_Vfp | Arm_Edsp | Arm_ThumbEE | Arm_Neon |
173  Arm_Vfpv3 | Arm_Vfpv3d16;
174 }
175 
176 uint32_t
178 {
179  // In order to know what these flags mean, please refer to Linux
180  // /Documentation/arm64/elf_hwcaps.txt text file.
181  enum ArmCpuFeature
182  {
183  Arm_Fp = 1 << 0,
184  Arm_Asimd = 1 << 1,
185  Arm_Evtstrm = 1 << 2,
186  Arm_Aes = 1 << 3,
187  Arm_Pmull = 1 << 4,
188  Arm_Sha1 = 1 << 5,
189  Arm_Sha2 = 1 << 6,
190  Arm_Crc32 = 1 << 7,
191  Arm_Atomics = 1 << 8,
192  Arm_Fphp = 1 << 9,
193  Arm_Asimdhp = 1 << 10,
194  Arm_Cpuid = 1 << 11,
195  Arm_Asimdrdm = 1 << 12,
196  Arm_Jscvt = 1 << 13,
197  Arm_Fcma = 1 << 14,
198  Arm_Lrcpc = 1 << 15,
199  Arm_Dcpop = 1 << 16,
200  Arm_Sha3 = 1 << 17,
201  Arm_Sm3 = 1 << 18,
202  Arm_Sm4 = 1 << 19,
203  Arm_Asimddp = 1 << 20,
204  Arm_Sha512 = 1 << 21,
205  Arm_Sve = 1 << 22,
206  Arm_Asimdfhm = 1 << 23,
207  Arm_Dit = 1 << 24,
208  Arm_Uscat = 1 << 25,
209  Arm_Ilrcpc = 1 << 26,
210  Arm_Flagm = 1 << 27
211  };
212 
213  uint32_t hwcap = 0;
214 
216 
217  const AA64PFR0 pf_r0 = tc->readMiscReg(MISCREG_ID_AA64PFR0_EL1);
218 
219  hwcap |= (pf_r0.fp == 0) ? Arm_Fp : 0;
220  hwcap |= (pf_r0.fp == 1) ? Arm_Fphp | Arm_Fp : 0;
221  hwcap |= (pf_r0.advsimd == 0) ? Arm_Asimd : 0;
222  hwcap |= (pf_r0.advsimd == 1) ? Arm_Asimdhp | Arm_Asimd : 0;
223  hwcap |= (pf_r0.sve >= 1) ? Arm_Sve : 0;
224  hwcap |= (pf_r0.dit >= 1) ? Arm_Dit : 0;
225 
226  const AA64ISAR0 isa_r0 = tc->readMiscReg(MISCREG_ID_AA64ISAR0_EL1);
227 
228  hwcap |= (isa_r0.aes >= 1) ? Arm_Aes : 0;
229  hwcap |= (isa_r0.aes >= 2) ? Arm_Pmull : 0;
230  hwcap |= (isa_r0.sha1 >= 1) ? Arm_Sha1 : 0;
231  hwcap |= (isa_r0.sha2 >= 1) ? Arm_Sha2 : 0;
232  hwcap |= (isa_r0.sha2 >= 2) ? Arm_Sha512 : 0;
233  hwcap |= (isa_r0.crc32 >= 1) ? Arm_Crc32 : 0;
234  hwcap |= (isa_r0.atomic >= 1) ? Arm_Atomics : 0;
235  hwcap |= (isa_r0.rdm >= 1) ? Arm_Asimdrdm : 0;
236  hwcap |= (isa_r0.sha3 >= 1) ? Arm_Sha3 : 0;
237  hwcap |= (isa_r0.sm3 >= 1) ? Arm_Sm3 : 0;
238  hwcap |= (isa_r0.sm4 >= 1) ? Arm_Sm4 : 0;
239  hwcap |= (isa_r0.dp >= 1) ? Arm_Asimddp : 0;
240  hwcap |= (isa_r0.fhm >= 1) ? Arm_Asimdfhm : 0;
241  hwcap |= (isa_r0.ts >= 1) ? Arm_Flagm : 0;
242 
243  const AA64ISAR1 isa_r1 = tc->readMiscReg(MISCREG_ID_AA64ISAR1_EL1);
244 
245  hwcap |= (isa_r1.dpb >= 1) ? Arm_Dcpop : 0;
246  hwcap |= (isa_r1.jscvt >= 1) ? Arm_Jscvt : 0;
247  hwcap |= (isa_r1.fcma >= 1) ? Arm_Fcma : 0;
248  hwcap |= (isa_r1.lrcpc >= 1) ? Arm_Lrcpc : 0;
249  hwcap |= (isa_r1.lrcpc >= 2) ? Arm_Ilrcpc : 0;
250 
251  const AA64MMFR2 mm_fr2 = tc->readMiscReg(MISCREG_ID_AA64MMFR2_EL1);
252 
253  hwcap |= (mm_fr2.at >= 1) ? Arm_Uscat : 0;
254 
255  return hwcap;
256 }
257 
258 template <class IntType>
259 void
260 ArmProcess::argsInit(int pageSize, IntRegIndex spIndex)
261 {
262  int intSize = sizeof(IntType);
263 
265 
266  std::string filename;
267  if (argv.size() < 1)
268  filename = "";
269  else
270  filename = argv[0];
271 
272  //We want 16 byte alignment
273  uint64_t align = 16;
274 
275  //Setup the auxilliary vectors. These will already have endian conversion.
276  //Auxilliary vectors are loaded only for elf formatted executables.
277  auto *elfObject = dynamic_cast<loader::ElfObject *>(objFile);
278  if (elfObject) {
279 
280  if (objFile->getOpSys() == loader::Linux) {
281  IntType features = armHwcap<IntType>();
282 
283  //Bits which describe the system hardware capabilities
284  //XXX Figure out what these should be
285  auxv.emplace_back(gem5::auxv::Hwcap, features);
286  //Frequency at which times() increments
287  auxv.emplace_back(gem5::auxv::Clktck, 0x64);
288  //Whether to enable "secure mode" in the executable
289  auxv.emplace_back(gem5::auxv::Secure, 0);
290  // Pointer to 16 bytes of random data
291  auxv.emplace_back(gem5::auxv::Random, 0);
292  //The filename of the program
293  auxv.emplace_back(gem5::auxv::Execfn, 0);
294  //The string "v71" -- ARM v7 architecture
295  auxv.emplace_back(gem5::auxv::Platform, 0);
296  }
297 
298  //The system page size
299  auxv.emplace_back(gem5::auxv::Pagesz, ArmISA::PageBytes);
300  // For statically linked executables, this is the virtual address of
301  // the program header tables if they appear in the executable image
302  auxv.emplace_back(gem5::auxv::Phdr, elfObject->programHeaderTable());
303  // This is the size of a program header entry from the elf file.
304  auxv.emplace_back(gem5::auxv::Phent, elfObject->programHeaderSize());
305  // This is the number of program headers from the original elf file.
306  auxv.emplace_back(gem5::auxv::Phnum, elfObject->programHeaderCount());
307  // This is the base address of the ELF interpreter; it should be
308  // zero for static executables or contain the base address for
309  // dynamic executables.
310  auxv.emplace_back(gem5::auxv::Base, getBias());
311  //XXX Figure out what this should be.
312  auxv.emplace_back(gem5::auxv::Flags, 0);
313  //The entry point to the program
314  auxv.emplace_back(gem5::auxv::Entry, objFile->entryPoint());
315  //Different user and group IDs
316  auxv.emplace_back(gem5::auxv::Uid, uid());
317  auxv.emplace_back(gem5::auxv::Euid, euid());
318  auxv.emplace_back(gem5::auxv::Gid, gid());
319  auxv.emplace_back(gem5::auxv::Egid, egid());
320  }
321 
322  //Figure out how big the initial stack nedes to be
323 
324  // A sentry NULL void pointer at the top of the stack.
325  int sentry_size = intSize;
326 
327  std::string platform = "v71";
328  int platform_size = platform.size() + 1;
329 
330  // Bytes for AT_RANDOM above, we'll just keep them 0
331  int aux_random_size = 16; // as per the specification
332 
333  // The aux vectors are put on the stack in two groups. The first group are
334  // the vectors that are generated as the elf is loaded. The second group
335  // are the ones that were computed ahead of time and include the platform
336  // string.
337  int aux_data_size = filename.size() + 1;
338 
339  int env_data_size = 0;
340  for (int i = 0; i < envp.size(); ++i) {
341  env_data_size += envp[i].size() + 1;
342  }
343  int arg_data_size = 0;
344  for (int i = 0; i < argv.size(); ++i) {
345  arg_data_size += argv[i].size() + 1;
346  }
347 
348  int info_block_size =
349  sentry_size + env_data_size + arg_data_size +
350  aux_data_size + platform_size + aux_random_size;
351 
352  //Each auxilliary vector is two 4 byte words
353  int aux_array_size = intSize * 2 * (auxv.size() + 1);
354 
355  int envp_array_size = intSize * (envp.size() + 1);
356  int argv_array_size = intSize * (argv.size() + 1);
357 
358  int argc_size = intSize;
359 
360  //Figure out the size of the contents of the actual initial frame
361  int frame_size =
362  info_block_size +
363  aux_array_size +
364  envp_array_size +
365  argv_array_size +
366  argc_size;
367 
368  //There needs to be padding after the auxiliary vector data so that the
369  //very bottom of the stack is aligned properly.
370  int partial_size = frame_size;
371  int aligned_partial_size = roundUp(partial_size, align);
372  int aux_padding = aligned_partial_size - partial_size;
373 
374  int space_needed = frame_size + aux_padding;
375 
376  memState->setStackMin(memState->getStackBase() - space_needed);
377  memState->setStackMin(roundDown(memState->getStackMin(), align));
378  memState->setStackSize(memState->getStackBase() - memState->getStackMin());
379 
380  // map memory
381  memState->mapRegion(roundDown(memState->getStackMin(), pageSize),
382  roundUp(memState->getStackSize(), pageSize), "stack");
383 
384  // map out initial stack contents
385  IntType sentry_base = memState->getStackBase() - sentry_size;
386  IntType aux_data_base = sentry_base - aux_data_size;
387  IntType env_data_base = aux_data_base - env_data_size;
388  IntType arg_data_base = env_data_base - arg_data_size;
389  IntType platform_base = arg_data_base - platform_size;
390  IntType aux_random_base = platform_base - aux_random_size;
391  IntType auxv_array_base = aux_random_base - aux_array_size - aux_padding;
392  IntType envp_array_base = auxv_array_base - envp_array_size;
393  IntType argv_array_base = envp_array_base - argv_array_size;
394  IntType argc_base = argv_array_base - argc_size;
395 
396  DPRINTF(Stack, "The addresses of items on the initial stack:\n");
397  DPRINTF(Stack, "0x%x - aux data\n", aux_data_base);
398  DPRINTF(Stack, "0x%x - env data\n", env_data_base);
399  DPRINTF(Stack, "0x%x - arg data\n", arg_data_base);
400  DPRINTF(Stack, "0x%x - random data\n", aux_random_base);
401  DPRINTF(Stack, "0x%x - platform base\n", platform_base);
402  DPRINTF(Stack, "0x%x - auxv array\n", auxv_array_base);
403  DPRINTF(Stack, "0x%x - envp array\n", envp_array_base);
404  DPRINTF(Stack, "0x%x - argv array\n", argv_array_base);
405  DPRINTF(Stack, "0x%x - argc \n", argc_base);
406  DPRINTF(Stack, "0x%x - stack min\n", memState->getStackMin());
407 
408  // write contents to stack
409 
410  // figure out argc
411  IntType argc = argv.size();
412  IntType guestArgc = htole(argc);
413 
414  //Write out the sentry void *
415  IntType sentry_NULL = 0;
416  initVirtMem->writeBlob(sentry_base, &sentry_NULL, sentry_size);
417 
418  //Fix up the aux vectors which point to other data
419  for (int i = auxv.size() - 1; i >= 0; i--) {
420  if (auxv[i].type == gem5::auxv::Platform) {
421  auxv[i].val = platform_base;
422  initVirtMem->writeString(platform_base, platform.c_str());
423  } else if (auxv[i].type == gem5::auxv::Execfn) {
424  auxv[i].val = aux_data_base;
425  initVirtMem->writeString(aux_data_base, filename.c_str());
426  } else if (auxv[i].type == gem5::auxv::Random) {
427  auxv[i].val = aux_random_base;
428  // Just leave the value 0, we don't want randomness
429  }
430  }
431 
432  //Copy the aux stuff
433  Addr auxv_array_end = auxv_array_base;
434  for (const auto &aux: auxv) {
435  initVirtMem->write(auxv_array_end, aux, ByteOrder::little);
436  auxv_array_end += sizeof(aux);
437  }
438  //Write out the terminating zeroed auxillary vector
439  const gem5::auxv::AuxVector<IntType> zero(0, 0);
440  initVirtMem->write(auxv_array_end, zero);
441  auxv_array_end += sizeof(zero);
442 
443  copyStringArray(envp, envp_array_base, env_data_base,
444  ByteOrder::little, *initVirtMem);
445  copyStringArray(argv, argv_array_base, arg_data_base,
446  ByteOrder::little, *initVirtMem);
447 
448  initVirtMem->writeBlob(argc_base, &guestArgc, intSize);
449 
451  //Set the stack pointer register
452  tc->setIntReg(spIndex, memState->getStackMin());
453  //A pointer to a function to run when the program exits. We'll set this
454  //to zero explicitly to make sure this isn't used.
455  tc->setIntReg(ArgumentReg0, 0);
456  //Set argument regs 1 and 2 to argv[0] and envp[0] respectively
457  if (argv.size() > 0) {
458  tc->setIntReg(ArgumentReg1, arg_data_base + arg_data_size -
459  argv[argv.size() - 1].size() - 1);
460  } else {
461  tc->setIntReg(ArgumentReg1, 0);
462  }
463  if (envp.size() > 0) {
464  tc->setIntReg(ArgumentReg2, env_data_base + env_data_size -
465  envp[envp.size() - 1].size() - 1);
466  } else {
467  tc->setIntReg(ArgumentReg2, 0);
468  }
469 
470  PCState pc;
471  pc.thumb(arch == loader::Thumb);
472  pc.nextThumb(pc.thumb());
473  pc.aarch64(arch == loader::Arm64);
474  pc.nextAArch64(pc.aarch64());
475  pc.set(getStartPC() & ~mask(1));
476  tc->pcState(pc);
477 
478  //Align the "stackMin" to a page boundary.
479  memState->setStackMin(roundDown(memState->getStackMin(), pageSize));
480 }
481 
482 } // namespace gem5
gem5::ThreadContext::setIntReg
virtual void setIntReg(RegIndex reg_idx, RegVal val)=0
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
gem5::loader::MemoryImage::maxAddr
Addr maxAddr() const
Definition: memory_image.hh:136
gem5::auxv::Platform
@ Platform
Definition: aux_vector.hh:84
gem5::Process::euid
uint64_t euid()
Definition: process.hh:83
gem5::ArmProcess::ArmProcess
ArmProcess(const ProcessParams &params, loader::ObjectFile *objFile, loader::Arch _arch)
Definition: process.cc:65
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::EmulationPageTable
Definition: page_table.hh:52
gem5::loader::ObjectFile
Definition: object_file.hh:85
gem5::auxv::Gid
@ Gid
Definition: aux_vector.hh:82
system.hh
gem5::X86ISA::L
Bitfield< 7, 0 > L
Definition: int.hh:59
gem5::Process::getStartPC
Addr getStartPC()
Definition: process.cc:490
gem5::Process::initVirtMem
std::unique_ptr< SETranslatingPortProxy > initVirtMem
Definition: process.hh:174
gem5::loader::ObjectFile::entryPoint
Addr entryPoint() const
Definition: object_file.hh:125
gem5::auxv::Random
@ Random
Definition: aux_vector.hh:89
gem5::ArmISA::ArgumentReg0
const int ArgumentReg0
Definition: int.hh:540
gem5::Process::getBias
Addr getBias()
Definition: process.cc:482
gem5::auxv::Hwcap
@ Hwcap
Definition: aux_vector.hh:85
gem5::loader::ElfObject
Definition: elf_object.hh:64
gem5::Process::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: process.cc:287
process_impl.hh
gem5::Process::egid
uint64_t egid()
Definition: process.hh:85
std::vector
STL vector class.
Definition: stl.hh:37
gem5::ArmProcess64::armHwcapImpl
uint32_t armHwcapImpl() const override
AArch64 AT_HWCAP.
Definition: process.cc:177
gem5::auxv::Phent
@ Phent
Definition: aux_vector.hh:73
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
types.hh
gem5::Process::gid
uint64_t gid()
Definition: process.hh:84
gem5::PowerISA::PCState
Definition: pcstate.hh:42
cc.hh
gem5::ArmISA::ArgumentReg2
const int ArgumentReg2
Definition: int.hh:542
gem5::Process::memState
std::shared_ptr< MemState > memState
Definition: process.hh:276
sc_dt::align
void align(const scfx_rep &lhs, const scfx_rep &rhs, int &new_wp, int &len_mant, scfx_mant_ref &lhs_mant, scfx_mant_ref &rhs_mant)
Definition: scfx_rep.cc:2083
gem5::loader::Arm64
@ Arm64
Definition: object_file.hh:58
gem5::mask
constexpr uint64_t mask(unsigned nbits)
Generate a 64-bit mask of 'nbits' 1s, right justified.
Definition: bitfield.hh:63
gem5::Process::uid
uint64_t uid()
Definition: process.hh:82
gem5::auxv::Base
@ Base
Definition: aux_vector.hh:76
gem5::auxv::Pagesz
@ Pagesz
Definition: aux_vector.hh:75
elf_object.hh
syscall_return.hh
gem5::auxv::Secure
@ Secure
Definition: aux_vector.hh:87
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::ArmISA::MISCREG_ID_AA64MMFR2_EL1
@ MISCREG_ID_AA64MMFR2_EL1
Definition: misc.hh:822
gem5::ArmProcess32::armHwcapImpl
uint32_t armHwcapImpl() const override
AArch32 AT_HWCAP.
Definition: process.cc:150
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
gem5::auxv::Clktck
@ Clktck
Definition: aux_vector.hh:86
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::ArmISA::MISCREG_FPEXC
@ MISCREG_FPEXC
Definition: misc.hh:75
gem5::ArmProcess
Definition: process.hh:56
gem5::ArmProcess::argsInit
void argsInit(int pageSize, ArmISA::IntRegIndex spIndex)
gem5::copyStringArray
void copyStringArray(std::vector< std::string > &strings, AddrType array_ptr, AddrType data_ptr, const ByteOrder bo, PortProxy &memProxy)
Definition: process_impl.hh:43
gem5::X86ISA::type
type
Definition: misc.hh:733
gem5::auxv::AuxVector
Definition: aux_vector.hh:45
gem5::auxv::Phdr
@ Phdr
Definition: aux_vector.hh:72
gem5::ArmProcess64::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: process.cc:126
gem5::ArmISA::MISCREG_CPACR_EL1
@ MISCREG_CPACR_EL1
Definition: misc.hh:582
gem5::Process::argv
std::vector< std::string > argv
Definition: process.hh:213
gem5::ArmProcess::arch
loader::Arch arch
Definition: process.hh:59
gem5::loader::Arch
Arch
Definition: object_file.hh:50
gem5::roundDown
static constexpr T roundDown(const T &val, const U &align)
This function is used to align addresses in memory.
Definition: intmath.hh:279
gem5::ThreadContext::pcState
virtual TheISA::PCState pcState() const =0
gem5::loader::ObjectFile::getOpSys
OpSys getOpSys() const
Definition: object_file.hh:116
gem5::auxv::Egid
@ Egid
Definition: aux_vector.hh:83
gem5::auxv::Entry
@ Entry
Definition: aux_vector.hh:78
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::Process::envp
std::vector< std::string > envp
Definition: process.hh:214
gem5::auxv::Phnum
@ Phnum
Definition: aux_vector.hh:74
name
const std::string & name()
Definition: trace.cc:49
gem5::ArmISA::MISCREG_ID_AA64ISAR1_EL1
@ MISCREG_ID_AA64ISAR1_EL1
Definition: misc.hh:568
gem5::Process
Definition: process.hh:67
gem5::auxv::Execfn
@ Execfn
Definition: aux_vector.hh:91
gem5::loader::Thumb
@ Thumb
Definition: object_file.hh:60
aux_vector.hh
gem5::ArmISA::MODE_EL0T
@ MODE_EL0T
Definition: types.hh:274
gem5::System::threads
Threads threads
Definition: system.hh:316
misc.hh
gem5::ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::htole
T htole(T value)
Definition: byteswap.hh:172
gem5::auxv::Uid
@ Uid
Definition: aux_vector.hh:80
gem5::ArmISA::PageBytes
const Addr PageBytes
Definition: page_size.hh:53
gem5::roundUp
static constexpr T roundUp(const T &val, const U &align)
This function is used to align addresses in memory.
Definition: intmath.hh:260
logging.hh
gem5::Process::system
System * system
Definition: process.hh:162
gem5::ArmISA::id
Bitfield< 33 > id
Definition: misc_types.hh:250
gem5::ArmISA::ArgumentReg1
const int ArgumentReg1
Definition: int.hh:541
gem5::auxv::Euid
@ Euid
Definition: aux_vector.hh:81
gem5::Process::contextIds
std::vector< ContextID > contextIds
Definition: process.hh:159
page_size.hh
gem5::ArmProcess32::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: process.cc:107
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:225
page_table.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::MISCREG_ID_AA64PFR0_EL1
@ MISCREG_ID_AA64PFR0_EL1
Definition: misc.hh:561
process.hh
gem5::auxv::Flags
@ Flags
Definition: aux_vector.hh:77
object_file.hh
gem5::ArmISA::MISCREG_CPACR
@ MISCREG_CPACR
Definition: misc.hh:241
gem5::ArmProcess64::ArmProcess64
ArmProcess64(const ProcessParams &params, loader::ObjectFile *objFile, loader::Arch _arch)
Definition: process.cc:90
gem5::ArmProcess32::ArmProcess32
ArmProcess32(const ProcessParams &params, loader::ObjectFile *objFile, loader::Arch _arch)
Definition: process.cc:75
gem5::Process::image
loader::MemoryImage image
Definition: process.hh:211
thread_context.hh
gem5::Process::objFile
loader::ObjectFile * objFile
Definition: process.hh:210
gem5::ArmISA::MISCREG_ID_AA64ISAR0_EL1
@ MISCREG_ID_AA64ISAR0_EL1
Definition: misc.hh:567
gem5::loader::Linux
@ Linux
Definition: object_file.hh:73
byteswap.hh

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