gem5  v21.2.1.1
queued.cc
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37 
39 
40 #include <cassert>
41 
42 #include "arch/generic/tlb.hh"
43 #include "base/logging.hh"
44 #include "base/trace.hh"
45 #include "debug/HWPrefetch.hh"
46 #include "debug/HWPrefetchQueue.hh"
47 #include "mem/cache/base.hh"
48 #include "mem/request.hh"
49 #include "params/QueuedPrefetcher.hh"
50 
51 namespace gem5
52 {
53 
55 namespace prefetch
56 {
57 
58 void
59 Queued::DeferredPacket::createPkt(Addr paddr, unsigned blk_size,
60  RequestorID requestor_id,
61  bool tag_prefetch,
62  Tick t) {
63  /* Create a prefetch memory request */
64  RequestPtr req = std::make_shared<Request>(paddr, blk_size,
65  0, requestor_id);
66 
67  if (pfInfo.isSecure()) {
68  req->setFlags(Request::SECURE);
69  }
71  pkt = new Packet(req, MemCmd::HardPFReq);
72  pkt->allocate();
73  if (tag_prefetch && pfInfo.hasPC()) {
74  // Tag prefetch packet with accessing pc
75  pkt->req->setPC(pfInfo.getPC());
76  }
77  tick = t;
78 }
79 
80 void
82 {
83  assert(translationRequest != nullptr);
84  if (!ongoingTranslation) {
85  ongoingTranslation = true;
86  // Prefetchers only operate in Timing mode
87  tlb->translateTiming(translationRequest, tc, this, BaseMMU::Read);
88  }
89 }
90 
91 void
93  const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode)
94 {
95  assert(ongoingTranslation);
96  ongoingTranslation = false;
97  bool failed = (fault != NoFault);
98  owner->translationComplete(this, failed);
99 }
100 
101 Queued::Queued(const QueuedPrefetcherParams &p)
102  : Base(p), queueSize(p.queue_size),
104  p.max_prefetch_requests_with_pending_translation),
105  latency(p.latency), queueSquash(p.queue_squash),
106  queueFilter(p.queue_filter), cacheSnoop(p.cache_snoop),
107  tagPrefetch(p.tag_prefetch),
108  throttleControlPct(p.throttle_control_percentage), statsQueued(this)
109 {
110 }
111 
113 {
114  // Delete the queued prefetch packets
115  for (DeferredPacket &p : pfq) {
116  delete p.pkt;
117  }
118 }
119 
120 void
122 {
123  int pos = 0;
124  std::string queue_name = "";
125  if (&queue == &pfq) {
126  queue_name = "PFQ";
127  } else {
128  assert(&queue == &pfqMissingTranslation);
129  queue_name = "PFTransQ";
130  }
131 
132  for (const_iterator it = queue.cbegin(); it != queue.cend();
133  it++, pos++) {
134  Addr vaddr = it->pfInfo.getAddr();
135  /* Set paddr to 0 if not yet translated */
136  Addr paddr = it->pkt ? it->pkt->getAddr() : 0;
137  DPRINTF(HWPrefetchQueue, "%s[%d]: Prefetch Req VA: %#x PA: %#x "
138  "prio: %3d\n", queue_name, pos, vaddr, paddr, it->priority);
139  }
140 }
141 
142 size_t
144 {
161  size_t max_pfs = total;
162  if (total > 0 && issuedPrefetches > 0) {
163  size_t throttle_pfs = (total * throttleControlPct) / 100;
164  size_t min_pfs = (total - throttle_pfs) == 0 ?
165  1 : (total - throttle_pfs);
166  max_pfs = min_pfs + (total - min_pfs) *
168  }
169  return max_pfs;
170 }
171 
172 void
173 Queued::notify(const PacketPtr &pkt, const PrefetchInfo &pfi)
174 {
175  Addr blk_addr = blockAddress(pfi.getAddr());
176  bool is_secure = pfi.isSecure();
177 
178  // Squash queued prefetches if demand miss to same line
179  if (queueSquash) {
180  auto itr = pfq.begin();
181  while (itr != pfq.end()) {
182  if (itr->pfInfo.getAddr() == blk_addr &&
183  itr->pfInfo.isSecure() == is_secure) {
184  DPRINTF(HWPrefetch, "Removing pf candidate addr: %#x "
185  "(cl: %#x), demand request going to the same addr\n",
186  itr->pfInfo.getAddr(),
187  blockAddress(itr->pfInfo.getAddr()));
188  delete itr->pkt;
189  itr = pfq.erase(itr);
191  } else {
192  ++itr;
193  }
194  }
195  }
196 
197  // Calculate prefetches given this access
198  std::vector<AddrPriority> addresses;
199  calculatePrefetch(pfi, addresses);
200 
201  // Get the maximu number of prefetches that we are allowed to generate
202  size_t max_pfs = getMaxPermittedPrefetches(addresses.size());
203 
204  // Queue up generated prefetches
205  size_t num_pfs = 0;
206  for (AddrPriority& addr_prio : addresses) {
207 
208  // Block align prefetch address
209  addr_prio.first = blockAddress(addr_prio.first);
210 
211  if (!samePage(addr_prio.first, pfi.getAddr())) {
212  statsQueued.pfSpanPage += 1;
213  }
214 
215  bool can_cross_page = (tlb != nullptr);
216  if (can_cross_page || samePage(addr_prio.first, pfi.getAddr())) {
217  PrefetchInfo new_pfi(pfi,addr_prio.first);
219  DPRINTF(HWPrefetch, "Found a pf candidate addr: %#x, "
220  "inserting into prefetch queue.\n", new_pfi.getAddr());
221  // Create and insert the request
222  insert(pkt, new_pfi, addr_prio.second);
223  num_pfs += 1;
224  if (num_pfs == max_pfs) {
225  break;
226  }
227  } else {
228  DPRINTF(HWPrefetch, "Ignoring page crossing prefetch.\n");
229  }
230  }
231 }
232 
233 PacketPtr
235 {
236  DPRINTF(HWPrefetch, "Requesting a prefetch to issue.\n");
237 
238  if (pfq.empty()) {
239  // If the queue is empty, attempt first to fill it with requests
240  // from the queue of missing translations
242  }
243 
244  if (pfq.empty()) {
245  DPRINTF(HWPrefetch, "No hardware prefetches available.\n");
246  return nullptr;
247  }
248 
249  PacketPtr pkt = pfq.front().pkt;
250  pfq.pop_front();
251 
253  issuedPrefetches += 1;
254  assert(pkt != nullptr);
255  DPRINTF(HWPrefetch, "Generating prefetch for %#x.\n", pkt->getAddr());
256 
258  return pkt;
259 }
260 
262  : statistics::Group(parent),
263  ADD_STAT(pfIdentified, statistics::units::Count::get(),
264  "number of prefetch candidates identified"),
265  ADD_STAT(pfBufferHit, statistics::units::Count::get(),
266  "number of redundant prefetches already in prefetch queue"),
267  ADD_STAT(pfInCache, statistics::units::Count::get(),
268  "number of redundant prefetches already in cache/mshr dropped"),
269  ADD_STAT(pfRemovedDemand, statistics::units::Count::get(),
270  "number of prefetches dropped due to a demand for the same "
271  "address"),
272  ADD_STAT(pfRemovedFull, statistics::units::Count::get(),
273  "number of prefetches dropped due to prefetch queue size"),
274  ADD_STAT(pfSpanPage, statistics::units::Count::get(),
275  "number of prefetches that crossed the page")
276 {
277 }
278 
279 
280 void
282 {
283  unsigned count = 0;
284  iterator it = pfqMissingTranslation.begin();
285  while (it != pfqMissingTranslation.end() && count < max) {
286  DeferredPacket &dp = *it;
287  // Increase the iterator first because dp.startTranslation can end up
288  // calling finishTranslation, which will erase "it"
289  it++;
290  dp.startTranslation(tlb);
291  count += 1;
292  }
293 }
294 
295 void
297 {
298  auto it = pfqMissingTranslation.begin();
299  while (it != pfqMissingTranslation.end()) {
300  if (&(*it) == dp) {
301  break;
302  }
303  it++;
304  }
305  assert(it != pfqMissingTranslation.end());
306  if (!failed) {
307  DPRINTF(HWPrefetch, "%s Translation of vaddr %#x succeeded: "
308  "paddr %#x \n", tlb->name(),
309  it->translationRequest->getVaddr(),
310  it->translationRequest->getPaddr());
311  Addr target_paddr = it->translationRequest->getPaddr();
312  // check if this prefetch is already redundant
313  if (cacheSnoop && (inCache(target_paddr, it->pfInfo.isSecure()) ||
314  inMissQueue(target_paddr, it->pfInfo.isSecure()))) {
316  DPRINTF(HWPrefetch, "Dropping redundant in "
317  "cache/MSHR prefetch addr:%#x\n", target_paddr);
318  } else {
319  Tick pf_time = curTick() + clockPeriod() * latency;
320  it->createPkt(target_paddr, blkSize, requestorId, tagPrefetch,
321  pf_time);
322  addToQueue(pfq, *it);
323  }
324  } else {
325  DPRINTF(HWPrefetch, "%s Translation of vaddr %#x failed, dropping "
326  "prefetch request %#x \n", tlb->name(),
327  it->translationRequest->getVaddr());
328  }
329  pfqMissingTranslation.erase(it);
330 }
331 
332 bool
334  const PrefetchInfo &pfi, int32_t priority)
335 {
336  bool found = false;
337  iterator it;
338  for (it = queue.begin(); it != queue.end() && !found; it++) {
339  found = it->pfInfo.sameAddr(pfi);
340  }
341 
342  /* If the address is already in the queue, update priority and leave */
343  if (it != queue.end()) {
345  if (it->priority < priority) {
346  /* Update priority value and position in the queue */
347  it->priority = priority;
348  iterator prev = it;
349  while (prev != queue.begin()) {
350  prev--;
351  /* If the packet has higher priority, swap */
352  if (*it > *prev) {
353  std::swap(*it, *prev);
354  it = prev;
355  }
356  }
357  DPRINTF(HWPrefetch, "Prefetch addr already in "
358  "prefetch queue, priority updated\n");
359  } else {
360  DPRINTF(HWPrefetch, "Prefetch addr already in "
361  "prefetch queue\n");
362  }
363  }
364  return found;
365 }
366 
369  PacketPtr pkt)
370 {
371  RequestPtr translation_req = std::make_shared<Request>(
372  addr, blkSize, pkt->req->getFlags(), requestorId, pfi.getPC(),
373  pkt->req->contextId());
374  translation_req->setFlags(Request::PREFETCH);
375  return translation_req;
376 }
377 
378 void
379 Queued::insert(const PacketPtr &pkt, PrefetchInfo &new_pfi,
380  int32_t priority)
381 {
382  if (queueFilter) {
383  if (alreadyInQueue(pfq, new_pfi, priority)) {
384  return;
385  }
386  if (alreadyInQueue(pfqMissingTranslation, new_pfi, priority)) {
387  return;
388  }
389  }
390 
391  /*
392  * Physical address computation
393  * if the prefetch is within the same page
394  * using VA: add the computed stride to the original PA
395  * using PA: no actions needed
396  * if we are page crossing
397  * using VA: Create a translaion request and enqueue the corresponding
398  * deferred packet to the queue of pending translations
399  * using PA: use the provided VA to obtain the target VA, then attempt to
400  * translate the resulting address
401  */
402 
403  Addr orig_addr = useVirtualAddresses ?
404  pkt->req->getVaddr() : pkt->req->getPaddr();
405  bool positive_stride = new_pfi.getAddr() >= orig_addr;
406  Addr stride = positive_stride ?
407  (new_pfi.getAddr() - orig_addr) : (orig_addr - new_pfi.getAddr());
408 
409  Addr target_paddr;
410  bool has_target_pa = false;
411  RequestPtr translation_req = nullptr;
412  if (samePage(orig_addr, new_pfi.getAddr())) {
413  if (useVirtualAddresses) {
414  // if we trained with virtual addresses,
415  // compute the target PA using the original PA and adding the
416  // prefetch stride (difference between target VA and original VA)
417  target_paddr = positive_stride ? (pkt->req->getPaddr() + stride) :
418  (pkt->req->getPaddr() - stride);
419  } else {
420  target_paddr = new_pfi.getAddr();
421  }
422  has_target_pa = true;
423  } else {
424  // Page crossing reference
425 
426  // ContextID is needed for translation
427  if (!pkt->req->hasContextId()) {
428  return;
429  }
430  if (useVirtualAddresses) {
431  has_target_pa = false;
432  translation_req = createPrefetchRequest(new_pfi.getAddr(), new_pfi,
433  pkt);
434  } else if (pkt->req->hasVaddr()) {
435  has_target_pa = false;
436  // Compute the target VA using req->getVaddr + stride
437  Addr target_vaddr = positive_stride ?
438  (pkt->req->getVaddr() + stride) :
439  (pkt->req->getVaddr() - stride);
440  translation_req = createPrefetchRequest(target_vaddr, new_pfi,
441  pkt);
442  } else {
443  // Using PA for training but the request does not have a VA,
444  // unable to process this page crossing prefetch.
445  return;
446  }
447  }
448  if (has_target_pa && cacheSnoop &&
449  (inCache(target_paddr, new_pfi.isSecure()) ||
450  inMissQueue(target_paddr, new_pfi.isSecure()))) {
452  DPRINTF(HWPrefetch, "Dropping redundant in "
453  "cache/MSHR prefetch addr:%#x\n", target_paddr);
454  return;
455  }
456 
457  /* Create the packet and find the spot to insert it */
458  DeferredPacket dpp(this, new_pfi, 0, priority);
459  if (has_target_pa) {
460  Tick pf_time = curTick() + clockPeriod() * latency;
461  dpp.createPkt(target_paddr, blkSize, requestorId, tagPrefetch,
462  pf_time);
463  DPRINTF(HWPrefetch, "Prefetch queued. "
464  "addr:%#x priority: %3d tick:%lld.\n",
465  new_pfi.getAddr(), priority, pf_time);
466  addToQueue(pfq, dpp);
467  } else {
468  // Add the translation request and try to resolve it later
469  dpp.setTranslationRequest(translation_req);
470  dpp.tc = cache->system->threads[translation_req->contextId()];
471  DPRINTF(HWPrefetch, "Prefetch queued with no translation. "
472  "addr:%#x priority: %3d\n", new_pfi.getAddr(), priority);
474  }
475 }
476 
477 void
479  DeferredPacket &dpp)
480 {
481  /* Verify prefetch buffer space for request */
482  if (queue.size() == queueSize) {
484  /* Lowest priority packet */
485  iterator it = queue.end();
486  panic_if (it == queue.begin(),
487  "Prefetch queue is both full and empty!");
488  --it;
489  /* Look for oldest in that level of priority */
490  panic_if (it == queue.begin(),
491  "Prefetch queue is full with 1 element!");
492  iterator prev = it;
493  bool cont = true;
494  /* While not at the head of the queue */
495  while (cont && prev != queue.begin()) {
496  prev--;
497  /* While at the same level of priority */
498  cont = prev->priority == it->priority;
499  if (cont)
500  /* update pointer */
501  it = prev;
502  }
503  DPRINTF(HWPrefetch, "Prefetch queue full, removing lowest priority "
504  "oldest packet, addr: %#x\n",it->pfInfo.getAddr());
505  delete it->pkt;
506  queue.erase(it);
507  }
508 
509  if ((queue.size() == 0) || (dpp <= queue.back())) {
510  queue.emplace_back(dpp);
511  } else {
512  iterator it = queue.end();
513  do {
514  --it;
515  } while (it != queue.begin() && dpp > *it);
516  /* If we reach the head, we have to see if the new element is new head
517  * or not */
518  if (it == queue.begin() && dpp <= *it)
519  it++;
520  queue.insert(it, dpp);
521  }
522 
523  if (debug::HWPrefetchQueue)
524  printQueue(queue);
525 }
526 
527 } // namespace prefetch
528 } // namespace gem5
gem5::prefetch::Base::PrefetchInfo::getAddr
Addr getAddr() const
Obtains the address value of this Prefetcher address.
Definition: base.hh:125
gem5::prefetch::Queued::DeferredPacket::finish
void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override
Definition: queued.cc:92
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::prefetch::Base::useVirtualAddresses
const bool useVirtualAddresses
Use Virtual Addresses for prefetching.
Definition: base.hh:302
gem5::prefetch::Queued::~Queued
virtual ~Queued()
Definition: queued.cc:112
gem5::prefetch::Queued::cacheSnoop
const bool cacheSnoop
Snoop the cache before generating prefetch (cheating basically)
Definition: queued.hh:170
gem5::BaseMMU::Read
@ Read
Definition: mmu.hh:56
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::prefetch::Queued::notify
void notify(const PacketPtr &pkt, const PrefetchInfo &pfi) override
Notify prefetcher of cache access (may be any access or just misses, depending on cache parameters....
Definition: queued.cc:173
gem5::prefetch::Queued::iterator
std::list< DeferredPacket >::iterator iterator
Definition: queued.hh:147
gem5::prefetch::Queued::addToQueue
void addToQueue(std::list< DeferredPacket > &queue, DeferredPacket &dpp)
Adds a DeferredPacket to the specified queue.
Definition: queued.cc:478
base.hh
gem5::prefetch::Queued::QueuedStats::pfRemovedDemand
statistics::Scalar pfRemovedDemand
Definition: queued.hh:185
gem5::prefetch::Queued::DeferredPacket::tick
Tick tick
Time when this prefetch becomes ready.
Definition: queued.hh:70
gem5::prefetch::Queued::getMaxPermittedPrefetches
size_t getMaxPermittedPrefetches(size_t total) const
Returns the maxmimum number of prefetch requests that are allowed to be created from the number of pr...
Definition: queued.cc:143
gem5::prefetch::Queued::DeferredPacket::setTranslationRequest
void setTranslationRequest(const RequestPtr &req)
Sets the translation request needed to obtain the physical address of this request.
Definition: queued.hh:125
gem5::prefetch::Queued::QueuedStats::pfInCache
statistics::Scalar pfInCache
Definition: queued.hh:184
gem5::prefetch::Base::PrefetchInfo::isSecure
bool isSecure() const
Returns true if the address targets the secure memory space.
Definition: base.hh:134
gem5::prefetch::Queued::QueuedStats::pfSpanPage
statistics::Scalar pfSpanPage
Definition: queued.hh:187
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:56
gem5::prefetch::Base::StatGroup::pfIssued
statistics::Scalar pfIssued
Definition: base.hh:335
gem5::Packet::req
RequestPtr req
A pointer to the original request.
Definition: packet.hh:366
gem5::prefetch::Queued::missingTranslationQueueSize
const unsigned missingTranslationQueueSize
Maximum size of the queue holding prefetch requests with missing address translations.
Definition: queued.hh:158
tlb.hh
gem5::Request::SECURE
@ SECURE
The request targets the secure memory space.
Definition: request.hh:186
gem5::prefetch::Base::inMissQueue
bool inMissQueue(Addr addr, bool is_secure) const
Determine if address is in cache miss queue.
Definition: base.cc:195
std::vector
STL vector class.
Definition: stl.hh:37
gem5::prefetch::Queued::printQueue
void printQueue(const std::list< DeferredPacket > &queue) const
Definition: queued.cc:121
gem5::prefetch::Base::blockAddress
Addr blockAddress(Addr a) const
Determine the address of the block in which a lays.
Definition: base.cc:213
gem5::prefetch::Queued::QueuedStats::pfIdentified
statistics::Scalar pfIdentified
Definition: queued.hh:182
gem5::prefetch::Queued::tagPrefetch
const bool tagPrefetch
Tag prefetch with PC of generating access?
Definition: queued.hh:173
gem5::MemCmd::HardPFReq
@ HardPFReq
Definition: packet.hh:98
gem5::prefetch::Base::requestorId
const RequestorID requestorId
Request id for prefetches.
Definition: base.hh:291
gem5::prefetch::Queued::insert
void insert(const PacketPtr &pkt, PrefetchInfo &new_pfi, int32_t priority)
Definition: queued.cc:379
gem5::prefetch::Queued::calculatePrefetch
virtual void calculatePrefetch(const PrefetchInfo &pfi, std::vector< AddrPriority > &addresses)=0
request.hh
queued.hh
gem5::prefetch::Base::PrefetchInfo::getPC
Addr getPC() const
Returns the program counter that generated this request.
Definition: base.hh:143
gem5::prefetch::Queued::latency
const Cycles latency
Cycles after generation when a prefetch can first be issued.
Definition: queued.hh:161
gem5::prefetch::Base::samePage
bool samePage(Addr a, Addr b) const
Determine if addresses are on the same page.
Definition: base.cc:207
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
ADD_STAT
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
Definition: group.hh:75
gem5::X86ISA::count
count
Definition: misc.hh:709
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::prefetch::Queued::alreadyInQueue
bool alreadyInQueue(std::list< DeferredPacket > &queue, const PrefetchInfo &pfi, int32_t priority)
Checks whether the specified prefetch request is already in the specified queue.
Definition: queued.cc:333
gem5::prefetch::Base::usefulPrefetches
uint64_t usefulPrefetches
Total prefetches that has been useful.
Definition: base.hh:365
gem5::prefetch::Queued::DeferredPacket::startTranslation
void startTranslation(BaseTLB *tlb)
Issues the translation request to the provided TLB.
Definition: queued.cc:81
gem5::probing::Packet
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:109
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::Request::PREFETCH
@ PREFETCH
The request is a prefetch.
Definition: request.hh:164
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::BaseTLB
Definition: tlb.hh:58
gem5::prefetch::Queued::QueuedStats::pfBufferHit
statistics::Scalar pfBufferHit
Definition: queued.hh:183
gem5::prefetch::Queued::DeferredPacket::createPkt
void createPkt(Addr paddr, unsigned blk_size, RequestorID requestor_id, bool tag_prefetch, Tick t)
Create the associated memory packet.
Definition: queued.cc:59
gem5::prefetch::Queued::throttleControlPct
const unsigned int throttleControlPct
Percentage of requests that can be throttled.
Definition: queued.hh:176
gem5::BaseTLB::translateTiming
virtual void translateTiming(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode)=0
gem5::ArmISA::t
Bitfield< 5 > t
Definition: misc_types.hh:71
std::pair
STL pair class.
Definition: stl.hh:58
gem5::prefetch::Queued::getPacket
PacketPtr getPacket() override
Definition: queued.cc:234
gem5::prefetch::Queued::pfq
std::list< DeferredPacket > pfq
Definition: queued.hh:143
gem5::prefetch::Queued::QueuedStats::QueuedStats
QueuedStats(statistics::Group *parent)
Definition: queued.cc:261
gem5::prefetch::Queued::queueFilter
const bool queueFilter
Filter prefetches if already queued.
Definition: queued.hh:167
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
gem5::prefetch::Queued::translationComplete
void translationComplete(DeferredPacket *dp, bool failed)
Indicates that the translation of the address of the provided deferred packet has been successfully c...
Definition: queued.cc:296
gem5::prefetch::Queued::DeferredPacket::tc
ThreadContext * tc
Definition: queued.hh:77
gem5::prefetch::Queued::queueSize
const unsigned queueSize
Maximum size of the prefetch queue.
Definition: queued.hh:152
gem5::prefetch::Base::prefetchStats
gem5::prefetch::Base::StatGroup prefetchStats
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:204
gem5::prefetch::Queued::DeferredPacket::pfInfo
PrefetchInfo pfInfo
Prefetch info corresponding to this packet.
Definition: queued.hh:68
gem5::prefetch::Base::issuedPrefetches
uint64_t issuedPrefetches
Total prefetches issued.
Definition: base.hh:363
gem5::prefetch::Queued::processMissingTranslations
void processMissingTranslations(unsigned max)
Starts the translations of the queued prefetches with a missing translation.
Definition: queued.cc:281
gem5::Packet::allocate
void allocate()
Allocate memory for the packet.
Definition: packet.hh:1326
gem5::System::threads
Threads threads
Definition: system.hh:314
gem5::prefetch::Queued::DeferredPacket::pkt
PacketPtr pkt
The memory packet generated by this prefetch.
Definition: queued.hh:72
gem5::prefetch::Queued::Queued
Queued(const QueuedPrefetcherParams &p)
Definition: queued.cc:101
gem5::BaseCache::system
System * system
System we are currently operating in.
Definition: base.hh:986
logging.hh
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::prefetch::Base::cache
BaseCache * cache
Pointr to the parent cache.
Definition: base.hh:267
gem5::prefetch::Base::blkSize
unsigned blkSize
The block size of the parent cache.
Definition: base.hh:270
gem5::RequestorID
uint16_t RequestorID
Definition: request.hh:95
gem5::prefetch::Base::tlb
BaseTLB * tlb
Registered tlb for address translations.
Definition: base.hh:368
trace.hh
gem5::context_switch_task_id::Prefetcher
@ Prefetcher
Definition: request.hh:83
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::prefetch::Base::inCache
bool inCache(Addr addr, bool is_secure) const
Determine if address is in cache.
Definition: base.cc:189
gem5::prefetch::Queued::createPrefetchRequest
RequestPtr createPrefetchRequest(Addr addr, PrefetchInfo const &pfi, PacketPtr pkt)
Definition: queued.cc:368
std::list< DeferredPacket >
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:781
gem5::prefetch::Queued::const_iterator
std::list< DeferredPacket >::const_iterator const_iterator
Definition: queued.hh:146
gem5::prefetch::Queued::DeferredPacket
Definition: queued.hh:63
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::statistics::total
const FlagsType total
Print the total.
Definition: info.hh:60
gem5::ArmISA::stride
Bitfield< 21, 20 > stride
Definition: misc_types.hh:447
gem5::prefetch::Base
Definition: base.hh:72
gem5::prefetch::Base::PrefetchInfo
Class containing the information needed by the prefetch to train and generate new prefetch requests.
Definition: base.hh:97
gem5::ArmISA::dp
Bitfield< 47, 44 > dp
Definition: misc_types.hh:95
gem5::prefetch::Queued::QueuedStats::pfRemovedFull
statistics::Scalar pfRemovedFull
Definition: queued.hh:186
gem5::Clocked::clockPeriod
Tick clockPeriod() const
Definition: clocked_object.hh:217
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:74
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::prefetch::Queued::pfqMissingTranslation
std::list< DeferredPacket > pfqMissingTranslation
Definition: queued.hh:144
gem5::prefetch::Base::PrefetchInfo::hasPC
bool hasPC() const
Returns true if the associated program counter is valid.
Definition: base.hh:153
gem5::prefetch::Queued::queueSquash
const bool queueSquash
Squash queued prefetch if demand access observed.
Definition: queued.hh:164
gem5::prefetch::Queued::statsQueued
gem5::prefetch::Queued::QueuedStats statsQueued

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