gem5 v24.0.0.0
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queued.cc
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1/*
2 * Copyright (c) 2014-2015, 2022-2023 Arm Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
39
40#include <cassert>
41
42#include "arch/generic/tlb.hh"
43#include "base/logging.hh"
44#include "base/trace.hh"
45#include "debug/HWPrefetch.hh"
46#include "debug/HWPrefetchQueue.hh"
47#include "mem/cache/base.hh"
48#include "mem/request.hh"
49#include "params/QueuedPrefetcher.hh"
50
51namespace gem5
52{
53
54namespace prefetch
55{
56
57void
58Queued::DeferredPacket::createPkt(Addr paddr, unsigned blk_size,
59 RequestorID requestor_id,
60 bool tag_prefetch,
61 Tick t) {
62 /* Create a prefetch memory request */
63 RequestPtr req = std::make_shared<Request>(paddr, blk_size,
64 0, requestor_id);
65
66 if (pfInfo.isSecure()) {
67 req->setFlags(Request::SECURE);
68 }
70 pkt = new Packet(req, MemCmd::HardPFReq);
71 pkt->allocate();
72 if (tag_prefetch && pfInfo.hasPC()) {
73 // Tag prefetch packet with accessing pc
74 pkt->req->setPC(pfInfo.getPC());
75 }
76 tick = t;
77}
78
79void
81{
82 assert(translationRequest != nullptr);
83 if (!ongoingTranslation) {
84 ongoingTranslation = true;
85 // Prefetchers only operate in Timing mode
86 mmu->translateTiming(translationRequest, tc, this, BaseMMU::Read);
87 }
88}
89
90void
93{
94 assert(ongoingTranslation);
95 ongoingTranslation = false;
96 bool failed = (fault != NoFault);
97 owner->translationComplete(this, failed, *cache);
98}
99
100Queued::Queued(const QueuedPrefetcherParams &p)
101 : Base(p), queueSize(p.queue_size),
103 p.max_prefetch_requests_with_pending_translation),
104 latency(p.latency), queueSquash(p.queue_squash),
105 queueFilter(p.queue_filter), cacheSnoop(p.cache_snoop),
106 tagPrefetch(p.tag_prefetch),
107 throttleControlPct(p.throttle_control_percentage), statsQueued(this)
108{
109}
110
112{
113 // Delete the queued prefetch packets
114 for (DeferredPacket &p : pfq) {
115 delete p.pkt;
116 }
117}
118
119void
121{
122 int pos = 0;
123 std::string queue_name = "";
124 if (&queue == &pfq) {
125 queue_name = "PFQ";
126 } else {
127 assert(&queue == &pfqMissingTranslation);
128 queue_name = "PFTransQ";
129 }
130
131 for (const_iterator it = queue.cbegin(); it != queue.cend();
132 it++, pos++) {
133 Addr vaddr = it->pfInfo.getAddr();
134 /* Set paddr to 0 if not yet translated */
135 Addr paddr = it->pkt ? it->pkt->getAddr() : 0;
136 DPRINTF(HWPrefetchQueue, "%s[%d]: Prefetch Req VA: %#x PA: %#x "
137 "prio: %3d\n", queue_name, pos, vaddr, paddr, it->priority);
138 }
139}
140
141size_t
143{
160 size_t max_pfs = total;
161 if (total > 0 && issuedPrefetches > 0) {
162 size_t throttle_pfs = (total * throttleControlPct) / 100;
163 size_t min_pfs = (total - throttle_pfs) == 0 ?
164 1 : (total - throttle_pfs);
165 max_pfs = min_pfs + (total - min_pfs) *
167 }
168 return max_pfs;
169}
170
171void
173{
174 Addr blk_addr = blockAddress(pfi.getAddr());
175 bool is_secure = pfi.isSecure();
176 const PacketPtr pkt = acc.pkt;
177 const CacheAccessor &cache = acc.cache;
178
179 // Squash queued prefetches if demand miss to same line
180 if (queueSquash) {
181 auto itr = pfq.begin();
182 while (itr != pfq.end()) {
183 if (blockAddress(itr->pfInfo.getAddr()) == blk_addr &&
184 itr->pfInfo.isSecure() == is_secure) {
185 DPRINTF(HWPrefetch, "Removing pf candidate addr: %#x "
186 "(cl: %#x), demand request going to the same addr\n",
187 itr->pfInfo.getAddr(),
188 blockAddress(itr->pfInfo.getAddr()));
189 delete itr->pkt;
190 itr = pfq.erase(itr);
192 } else {
193 ++itr;
194 }
195 }
196 }
197
198 // Calculate prefetches given this access
200 calculatePrefetch(pfi, addresses, cache);
201
202 // Get the maximu number of prefetches that we are allowed to generate
203 size_t max_pfs = getMaxPermittedPrefetches(addresses.size());
204
205 // Queue up generated prefetches
206 size_t num_pfs = 0;
207 for (AddrPriority& addr_prio : addresses) {
208
209 // Block align prefetch address
210 addr_prio.first = blockAddress(addr_prio.first);
211
212 if (!samePage(addr_prio.first, pfi.getAddr())) {
214
215 if (cache.hasBeenPrefetched(pkt->getAddr(), pkt->isSecure())) {
217 }
218 }
219
220 bool can_cross_page = (mmu != nullptr);
221 if (can_cross_page || samePage(addr_prio.first, pfi.getAddr())) {
222 PrefetchInfo new_pfi(pfi,addr_prio.first);
224 DPRINTF(HWPrefetch, "Found a pf candidate addr: %#x, "
225 "inserting into prefetch queue.\n", new_pfi.getAddr());
226 // Create and insert the request
227 insert(pkt, new_pfi, addr_prio.second, cache);
228 num_pfs += 1;
229 if (num_pfs == max_pfs) {
230 break;
231 }
232 } else {
233 DPRINTF(HWPrefetch, "Ignoring page crossing prefetch.\n");
234 }
235 }
236}
237
240{
241 DPRINTF(HWPrefetch, "Requesting a prefetch to issue.\n");
242
243 if (pfq.empty()) {
244 // If the queue is empty, attempt first to fill it with requests
245 // from the queue of missing translations
247 }
248
249 if (pfq.empty()) {
250 DPRINTF(HWPrefetch, "No hardware prefetches available.\n");
251 return nullptr;
252 }
253
254 PacketPtr pkt = pfq.front().pkt;
255 pfq.pop_front();
256
258 issuedPrefetches += 1;
259 assert(pkt != nullptr);
260 DPRINTF(HWPrefetch, "Generating prefetch for %#x.\n", pkt->getAddr());
261
263 return pkt;
264}
265
267 : statistics::Group(parent),
268 ADD_STAT(pfIdentified, statistics::units::Count::get(),
269 "number of prefetch candidates identified"),
270 ADD_STAT(pfBufferHit, statistics::units::Count::get(),
271 "number of redundant prefetches already in prefetch queue"),
272 ADD_STAT(pfInCache, statistics::units::Count::get(),
273 "number of redundant prefetches already in cache/mshr dropped"),
274 ADD_STAT(pfRemovedDemand, statistics::units::Count::get(),
275 "number of prefetches dropped due to a demand for the same "
276 "address"),
277 ADD_STAT(pfRemovedFull, statistics::units::Count::get(),
278 "number of prefetches dropped due to prefetch queue size"),
279 ADD_STAT(pfSpanPage, statistics::units::Count::get(),
280 "number of prefetches that crossed the page"),
281 ADD_STAT(pfUsefulSpanPage, statistics::units::Count::get(),
282 "number of prefetches that is useful and crossed the page")
283{
284}
285
286
287void
289{
290 unsigned count = 0;
291 iterator it = pfqMissingTranslation.begin();
292 while (it != pfqMissingTranslation.end() && count < max) {
293 DeferredPacket &dp = *it;
294 // Increase the iterator first because dp.startTranslation can end up
295 // calling finishTranslation, which will erase "it"
296 it++;
298 count += 1;
299 }
300}
301
302void
304 const CacheAccessor &cache)
305{
306 auto it = pfqMissingTranslation.begin();
307 while (it != pfqMissingTranslation.end()) {
308 if (&(*it) == dp) {
309 break;
310 }
311 it++;
312 }
313 assert(it != pfqMissingTranslation.end());
314 if (!failed) {
315 DPRINTF(HWPrefetch, "%s Translation of vaddr %#x succeeded: "
316 "paddr %#x \n", mmu->name(),
317 it->translationRequest->getVaddr(),
318 it->translationRequest->getPaddr());
319 Addr target_paddr = it->translationRequest->getPaddr();
320 // check if this prefetch is already redundant
321 if (cacheSnoop &&
322 (cache.inCache(target_paddr, it->pfInfo.isSecure()) ||
323 cache.inMissQueue(target_paddr, it->pfInfo.isSecure()))) {
325 DPRINTF(HWPrefetch, "Dropping redundant in "
326 "cache/MSHR prefetch addr:%#x\n", target_paddr);
327 } else {
328 Tick pf_time = curTick() + clockPeriod() * latency;
329 it->createPkt(target_paddr, blkSize, requestorId, tagPrefetch,
330 pf_time);
331 addToQueue(pfq, *it);
332 }
333 } else {
334 DPRINTF(HWPrefetch, "%s Translation of vaddr %#x failed, dropping "
335 "prefetch request %#x \n", mmu->name(),
336 it->translationRequest->getVaddr());
337 }
338 pfqMissingTranslation.erase(it);
339}
340
341bool
343 const PrefetchInfo &pfi, int32_t priority)
344{
345 bool found = false;
346 iterator it;
347 for (it = queue.begin(); it != queue.end() && !found; it++) {
348 found = it->pfInfo.sameAddr(pfi);
349 }
350
351 /* If the address is already in the queue, update priority and leave */
352 if (it != queue.end()) {
354 if (it->priority < priority) {
355 /* Update priority value and position in the queue */
356 it->priority = priority;
357 iterator prev = it;
358 while (prev != queue.begin()) {
359 prev--;
360 /* If the packet has higher priority, swap */
361 if (*it > *prev) {
362 std::swap(*it, *prev);
363 it = prev;
364 }
365 }
366 DPRINTF(HWPrefetch, "Prefetch addr already in "
367 "prefetch queue, priority updated\n");
368 } else {
369 DPRINTF(HWPrefetch, "Prefetch addr already in "
370 "prefetch queue\n");
371 }
372 }
373 return found;
374}
375
378 PacketPtr pkt)
379{
380 RequestPtr translation_req = std::make_shared<Request>(
381 addr, blkSize, pkt->req->getFlags(), requestorId, pfi.getPC(),
382 pkt->req->contextId());
383 translation_req->setFlags(Request::PREFETCH);
384 return translation_req;
385}
386
387void
389 int32_t priority, const CacheAccessor &cache)
390{
391 if (queueFilter) {
392 if (alreadyInQueue(pfq, new_pfi, priority)) {
393 return;
394 }
396 return;
397 }
398 }
399
400 /*
401 * Physical address computation
402 * if the prefetch is within the same page
403 * using VA: add the computed stride to the original PA
404 * using PA: no actions needed
405 * if we are page crossing
406 * using VA: Create a translaion request and enqueue the corresponding
407 * deferred packet to the queue of pending translations
408 * using PA: use the provided VA to obtain the target VA, then attempt to
409 * translate the resulting address
410 */
411
412 Addr orig_addr = useVirtualAddresses ?
413 pkt->req->getVaddr() : pkt->req->getPaddr();
414 bool positive_stride = new_pfi.getAddr() >= orig_addr;
415 Addr stride = positive_stride ?
416 (new_pfi.getAddr() - orig_addr) : (orig_addr - new_pfi.getAddr());
417
418 Addr target_paddr;
419 bool has_target_pa = false;
420 RequestPtr translation_req = nullptr;
421 if (samePage(orig_addr, new_pfi.getAddr())) {
423 // if we trained with virtual addresses,
424 // compute the target PA using the original PA and adding the
425 // prefetch stride (difference between target VA and original VA)
426 target_paddr = positive_stride ? (pkt->req->getPaddr() + stride) :
427 (pkt->req->getPaddr() - stride);
428 } else {
429 target_paddr = new_pfi.getAddr();
430 }
431 has_target_pa = true;
432 } else {
433 // Page crossing reference
434
435 // ContextID is needed for translation
436 if (!pkt->req->hasContextId()) {
437 return;
438 }
440 has_target_pa = false;
441 translation_req = createPrefetchRequest(new_pfi.getAddr(), new_pfi,
442 pkt);
443 } else if (pkt->req->hasVaddr()) {
444 has_target_pa = false;
445 // Compute the target VA using req->getVaddr + stride
446 Addr target_vaddr = positive_stride ?
447 (pkt->req->getVaddr() + stride) :
448 (pkt->req->getVaddr() - stride);
449 translation_req = createPrefetchRequest(target_vaddr, new_pfi,
450 pkt);
451 } else {
452 // Using PA for training but the request does not have a VA,
453 // unable to process this page crossing prefetch.
454 return;
455 }
456 }
457 if (has_target_pa && cacheSnoop &&
458 (cache.inCache(target_paddr, new_pfi.isSecure()) ||
459 cache.inMissQueue(target_paddr, new_pfi.isSecure()))) {
461 DPRINTF(HWPrefetch, "Dropping redundant in "
462 "cache/MSHR prefetch addr:%#x\n", target_paddr);
463 return;
464 }
465
466 /* Create the packet and find the spot to insert it */
467 DeferredPacket dpp(this, new_pfi, 0, priority, cache);
468 if (has_target_pa) {
469 Tick pf_time = curTick() + clockPeriod() * latency;
470 dpp.createPkt(target_paddr, blkSize, requestorId, tagPrefetch,
471 pf_time);
472 DPRINTF(HWPrefetch, "Prefetch queued. "
473 "addr:%#x priority: %3d tick:%lld.\n",
474 new_pfi.getAddr(), priority, pf_time);
475 addToQueue(pfq, dpp);
476 } else {
477 // Add the translation request and try to resolve it later
478 dpp.setTranslationRequest(translation_req);
479 dpp.tc = system->threads[translation_req->contextId()];
480 DPRINTF(HWPrefetch, "Prefetch queued with no translation. "
481 "addr:%#x priority: %3d\n", new_pfi.getAddr(), priority);
483 }
484}
485
486void
488 DeferredPacket &dpp)
489{
490 /* Verify prefetch buffer space for request */
491 if (queue.size() == queueSize) {
493 /* Lowest priority packet */
494 iterator it = queue.end();
495 panic_if (it == queue.begin(),
496 "Prefetch queue is both full and empty!");
497 --it;
498 /* Look for oldest in that level of priority */
499 panic_if (it == queue.begin(),
500 "Prefetch queue is full with 1 element!");
501 iterator prev = it;
502 bool cont = true;
503 /* While not at the head of the queue */
504 while (cont && prev != queue.begin()) {
505 prev--;
506 /* While at the same level of priority */
507 cont = prev->priority == it->priority;
508 if (cont)
509 /* update pointer */
510 it = prev;
511 }
512 DPRINTF(HWPrefetch, "Prefetch queue full, removing lowest priority "
513 "oldest packet, addr: %#x\n",it->pfInfo.getAddr());
514 delete it->pkt;
515 queue.erase(it);
516 }
517
518 if ((queue.size() == 0) || (dpp <= queue.back())) {
519 queue.emplace_back(dpp);
520 } else {
521 iterator it = queue.end();
522 do {
523 --it;
524 } while (it != queue.begin() && dpp > *it);
525 /* If we reach the head, we have to see if the new element is new head
526 * or not */
527 if (it == queue.begin() && dpp <= *it)
528 it++;
529 queue.insert(it, dpp);
530 }
531
532 if (debug::HWPrefetchQueue)
533 printQueue(queue);
534}
535
536} // namespace prefetch
537} // namespace gem5
#define DPRINTF(x,...)
Definition trace.hh:210
virtual void translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode)
Definition mmu.cc:111
Information provided to probes on a cache event.
PacketPtr pkt
Packet that triggered the cache access.
CacheAccessor & cache
Accessor for the cache.
Tick clockPeriod() const
virtual std::string name() const
Definition named.hh:47
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition packet.hh:295
bool isSecure() const
Definition packet.hh:836
Addr getAddr() const
Definition packet.hh:807
RequestPtr req
A pointer to the original request.
Definition packet.hh:377
void allocate()
Allocate memory for the packet.
Definition packet.hh:1367
@ SECURE
The request targets the secure memory space.
Definition request.hh:186
@ PREFETCH
The request is a prefetch.
Definition request.hh:164
Threads threads
Definition system.hh:310
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Class containing the information needed by the prefetch to train and generate new prefetch requests.
Definition base.hh:111
Addr getPC() const
Returns the program counter that generated this request.
Definition base.hh:156
bool isSecure() const
Returns true if the address targets the secure memory space.
Definition base.hh:147
Addr getAddr() const
Obtains the address value of this Prefetcher address.
Definition base.hh:138
bool hasPC() const
Returns true if the associated program counter is valid.
Definition base.hh:166
const bool useVirtualAddresses
Use Virtual Addresses for prefetching.
Definition base.hh:318
unsigned blkSize
The block size of the parent cache.
Definition base.hh:286
uint64_t issuedPrefetches
Total prefetches issued.
Definition base.hh:372
const RequestorID requestorId
Request id for prefetches.
Definition base.hh:307
uint64_t usefulPrefetches
Total prefetches that has been useful.
Definition base.hh:374
gem5::prefetch::Base::StatGroup prefetchStats
BaseMMU * mmu
Registered mmu for address translations.
Definition base.hh:377
System * system
Pointer to the parent system.
Definition base.hh:280
Addr blockAddress(Addr a) const
Determine the address of the block in which a lays.
Definition base.cc:202
bool samePage(Addr a, Addr b) const
Determine if addresses are on the same page.
Definition base.cc:196
void translationComplete(DeferredPacket *dp, bool failed, const CacheAccessor &cache)
Indicates that the translation of the address of the provided deferred packet has been successfully c...
Definition queued.cc:303
const bool queueSquash
Squash queued prefetch if demand access observed.
Definition queued.hh:165
gem5::prefetch::Queued::QueuedStats statsQueued
void insert(const PacketPtr &pkt, PrefetchInfo &new_pfi, int32_t priority, const CacheAccessor &cache)
Definition queued.cc:388
std::list< DeferredPacket >::iterator iterator
Definition queued.hh:148
void notify(const CacheAccessProbeArg &acc, const PrefetchInfo &pfi) override
Notify prefetcher of cache access (may be any access or just misses, depending on cache parameters....
Definition queued.cc:172
Queued(const QueuedPrefetcherParams &p)
Definition queued.cc:100
void printQueue(const std::list< DeferredPacket > &queue) const
Definition queued.cc:120
const unsigned queueSize
Maximum size of the prefetch queue.
Definition queued.hh:153
std::list< DeferredPacket > pfqMissingTranslation
Definition queued.hh:145
void processMissingTranslations(unsigned max)
Starts the translations of the queued prefetches with a missing translation.
Definition queued.cc:288
RequestPtr createPrefetchRequest(Addr addr, PrefetchInfo const &pfi, PacketPtr pkt)
Definition queued.cc:377
const bool queueFilter
Filter prefetches if already queued.
Definition queued.hh:168
std::list< DeferredPacket >::const_iterator const_iterator
Definition queued.hh:147
virtual void calculatePrefetch(const PrefetchInfo &pfi, std::vector< AddrPriority > &addresses, const CacheAccessor &cache)=0
const bool tagPrefetch
Tag prefetch with PC of generating access?
Definition queued.hh:174
const Cycles latency
Cycles after generation when a prefetch can first be issued.
Definition queued.hh:162
const bool cacheSnoop
Snoop the cache before generating prefetch (cheating basically)
Definition queued.hh:171
const unsigned int throttleControlPct
Percentage of requests that can be throttled.
Definition queued.hh:177
PacketPtr getPacket() override
Definition queued.cc:239
void addToQueue(std::list< DeferredPacket > &queue, DeferredPacket &dpp)
Adds a DeferredPacket to the specified queue.
Definition queued.cc:487
bool alreadyInQueue(std::list< DeferredPacket > &queue, const PrefetchInfo &pfi, int32_t priority)
Checks whether the specified prefetch request is already in the specified queue.
Definition queued.cc:342
size_t getMaxPermittedPrefetches(size_t total) const
Returns the maxmimum number of prefetch requests that are allowed to be created from the number of pr...
Definition queued.cc:142
const unsigned missingTranslationQueueSize
Maximum size of the queue holding prefetch requests with missing address translations.
Definition queued.hh:159
std::list< DeferredPacket > pfq
Definition queued.hh:144
Statistics container.
Definition group.hh:93
STL list class.
Definition stl.hh:51
STL pair class.
Definition stl.hh:58
STL vector class.
Definition stl.hh:37
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
Definition group.hh:75
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition logging.hh:214
Declares a basic cache interface BaseCache.
Bitfield< 4, 0 > mode
Definition misc_types.hh:74
Bitfield< 5 > t
Definition misc_types.hh:71
Bitfield< 7, 4 > dp
Bitfield< 21, 20 > stride
Bitfield< 3, 0 > priority
Bitfield< 0 > p
Bitfield< 3 > addr
Definition types.hh:84
const FlagsType total
Print the total.
Definition info.hh:59
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
std::shared_ptr< FaultBase > Fault
Definition types.hh:249
std::shared_ptr< Request > RequestPtr
Definition request.hh:94
Tick curTick()
The universal simulation clock.
Definition cur_tick.hh:46
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
uint64_t Tick
Tick count type.
Definition types.hh:58
uint16_t RequestorID
Definition request.hh:95
constexpr decltype(nullptr) NoFault
Definition types.hh:253
Declaration of a request, the overall memory request consisting of the parts of the request that are ...
Provides generic cache lookup functions.
virtual bool inCache(Addr addr, bool is_secure) const =0
Determine if address is in cache.
virtual bool inMissQueue(Addr addr, bool is_secure) const =0
Determine if address is in cache miss queue.
virtual bool hasBeenPrefetched(Addr addr, bool is_secure) const =0
Determine if address has been prefetched.
statistics::Scalar pfIssued
Definition base.hh:344
Tick tick
Time when this prefetch becomes ready.
Definition queued.hh:69
void startTranslation(BaseMMU *mmu)
Issues the translation request to the provided MMU.
Definition queued.cc:80
void setTranslationRequest(const RequestPtr &req)
Sets the translation request needed to obtain the physical address of this request.
Definition queued.hh:126
void createPkt(Addr paddr, unsigned blk_size, RequestorID requestor_id, bool tag_prefetch, Tick t)
Create the associated memory packet.
Definition queued.cc:58
void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override
Definition queued.cc:91
PacketPtr pkt
The memory packet generated by this prefetch.
Definition queued.hh:71
PrefetchInfo pfInfo
Prefetch info corresponding to this packet.
Definition queued.hh:67
statistics::Scalar pfUsefulSpanPage
Definition queued.hh:189
statistics::Scalar pfBufferHit
Definition queued.hh:184
statistics::Scalar pfIdentified
Definition queued.hh:183
statistics::Scalar pfRemovedDemand
Definition queued.hh:186
statistics::Scalar pfRemovedFull
Definition queued.hh:187
statistics::Scalar pfSpanPage
Definition queued.hh:188
QueuedStats(statistics::Group *parent)
Definition queued.cc:266

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