gem5  v22.1.0.0
queued.cc
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37 
39 
40 #include <cassert>
41 
42 #include "arch/generic/tlb.hh"
43 #include "base/logging.hh"
44 #include "base/trace.hh"
45 #include "debug/HWPrefetch.hh"
46 #include "debug/HWPrefetchQueue.hh"
47 #include "mem/cache/base.hh"
48 #include "mem/request.hh"
49 #include "params/QueuedPrefetcher.hh"
50 
51 namespace gem5
52 {
53 
55 namespace prefetch
56 {
57 
58 void
59 Queued::DeferredPacket::createPkt(Addr paddr, unsigned blk_size,
60  RequestorID requestor_id,
61  bool tag_prefetch,
62  Tick t) {
63  /* Create a prefetch memory request */
64  RequestPtr req = std::make_shared<Request>(paddr, blk_size,
65  0, requestor_id);
66 
67  if (pfInfo.isSecure()) {
68  req->setFlags(Request::SECURE);
69  }
71  pkt = new Packet(req, MemCmd::HardPFReq);
72  pkt->allocate();
73  if (tag_prefetch && pfInfo.hasPC()) {
74  // Tag prefetch packet with accessing pc
75  pkt->req->setPC(pfInfo.getPC());
76  }
77  tick = t;
78 }
79 
80 void
82 {
83  assert(translationRequest != nullptr);
84  if (!ongoingTranslation) {
85  ongoingTranslation = true;
86  // Prefetchers only operate in Timing mode
87  tlb->translateTiming(translationRequest, tc, this, BaseMMU::Read);
88  }
89 }
90 
91 void
93  const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode)
94 {
95  assert(ongoingTranslation);
96  ongoingTranslation = false;
97  bool failed = (fault != NoFault);
98  owner->translationComplete(this, failed);
99 }
100 
101 Queued::Queued(const QueuedPrefetcherParams &p)
102  : Base(p), queueSize(p.queue_size),
104  p.max_prefetch_requests_with_pending_translation),
105  latency(p.latency), queueSquash(p.queue_squash),
106  queueFilter(p.queue_filter), cacheSnoop(p.cache_snoop),
107  tagPrefetch(p.tag_prefetch),
108  throttleControlPct(p.throttle_control_percentage), statsQueued(this)
109 {
110 }
111 
113 {
114  // Delete the queued prefetch packets
115  for (DeferredPacket &p : pfq) {
116  delete p.pkt;
117  }
118 }
119 
120 void
122 {
123  int pos = 0;
124  std::string queue_name = "";
125  if (&queue == &pfq) {
126  queue_name = "PFQ";
127  } else {
128  assert(&queue == &pfqMissingTranslation);
129  queue_name = "PFTransQ";
130  }
131 
132  for (const_iterator it = queue.cbegin(); it != queue.cend();
133  it++, pos++) {
134  Addr vaddr = it->pfInfo.getAddr();
135  /* Set paddr to 0 if not yet translated */
136  Addr paddr = it->pkt ? it->pkt->getAddr() : 0;
137  DPRINTF(HWPrefetchQueue, "%s[%d]: Prefetch Req VA: %#x PA: %#x "
138  "prio: %3d\n", queue_name, pos, vaddr, paddr, it->priority);
139  }
140 }
141 
142 size_t
144 {
161  size_t max_pfs = total;
162  if (total > 0 && issuedPrefetches > 0) {
163  size_t throttle_pfs = (total * throttleControlPct) / 100;
164  size_t min_pfs = (total - throttle_pfs) == 0 ?
165  1 : (total - throttle_pfs);
166  max_pfs = min_pfs + (total - min_pfs) *
168  }
169  return max_pfs;
170 }
171 
172 void
173 Queued::notify(const PacketPtr &pkt, const PrefetchInfo &pfi)
174 {
175  Addr blk_addr = blockAddress(pfi.getAddr());
176  bool is_secure = pfi.isSecure();
177 
178  // Squash queued prefetches if demand miss to same line
179  if (queueSquash) {
180  auto itr = pfq.begin();
181  while (itr != pfq.end()) {
182  if (itr->pfInfo.getAddr() == blk_addr &&
183  itr->pfInfo.isSecure() == is_secure) {
184  DPRINTF(HWPrefetch, "Removing pf candidate addr: %#x "
185  "(cl: %#x), demand request going to the same addr\n",
186  itr->pfInfo.getAddr(),
187  blockAddress(itr->pfInfo.getAddr()));
188  delete itr->pkt;
189  itr = pfq.erase(itr);
191  } else {
192  ++itr;
193  }
194  }
195  }
196 
197  // Calculate prefetches given this access
198  std::vector<AddrPriority> addresses;
199  calculatePrefetch(pfi, addresses);
200 
201  // Get the maximu number of prefetches that we are allowed to generate
202  size_t max_pfs = getMaxPermittedPrefetches(addresses.size());
203 
204  // Queue up generated prefetches
205  size_t num_pfs = 0;
206  for (AddrPriority& addr_prio : addresses) {
207 
208  // Block align prefetch address
209  addr_prio.first = blockAddress(addr_prio.first);
210 
211  if (!samePage(addr_prio.first, pfi.getAddr())) {
212  statsQueued.pfSpanPage += 1;
213 
214  if (hasBeenPrefetched(pkt->getAddr(), pkt->isSecure())) {
216  }
217  }
218 
219  bool can_cross_page = (tlb != nullptr);
220  if (can_cross_page || samePage(addr_prio.first, pfi.getAddr())) {
221  PrefetchInfo new_pfi(pfi,addr_prio.first);
223  DPRINTF(HWPrefetch, "Found a pf candidate addr: %#x, "
224  "inserting into prefetch queue.\n", new_pfi.getAddr());
225  // Create and insert the request
226  insert(pkt, new_pfi, addr_prio.second);
227  num_pfs += 1;
228  if (num_pfs == max_pfs) {
229  break;
230  }
231  } else {
232  DPRINTF(HWPrefetch, "Ignoring page crossing prefetch.\n");
233  }
234  }
235 }
236 
237 PacketPtr
239 {
240  DPRINTF(HWPrefetch, "Requesting a prefetch to issue.\n");
241 
242  if (pfq.empty()) {
243  // If the queue is empty, attempt first to fill it with requests
244  // from the queue of missing translations
246  }
247 
248  if (pfq.empty()) {
249  DPRINTF(HWPrefetch, "No hardware prefetches available.\n");
250  return nullptr;
251  }
252 
253  PacketPtr pkt = pfq.front().pkt;
254  pfq.pop_front();
255 
257  issuedPrefetches += 1;
258  assert(pkt != nullptr);
259  DPRINTF(HWPrefetch, "Generating prefetch for %#x.\n", pkt->getAddr());
260 
262  return pkt;
263 }
264 
266  : statistics::Group(parent),
267  ADD_STAT(pfIdentified, statistics::units::Count::get(),
268  "number of prefetch candidates identified"),
269  ADD_STAT(pfBufferHit, statistics::units::Count::get(),
270  "number of redundant prefetches already in prefetch queue"),
271  ADD_STAT(pfInCache, statistics::units::Count::get(),
272  "number of redundant prefetches already in cache/mshr dropped"),
273  ADD_STAT(pfRemovedDemand, statistics::units::Count::get(),
274  "number of prefetches dropped due to a demand for the same "
275  "address"),
276  ADD_STAT(pfRemovedFull, statistics::units::Count::get(),
277  "number of prefetches dropped due to prefetch queue size"),
278  ADD_STAT(pfSpanPage, statistics::units::Count::get(),
279  "number of prefetches that crossed the page"),
280  ADD_STAT(pfUsefulSpanPage, statistics::units::Count::get(),
281  "number of prefetches that is useful and crossed the page")
282 {
283 }
284 
285 
286 void
288 {
289  unsigned count = 0;
290  iterator it = pfqMissingTranslation.begin();
291  while (it != pfqMissingTranslation.end() && count < max) {
292  DeferredPacket &dp = *it;
293  // Increase the iterator first because dp.startTranslation can end up
294  // calling finishTranslation, which will erase "it"
295  it++;
296  dp.startTranslation(tlb);
297  count += 1;
298  }
299 }
300 
301 void
303 {
304  auto it = pfqMissingTranslation.begin();
305  while (it != pfqMissingTranslation.end()) {
306  if (&(*it) == dp) {
307  break;
308  }
309  it++;
310  }
311  assert(it != pfqMissingTranslation.end());
312  if (!failed) {
313  DPRINTF(HWPrefetch, "%s Translation of vaddr %#x succeeded: "
314  "paddr %#x \n", tlb->name(),
315  it->translationRequest->getVaddr(),
316  it->translationRequest->getPaddr());
317  Addr target_paddr = it->translationRequest->getPaddr();
318  // check if this prefetch is already redundant
319  if (cacheSnoop && (inCache(target_paddr, it->pfInfo.isSecure()) ||
320  inMissQueue(target_paddr, it->pfInfo.isSecure()))) {
322  DPRINTF(HWPrefetch, "Dropping redundant in "
323  "cache/MSHR prefetch addr:%#x\n", target_paddr);
324  } else {
325  Tick pf_time = curTick() + clockPeriod() * latency;
326  it->createPkt(target_paddr, blkSize, requestorId, tagPrefetch,
327  pf_time);
328  addToQueue(pfq, *it);
329  }
330  } else {
331  DPRINTF(HWPrefetch, "%s Translation of vaddr %#x failed, dropping "
332  "prefetch request %#x \n", tlb->name(),
333  it->translationRequest->getVaddr());
334  }
335  pfqMissingTranslation.erase(it);
336 }
337 
338 bool
340  const PrefetchInfo &pfi, int32_t priority)
341 {
342  bool found = false;
343  iterator it;
344  for (it = queue.begin(); it != queue.end() && !found; it++) {
345  found = it->pfInfo.sameAddr(pfi);
346  }
347 
348  /* If the address is already in the queue, update priority and leave */
349  if (it != queue.end()) {
351  if (it->priority < priority) {
352  /* Update priority value and position in the queue */
353  it->priority = priority;
354  iterator prev = it;
355  while (prev != queue.begin()) {
356  prev--;
357  /* If the packet has higher priority, swap */
358  if (*it > *prev) {
359  std::swap(*it, *prev);
360  it = prev;
361  }
362  }
363  DPRINTF(HWPrefetch, "Prefetch addr already in "
364  "prefetch queue, priority updated\n");
365  } else {
366  DPRINTF(HWPrefetch, "Prefetch addr already in "
367  "prefetch queue\n");
368  }
369  }
370  return found;
371 }
372 
375  PacketPtr pkt)
376 {
377  RequestPtr translation_req = std::make_shared<Request>(
378  addr, blkSize, pkt->req->getFlags(), requestorId, pfi.getPC(),
379  pkt->req->contextId());
380  translation_req->setFlags(Request::PREFETCH);
381  return translation_req;
382 }
383 
384 void
385 Queued::insert(const PacketPtr &pkt, PrefetchInfo &new_pfi,
386  int32_t priority)
387 {
388  if (queueFilter) {
389  if (alreadyInQueue(pfq, new_pfi, priority)) {
390  return;
391  }
392  if (alreadyInQueue(pfqMissingTranslation, new_pfi, priority)) {
393  return;
394  }
395  }
396 
397  /*
398  * Physical address computation
399  * if the prefetch is within the same page
400  * using VA: add the computed stride to the original PA
401  * using PA: no actions needed
402  * if we are page crossing
403  * using VA: Create a translaion request and enqueue the corresponding
404  * deferred packet to the queue of pending translations
405  * using PA: use the provided VA to obtain the target VA, then attempt to
406  * translate the resulting address
407  */
408 
409  Addr orig_addr = useVirtualAddresses ?
410  pkt->req->getVaddr() : pkt->req->getPaddr();
411  bool positive_stride = new_pfi.getAddr() >= orig_addr;
412  Addr stride = positive_stride ?
413  (new_pfi.getAddr() - orig_addr) : (orig_addr - new_pfi.getAddr());
414 
415  Addr target_paddr;
416  bool has_target_pa = false;
417  RequestPtr translation_req = nullptr;
418  if (samePage(orig_addr, new_pfi.getAddr())) {
419  if (useVirtualAddresses) {
420  // if we trained with virtual addresses,
421  // compute the target PA using the original PA and adding the
422  // prefetch stride (difference between target VA and original VA)
423  target_paddr = positive_stride ? (pkt->req->getPaddr() + stride) :
424  (pkt->req->getPaddr() - stride);
425  } else {
426  target_paddr = new_pfi.getAddr();
427  }
428  has_target_pa = true;
429  } else {
430  // Page crossing reference
431 
432  // ContextID is needed for translation
433  if (!pkt->req->hasContextId()) {
434  return;
435  }
436  if (useVirtualAddresses) {
437  has_target_pa = false;
438  translation_req = createPrefetchRequest(new_pfi.getAddr(), new_pfi,
439  pkt);
440  } else if (pkt->req->hasVaddr()) {
441  has_target_pa = false;
442  // Compute the target VA using req->getVaddr + stride
443  Addr target_vaddr = positive_stride ?
444  (pkt->req->getVaddr() + stride) :
445  (pkt->req->getVaddr() - stride);
446  translation_req = createPrefetchRequest(target_vaddr, new_pfi,
447  pkt);
448  } else {
449  // Using PA for training but the request does not have a VA,
450  // unable to process this page crossing prefetch.
451  return;
452  }
453  }
454  if (has_target_pa && cacheSnoop &&
455  (inCache(target_paddr, new_pfi.isSecure()) ||
456  inMissQueue(target_paddr, new_pfi.isSecure()))) {
458  DPRINTF(HWPrefetch, "Dropping redundant in "
459  "cache/MSHR prefetch addr:%#x\n", target_paddr);
460  return;
461  }
462 
463  /* Create the packet and find the spot to insert it */
464  DeferredPacket dpp(this, new_pfi, 0, priority);
465  if (has_target_pa) {
466  Tick pf_time = curTick() + clockPeriod() * latency;
467  dpp.createPkt(target_paddr, blkSize, requestorId, tagPrefetch,
468  pf_time);
469  DPRINTF(HWPrefetch, "Prefetch queued. "
470  "addr:%#x priority: %3d tick:%lld.\n",
471  new_pfi.getAddr(), priority, pf_time);
472  addToQueue(pfq, dpp);
473  } else {
474  // Add the translation request and try to resolve it later
475  dpp.setTranslationRequest(translation_req);
476  dpp.tc = cache->system->threads[translation_req->contextId()];
477  DPRINTF(HWPrefetch, "Prefetch queued with no translation. "
478  "addr:%#x priority: %3d\n", new_pfi.getAddr(), priority);
480  }
481 }
482 
483 void
485  DeferredPacket &dpp)
486 {
487  /* Verify prefetch buffer space for request */
488  if (queue.size() == queueSize) {
490  /* Lowest priority packet */
491  iterator it = queue.end();
492  panic_if (it == queue.begin(),
493  "Prefetch queue is both full and empty!");
494  --it;
495  /* Look for oldest in that level of priority */
496  panic_if (it == queue.begin(),
497  "Prefetch queue is full with 1 element!");
498  iterator prev = it;
499  bool cont = true;
500  /* While not at the head of the queue */
501  while (cont && prev != queue.begin()) {
502  prev--;
503  /* While at the same level of priority */
504  cont = prev->priority == it->priority;
505  if (cont)
506  /* update pointer */
507  it = prev;
508  }
509  DPRINTF(HWPrefetch, "Prefetch queue full, removing lowest priority "
510  "oldest packet, addr: %#x\n",it->pfInfo.getAddr());
511  delete it->pkt;
512  queue.erase(it);
513  }
514 
515  if ((queue.size() == 0) || (dpp <= queue.back())) {
516  queue.emplace_back(dpp);
517  } else {
518  iterator it = queue.end();
519  do {
520  --it;
521  } while (it != queue.begin() && dpp > *it);
522  /* If we reach the head, we have to see if the new element is new head
523  * or not */
524  if (it == queue.begin() && dpp <= *it)
525  it++;
526  queue.insert(it, dpp);
527  }
528 
529  if (debug::HWPrefetchQueue)
530  printQueue(queue);
531 }
532 
533 } // namespace prefetch
534 } // namespace gem5
#define DPRINTF(x,...)
Definition: trace.hh:186
System * system
System we are currently operating in.
Definition: base.hh:986
virtual void translateTiming(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode)=0
Tick clockPeriod() const
virtual std::string name() const
Definition: named.hh:47
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:294
bool isSecure() const
Definition: packet.hh:834
Addr getAddr() const
Definition: packet.hh:805
RequestPtr req
A pointer to the original request.
Definition: packet.hh:376
void allocate()
Allocate memory for the packet.
Definition: packet.hh:1354
@ SECURE
The request targets the secure memory space.
Definition: request.hh:186
@ PREFETCH
The request is a prefetch.
Definition: request.hh:164
Threads threads
Definition: system.hh:313
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Class containing the information needed by the prefetch to train and generate new prefetch requests.
Definition: base.hh:98
Addr getPC() const
Returns the program counter that generated this request.
Definition: base.hh:143
bool isSecure() const
Returns true if the address targets the secure memory space.
Definition: base.hh:134
Addr getAddr() const
Obtains the address value of this Prefetcher address.
Definition: base.hh:125
bool hasPC() const
Returns true if the associated program counter is valid.
Definition: base.hh:153
const bool useVirtualAddresses
Use Virtual Addresses for prefetching.
Definition: base.hh:302
unsigned blkSize
The block size of the parent cache.
Definition: base.hh:270
uint64_t issuedPrefetches
Total prefetches issued.
Definition: base.hh:363
bool inCache(Addr addr, bool is_secure) const
Determine if address is in cache.
Definition: base.cc:189
const RequestorID requestorId
Request id for prefetches.
Definition: base.hh:291
BaseTLB * tlb
Registered tlb for address translations.
Definition: base.hh:368
bool inMissQueue(Addr addr, bool is_secure) const
Determine if address is in cache miss queue.
Definition: base.cc:195
bool hasBeenPrefetched(Addr addr, bool is_secure) const
Definition: base.cc:201
uint64_t usefulPrefetches
Total prefetches that has been useful.
Definition: base.hh:365
gem5::prefetch::Base::StatGroup prefetchStats
BaseCache * cache
Pointr to the parent cache.
Definition: base.hh:267
Addr blockAddress(Addr a) const
Determine the address of the block in which a lays.
Definition: base.cc:213
bool samePage(Addr a, Addr b) const
Determine if addresses are on the same page.
Definition: base.cc:207
const bool queueSquash
Squash queued prefetch if demand access observed.
Definition: queued.hh:164
void translationComplete(DeferredPacket *dp, bool failed)
Indicates that the translation of the address of the provided deferred packet has been successfully c...
Definition: queued.cc:302
gem5::prefetch::Queued::QueuedStats statsQueued
std::list< DeferredPacket >::iterator iterator
Definition: queued.hh:147
Queued(const QueuedPrefetcherParams &p)
Definition: queued.cc:101
void printQueue(const std::list< DeferredPacket > &queue) const
Definition: queued.cc:121
const unsigned queueSize
Maximum size of the prefetch queue.
Definition: queued.hh:152
std::list< DeferredPacket > pfqMissingTranslation
Definition: queued.hh:144
void processMissingTranslations(unsigned max)
Starts the translations of the queued prefetches with a missing translation.
Definition: queued.cc:287
RequestPtr createPrefetchRequest(Addr addr, PrefetchInfo const &pfi, PacketPtr pkt)
Definition: queued.cc:374
void notify(const PacketPtr &pkt, const PrefetchInfo &pfi) override
Notify prefetcher of cache access (may be any access or just misses, depending on cache parameters....
Definition: queued.cc:173
const bool queueFilter
Filter prefetches if already queued.
Definition: queued.hh:167
std::list< DeferredPacket >::const_iterator const_iterator
Definition: queued.hh:146
const bool tagPrefetch
Tag prefetch with PC of generating access?
Definition: queued.hh:173
const Cycles latency
Cycles after generation when a prefetch can first be issued.
Definition: queued.hh:161
const bool cacheSnoop
Snoop the cache before generating prefetch (cheating basically)
Definition: queued.hh:170
const unsigned int throttleControlPct
Percentage of requests that can be throttled.
Definition: queued.hh:176
void insert(const PacketPtr &pkt, PrefetchInfo &new_pfi, int32_t priority)
Definition: queued.cc:385
PacketPtr getPacket() override
Definition: queued.cc:238
void addToQueue(std::list< DeferredPacket > &queue, DeferredPacket &dpp)
Adds a DeferredPacket to the specified queue.
Definition: queued.cc:484
bool alreadyInQueue(std::list< DeferredPacket > &queue, const PrefetchInfo &pfi, int32_t priority)
Checks whether the specified prefetch request is already in the specified queue.
Definition: queued.cc:339
size_t getMaxPermittedPrefetches(size_t total) const
Returns the maxmimum number of prefetch requests that are allowed to be created from the number of pr...
Definition: queued.cc:143
virtual void calculatePrefetch(const PrefetchInfo &pfi, std::vector< AddrPriority > &addresses)=0
const unsigned missingTranslationQueueSize
Maximum size of the queue holding prefetch requests with missing address translations.
Definition: queued.hh:158
std::list< DeferredPacket > pfq
Definition: queued.hh:143
Statistics container.
Definition: group.hh:94
STL pair class.
Definition: stl.hh:58
STL vector class.
Definition: stl.hh:37
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
Definition: group.hh:75
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:204
Declares a basic cache interface BaseCache.
Bitfield< 4, 0 > mode
Definition: misc_types.hh:74
Bitfield< 47, 44 > dp
Definition: misc_types.hh:95
Bitfield< 21, 20 > stride
Definition: misc_types.hh:453
Bitfield< 51 > t
Definition: pagetable.hh:56
Bitfield< 54 > p
Definition: pagetable.hh:70
Bitfield< 3 > addr
Definition: types.hh:84
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:109
const FlagsType total
Print the total.
Definition: info.hh:60
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
uint64_t Tick
Tick count type.
Definition: types.hh:58
uint16_t RequestorID
Definition: request.hh:95
constexpr decltype(nullptr) NoFault
Definition: types.hh:253
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
Declaration of a request, the overall memory request consisting of the parts of the request that are ...
statistics::Scalar pfIssued
Definition: base.hh:335
Tick tick
Time when this prefetch becomes ready.
Definition: queued.hh:70
void startTranslation(BaseTLB *tlb)
Issues the translation request to the provided TLB.
Definition: queued.cc:81
void setTranslationRequest(const RequestPtr &req)
Sets the translation request needed to obtain the physical address of this request.
Definition: queued.hh:125
void createPkt(Addr paddr, unsigned blk_size, RequestorID requestor_id, bool tag_prefetch, Tick t)
Create the associated memory packet.
Definition: queued.cc:59
void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override
Definition: queued.cc:92
PacketPtr pkt
The memory packet generated by this prefetch.
Definition: queued.hh:72
PrefetchInfo pfInfo
Prefetch info corresponding to this packet.
Definition: queued.hh:68
statistics::Scalar pfUsefulSpanPage
Definition: queued.hh:188
statistics::Scalar pfBufferHit
Definition: queued.hh:183
statistics::Scalar pfIdentified
Definition: queued.hh:182
statistics::Scalar pfRemovedDemand
Definition: queued.hh:185
statistics::Scalar pfRemovedFull
Definition: queued.hh:186
statistics::Scalar pfSpanPage
Definition: queued.hh:187
statistics::Scalar pfInCache
Definition: queued.hh:184
QueuedStats(statistics::Group *parent)
Definition: queued.cc:265

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