gem5 v24.0.0.0
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remote_gdb.cc
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1/*
2 * Copyright (c) 2021 Huawei International
3 * Copyright 2015 LabWare
4 * Copyright 2014 Google, Inc.
5 * Copyright (c) 2010 ARM Limited
6 * Copyright (c) 2020 Barkhausen Institut
7 * All rights reserved
8 *
9 * The license below extends only to copyright in the software and shall
10 * not be construed as granting a license to any other intellectual
11 * property including but not limited to intellectual property relating
12 * to a hardware implementation of the functionality of the software
13 * licensed hereunder. You may use the software subject to the license
14 * terms below provided that you ensure that this notice is replicated
15 * unmodified and in its entirety in all distributions of the software,
16 * modified or unmodified, in source code or in binary form.
17 *
18 * Copyright (c) 2017 The University of Virginia
19 * Copyright (c) 2002-2005 The Regents of The University of Michigan
20 * All rights reserved.
21 *
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions are
24 * met: redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer;
26 * redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in the
28 * documentation and/or other materials provided with the distribution;
29 * neither the name of the copyright holders nor the names of its
30 * contributors may be used to endorse or promote products derived from
31 * this software without specific prior written permission.
32 *
33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
34 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
35 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
36 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
37 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
38 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
39 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
40 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
41 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
42 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
43 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 */
45
46/*
47 * Copyright (c) 1990, 1993 The Regents of the University of California
48 * All rights reserved
49 *
50 * This software was developed by the Computer Systems Engineering group
51 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
52 * contributed to Berkeley.
53 *
54 * All advertising materials mentioning features or use of this software
55 * must display the following acknowledgement:
56 * This product includes software developed by the University of
57 * California, Lawrence Berkeley Laboratories.
58 *
59 * Redistribution and use in source and binary forms, with or without
60 * modification, are permitted provided that the following conditions
61 * are met:
62 * 1. Redistributions of source code must retain the above copyright
63 * notice, this list of conditions and the following disclaimer.
64 * 2. Redistributions in binary form must reproduce the above copyright
65 * notice, this list of conditions and the following disclaimer in the
66 * documentation and/or other materials provided with the distribution.
67 * 3. All advertising materials mentioning features or use of this software
68 * must display the following acknowledgement:
69 * This product includes software developed by the University of
70 * California, Berkeley and its contributors.
71 * 4. Neither the name of the University nor the names of its contributors
72 * may be used to endorse or promote products derived from this software
73 * without specific prior written permission.
74 *
75 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
76 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
77 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
78 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
79 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
80 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
81 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
82 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
83 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
84 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
85 * SUCH DAMAGE.
86 *
87 * @(#)kgdb_stub.c 8.4 (Berkeley) 1/12/94
88 */
89
90/*-
91 * Copyright (c) 2001 The NetBSD Foundation, Inc.
92 * All rights reserved.
93 *
94 * This code is derived from software contributed to The NetBSD Foundation
95 * by Jason R. Thorpe.
96 *
97 * Redistribution and use in source and binary forms, with or without
98 * modification, are permitted provided that the following conditions
99 * are met:
100 * 1. Redistributions of source code must retain the above copyright
101 * notice, this list of conditions and the following disclaimer.
102 * 2. Redistributions in binary form must reproduce the above copyright
103 * notice, this list of conditions and the following disclaimer in the
104 * documentation and/or other materials provided with the distribution.
105 * 3. All advertising materials mentioning features or use of this software
106 * must display the following acknowledgement:
107 * This product includes software developed by the NetBSD
108 * Foundation, Inc. and its contributors.
109 * 4. Neither the name of The NetBSD Foundation nor the names of its
110 * contributors may be used to endorse or promote products derived
111 * from this software without specific prior written permission.
112 *
113 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
114 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
115 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
116 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
117 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
118 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
119 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
120 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
121 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
122 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
123 * POSSIBILITY OF SUCH DAMAGE.
124 */
125
126/*
127 * $NetBSD: kgdb_stub.c,v 1.8 2001/07/07 22:58:00 wdk Exp $
128 *
129 * Taken from NetBSD
130 *
131 * "Stub" to allow remote cpu to debug over a serial line using gdb.
132 */
133
134#include "arch/riscv/remote_gdb.hh"
135
136#include <string>
137
138#include "arch/riscv/gdb-xml/gdb_xml_riscv_32bit_cpu.hh"
139#include "arch/riscv/gdb-xml/gdb_xml_riscv_32bit_csr.hh"
140#include "arch/riscv/gdb-xml/gdb_xml_riscv_32bit_fpu.hh"
141#include "arch/riscv/gdb-xml/gdb_xml_riscv_32bit_target.hh"
142#include "arch/riscv/gdb-xml/gdb_xml_riscv_64bit_cpu.hh"
143#include "arch/riscv/gdb-xml/gdb_xml_riscv_64bit_csr.hh"
144#include "arch/riscv/gdb-xml/gdb_xml_riscv_64bit_fpu.hh"
145#include "arch/riscv/gdb-xml/gdb_xml_riscv_64bit_target.hh"
146#include "arch/riscv/mmu.hh"
147#include "arch/riscv/pagetable_walker.hh"
148#include "arch/riscv/regs/float.hh"
149#include "arch/riscv/regs/int.hh"
150#include "arch/riscv/regs/misc.hh"
151#include "arch/riscv/tlb.hh"
152#include "cpu/thread_state.hh"
153#include "debug/GDBAcc.hh"
154#include "mem/page_table.hh"
155#include "sim/full_system.hh"
156
157namespace gem5
158{
159
160using namespace RiscvISA;
161
162static RiscvType
163getRvType(ThreadContext* tc)
164{
165 auto isa = dynamic_cast<ISA*>(tc->getIsaPtr());
166 panic_if(!isa, "Cannot derive rv_type from non-riscv isa");
167 return isa->rvType();
168}
169
170static PrivilegeModeSet
171getPrivilegeModeSet(ThreadContext* tc)
172{
173 auto isa = dynamic_cast<ISA*>(tc->getIsaPtr());
174 panic_if(!isa, "Cannot derive rv_type from non-riscv isa");
175 return isa->getPrivilegeModeSet();
176}
177
178template <typename xint>
179static void
180setRegNoEffectWithMask(
181 ThreadContext *context, RiscvType type, PrivilegeModeSet pms,
182 CSRIndex idx, xint val)
183{
184 RegVal oldVal, newVal;
185 RegVal mask = CSRMasks[type][pms].at(idx);
186 oldVal = context->readMiscRegNoEffect(CSRData.at(idx).physIndex);
187 newVal = (oldVal & ~mask) | (val & mask);
188 context->setMiscRegNoEffect(CSRData.at(idx).physIndex, newVal);
189}
190
191template <typename xint>
192static void
193setRegWithMask(
194 ThreadContext *context, RiscvType type, PrivilegeModeSet pms,
195 CSRIndex idx, xint val)
196{
197 RegVal oldVal, newVal;
198 RegVal mask = CSRMasks[type][pms].at(idx);
199 oldVal = context->readMiscReg(CSRData.at(idx).physIndex);
200 newVal = (oldVal & ~mask) | (val & mask);
201 context->setMiscReg(CSRData.at(idx).physIndex, newVal);
202}
203
204RemoteGDB::RemoteGDB(System *_system, ListenSocketConfig _listen_config)
205 : BaseRemoteGDB(_system, _listen_config),
206 regCache32(this), regCache64(this)
207{
208}
209
210bool
211RemoteGDB::acc(Addr va, size_t len)
212{
213 if (FullSystem)
214 {
215 MMU *mmu = static_cast<MMU *>(context()->getMMUPtr());
216 unsigned logBytes;
217 Addr paddr = va;
218
219 PrivilegeMode pmode = mmu->getMemPriv(context(), BaseMMU::Read);
220 SATP satp = context()->readMiscReg(MISCREG_SATP);
221 MISA misa = tc->readMiscRegNoEffect(MISCREG_ISA);
222 if (misa.rvs && pmode != PrivilegeMode::PRV_M &&
223 satp.mode != AddrXlateMode::BARE) {
224 Walker *walker = mmu->getDataWalker();
225 Fault fault = walker->startFunctional(
226 context(), paddr, logBytes, BaseMMU::Read);
227 if (fault != NoFault)
228 return false;
229 }
230 return true;
231 }
232
233 return context()->getProcessPtr()->pTable->lookup(va) != nullptr;
234}
235
236void
237RemoteGDB::Riscv32GdbRegCache::getRegs(ThreadContext *context)
238{
239 DPRINTF(GDBAcc, "getregs in remotegdb, size %lu\n", size());
240 PrivilegeModeSet pms = getPrivilegeModeSet(context);
241 auto& RVxCSRMasks = CSRMasks[RV32][pms];
242
243 // General registers
244 for (int i = 0; i < int_reg::NumArchRegs; i++) {
245 r.gpr[i] = context->getReg(intRegClass[i]);
246 }
247 r.pc = context->pcState().instAddr();
248
249 // Floating point registers
250 for (int i = 0; i < float_reg::NumRegs; i++)
251 r.fpu[i] = context->getReg(floatRegClass[i]);
252 r.fflags = context->readMiscRegNoEffect(
253 CSRData.at(CSR_FFLAGS).physIndex) & RVxCSRMasks.at(CSR_FFLAGS);
254 r.frm = context->readMiscRegNoEffect(
255 CSRData.at(CSR_FRM).physIndex) & RVxCSRMasks.at(CSR_FRM);
256 r.fcsr = context->readMiscReg(
257 CSRData.at(CSR_FCSR).physIndex) & RVxCSRMasks.at(CSR_FCSR);
258
259 // CSR registers
260 r.cycle = context->readMiscRegNoEffect(
261 CSRData.at(CSR_CYCLE).physIndex);
262 r.cycleh = context->readMiscRegNoEffect(
263 CSRData.at(CSR_CYCLEH).physIndex);
264 r.time = context->readMiscRegNoEffect(
265 CSRData.at(CSR_TIME).physIndex);
266 r.timeh = context->readMiscRegNoEffect(
267 CSRData.at(CSR_TIMEH).physIndex);
268
269 // U mode CSR
270 r.ustatus = context->readMiscReg(
271 CSRData.at(CSR_USTATUS).physIndex) & RVxCSRMasks.at(CSR_USTATUS);
272 r.uie = context->readMiscReg(
273 CSRData.at(CSR_UIE).physIndex) & RVxCSRMasks.at(CSR_UIE);
274 r.utvec = context->readMiscRegNoEffect(
275 CSRData.at(CSR_UTVEC).physIndex);
276 r.uscratch = context->readMiscRegNoEffect(
277 CSRData.at(CSR_USCRATCH).physIndex);
278 r.uepc = context->readMiscRegNoEffect(
279 CSRData.at(CSR_UEPC).physIndex);
280 r.ucause = context->readMiscRegNoEffect(
281 CSRData.at(CSR_UCAUSE).physIndex);
282 r.utval = context->readMiscRegNoEffect(
283 CSRData.at(CSR_UTVAL).physIndex);
284 r.uip = context->readMiscReg(
285 CSRData.at(CSR_UIP).physIndex) & RVxCSRMasks.at(CSR_UIP);
286
287 // S mode CSR
288 r.sstatus = context->readMiscReg(
289 CSRData.at(CSR_SSTATUS).physIndex) & RVxCSRMasks.at(CSR_SSTATUS);
290 r.sedeleg = context->readMiscRegNoEffect(
291 CSRData.at(CSR_SEDELEG).physIndex);
292 r.sideleg = context->readMiscRegNoEffect(
293 CSRData.at(CSR_SIDELEG).physIndex);
294 r.sie = context->readMiscReg(
295 CSRData.at(CSR_SIE).physIndex) & RVxCSRMasks.at(CSR_SIE);
296 r.stvec = context->readMiscRegNoEffect(
297 CSRData.at(CSR_STVEC).physIndex);
298 r.scounteren = context->readMiscRegNoEffect(
299 CSRData.at(CSR_SCOUNTEREN).physIndex);
300 r.sscratch = context->readMiscRegNoEffect(
301 CSRData.at(CSR_SSCRATCH).physIndex);
302 r.sepc = context->readMiscReg(
303 CSRData.at(CSR_SEPC).physIndex);
304 r.scause = context->readMiscRegNoEffect(
305 CSRData.at(CSR_SCAUSE).physIndex);
306 r.stval = context->readMiscRegNoEffect(
307 CSRData.at(CSR_STVAL).physIndex);
308 r.sip = context->readMiscReg(
309 CSRData.at(CSR_SIP).physIndex) & RVxCSRMasks.at(CSR_SIP);
310 r.satp = context->readMiscRegNoEffect(
311 CSRData.at(CSR_SATP).physIndex);
312
313 // M mode CSR
314 r.mvendorid = context->readMiscRegNoEffect(
315 CSRData.at(CSR_MVENDORID).physIndex);
316 r.marchid = context->readMiscRegNoEffect(
317 CSRData.at(CSR_MARCHID).physIndex);
318 r.mimpid = context->readMiscRegNoEffect(
319 CSRData.at(CSR_MIMPID).physIndex);
320 r.mhartid = context->contextId();
321 r.mstatus = context->readMiscReg(
322 CSRData.at(CSR_MSTATUS).physIndex) & RVxCSRMasks.at(CSR_MSTATUS);
323 r.misa = context->readMiscRegNoEffect(
324 CSRData.at(CSR_MISA).physIndex) & RVxCSRMasks.at(CSR_MISA);
325 r.medeleg = context->readMiscRegNoEffect(
326 CSRData.at(CSR_MEDELEG).physIndex);
327 r.mideleg = context->readMiscRegNoEffect(
328 CSRData.at(CSR_MIDELEG).physIndex);
329 r.mie = context->readMiscReg(
330 CSRData.at(CSR_MIE).physIndex) & RVxCSRMasks.at(CSR_MIE);
331 r.mtvec = context->readMiscRegNoEffect(
332 CSRData.at(CSR_MTVEC).physIndex);
333 r.mcounteren = context->readMiscRegNoEffect(
334 CSRData.at(CSR_MCOUNTEREN).physIndex);
335 r.mstatush = context->readMiscReg(
336 CSRData.at(CSR_MSTATUSH).physIndex) & RVxCSRMasks.at(CSR_MSTATUSH);
337 r.mscratch = context->readMiscRegNoEffect(
338 CSRData.at(CSR_MSCRATCH).physIndex);
339 r.mepc = context->readMiscReg(
340 CSRData.at(CSR_MEPC).physIndex);
341 r.mcause = context->readMiscRegNoEffect(
342 CSRData.at(CSR_MCAUSE).physIndex);
343 r.mtval = context->readMiscRegNoEffect(
344 CSRData.at(CSR_MTVAL).physIndex);
345 r.mip = context->readMiscReg(
346 CSRData.at(CSR_MIP).physIndex) & RVxCSRMasks.at(CSR_MIP);
347
348 // H mode CSR (to be implemented)
349}
350
351void
352RemoteGDB::Riscv32GdbRegCache::setRegs(ThreadContext *context) const
353{
354 DPRINTF(GDBAcc, "setregs in remotegdb \n");
355 PrivilegeModeSet pms = getPrivilegeModeSet(context);
356 for (int i = 0; i < int_reg::NumArchRegs; i++)
357 context->setReg(intRegClass[i], r.gpr[i]);
358 context->pcState(r.pc);
359
360 // Floating point registers
361 for (int i = 0; i < float_reg::NumRegs; i++)
362 context->setReg(floatRegClass[i], r.fpu[i]);
363
364 setRegNoEffectWithMask(context, RV32, pms, CSR_FFLAGS, r.fflags);
365 setRegNoEffectWithMask(context, RV32, pms, CSR_FRM, r.frm);
366 setRegWithMask(context, RV32, pms, CSR_FCSR, r.fcsr);
367
368 // TODO: implement CSR counter registers for mcycle(h), minstret(h)
369
370 // U mode CSR
371 setRegNoEffectWithMask(context, RV32, pms, CSR_USTATUS, r.ustatus);
372 setRegWithMask(context, RV32, pms, CSR_UIE, r.uie);
373 setRegWithMask(context, RV32, pms, CSR_UIP, r.uip);
374 context->setMiscRegNoEffect(
375 CSRData.at(CSR_UTVEC).physIndex, r.utvec);
376 context->setMiscRegNoEffect(
377 CSRData.at(CSR_USCRATCH).physIndex, r.uscratch);
378 context->setMiscRegNoEffect(
379 CSRData.at(CSR_UEPC).physIndex, r.uepc);
380 context->setMiscRegNoEffect(
381 CSRData.at(CSR_UCAUSE).physIndex, r.ucause);
382 context->setMiscRegNoEffect(
383 CSRData.at(CSR_UTVAL).physIndex, r.utval);
384
385 // S mode CSR
386 setRegNoEffectWithMask(context, RV32, pms, CSR_SSTATUS, r.sstatus);
387 setRegWithMask(context, RV32, pms, CSR_SIE, r.sie);
388 setRegWithMask(context, RV32, pms, CSR_SIP, r.sip);
389 context->setMiscRegNoEffect(
390 CSRData.at(CSR_SEDELEG).physIndex, r.sedeleg);
391 context->setMiscRegNoEffect(
392 CSRData.at(CSR_SIDELEG).physIndex, r.sideleg);
393 context->setMiscRegNoEffect(
394 CSRData.at(CSR_STVEC).physIndex, r.stvec);
395 context->setMiscRegNoEffect(
396 CSRData.at(CSR_SCOUNTEREN).physIndex, r.scounteren);
397 context->setMiscRegNoEffect(
398 CSRData.at(CSR_SSCRATCH).physIndex, r.sscratch);
399 context->setMiscRegNoEffect(
400 CSRData.at(CSR_SEPC).physIndex, r.sepc);
401 context->setMiscRegNoEffect(
402 CSRData.at(CSR_SCAUSE).physIndex, r.scause);
403 context->setMiscRegNoEffect(
404 CSRData.at(CSR_STVAL).physIndex, r.stval);
405 context->setMiscRegNoEffect(
406 CSRData.at(CSR_SATP).physIndex, r.satp);
407
408 // M mode CSR
409 setRegNoEffectWithMask(context, RV32, pms, CSR_MSTATUS, r.mstatus);
410 setRegNoEffectWithMask(context, RV32, pms, CSR_MISA, r.misa);
411 setRegWithMask(context, RV32, pms, CSR_MIE, r.mie);
412 setRegWithMask(context, RV32, pms, CSR_MIP, r.mip);
413 context->setMiscRegNoEffect(
414 CSRData.at(CSR_MEDELEG).physIndex, r.medeleg);
415 context->setMiscRegNoEffect(
416 CSRData.at(CSR_MIDELEG).physIndex, r.mideleg);
417 context->setMiscRegNoEffect(
418 CSRData.at(CSR_MTVEC).physIndex, r.mtvec);
419 context->setMiscRegNoEffect(
420 CSRData.at(CSR_MCOUNTEREN).physIndex, r.mcounteren);
421 context->setMiscRegNoEffect(
422 CSRData.at(CSR_MSCRATCH).physIndex, r.mscratch);
423 context->setMiscRegNoEffect(
424 CSRData.at(CSR_MEPC).physIndex, r.mepc);
425 context->setMiscRegNoEffect(
426 CSRData.at(CSR_MCAUSE).physIndex, r.mcause);
427 context->setMiscRegNoEffect(
428 CSRData.at(CSR_MTVAL).physIndex, r.mtval);
429
430 // H mode CSR (to be implemented)
431}
432
433void
434RemoteGDB::Riscv64GdbRegCache::getRegs(ThreadContext *context)
435{
436 DPRINTF(GDBAcc, "getregs in remotegdb, size %lu\n", size());
437 PrivilegeModeSet pms = getPrivilegeModeSet(context);
438 auto& RVxCSRMasks = CSRMasks[RV64][pms];
439
440 // General registers
441 for (int i = 0; i < int_reg::NumArchRegs; i++) {
442 r.gpr[i] = context->getReg(intRegClass[i]);
443 }
444 r.pc = context->pcState().instAddr();
445
446 // Floating point registers
447 for (int i = 0; i < float_reg::NumRegs; i++)
448 r.fpu[i] = context->getReg(floatRegClass[i]);
449 r.fflags = context->readMiscRegNoEffect(
450 CSRData.at(CSR_FFLAGS).physIndex) & RVxCSRMasks.at(CSR_FFLAGS);
451 r.frm = context->readMiscRegNoEffect(
452 CSRData.at(CSR_FRM).physIndex) & RVxCSRMasks.at(CSR_FRM);
453 r.fcsr = context->readMiscReg(
454 CSRData.at(CSR_FCSR).physIndex) & RVxCSRMasks.at(CSR_FCSR);
455
456 // CSR registers
457 r.cycle = context->readMiscRegNoEffect(
458 CSRData.at(CSR_CYCLE).physIndex);
459 r.time = context->readMiscRegNoEffect(
460 CSRData.at(CSR_TIME).physIndex);
461
462 // U mode CSR
463 r.ustatus = context->readMiscReg(
464 CSRData.at(CSR_USTATUS).physIndex) & RVxCSRMasks.at(CSR_USTATUS);
465 r.uie = context->readMiscReg(
466 CSRData.at(CSR_UIE).physIndex) & RVxCSRMasks.at(CSR_UIE);
467 r.utvec = context->readMiscRegNoEffect(
468 CSRData.at(CSR_UTVEC).physIndex);
469 r.uscratch = context->readMiscRegNoEffect(
470 CSRData.at(CSR_USCRATCH).physIndex);
471 r.uepc = context->readMiscRegNoEffect(
472 CSRData.at(CSR_UEPC).physIndex);
473 r.ucause = context->readMiscRegNoEffect(
474 CSRData.at(CSR_UCAUSE).physIndex);
475 r.utval = context->readMiscRegNoEffect(
476 CSRData.at(CSR_UTVAL).physIndex);
477 r.uip = context->readMiscReg(
478 CSRData.at(CSR_UIP).physIndex) & RVxCSRMasks.at(CSR_UIP);
479
480 // S mode CSR
481 r.sstatus = context->readMiscReg(
482 CSRData.at(CSR_SSTATUS).physIndex) & RVxCSRMasks.at(CSR_SSTATUS);
483 r.sedeleg = context->readMiscRegNoEffect(
484 CSRData.at(CSR_SEDELEG).physIndex);
485 r.sideleg = context->readMiscRegNoEffect(
486 CSRData.at(CSR_SIDELEG).physIndex);
487 r.sie = context->readMiscReg(
488 CSRData.at(CSR_SIE).physIndex) & RVxCSRMasks.at(CSR_SIE);
489 r.stvec = context->readMiscRegNoEffect(
490 CSRData.at(CSR_STVEC).physIndex);
491 r.scounteren = context->readMiscRegNoEffect(
492 CSRData.at(CSR_SCOUNTEREN).physIndex);
493 r.sscratch = context->readMiscRegNoEffect(
494 CSRData.at(CSR_SSCRATCH).physIndex);
495 r.sepc = context->readMiscReg(
496 CSRData.at(CSR_SEPC).physIndex);
497 r.scause = context->readMiscRegNoEffect(
498 CSRData.at(CSR_SCAUSE).physIndex);
499 r.stval = context->readMiscRegNoEffect(
500 CSRData.at(CSR_STVAL).physIndex);
501 r.sip = context->readMiscReg(
502 CSRData.at(CSR_SIP).physIndex) & RVxCSRMasks.at(CSR_SIP);
503 r.satp = context->readMiscRegNoEffect(
504 CSRData.at(CSR_SATP).physIndex);
505
506 // M mode CSR
507 r.mvendorid = context->readMiscRegNoEffect(
508 CSRData.at(CSR_MVENDORID).physIndex);
509 r.marchid = context->readMiscRegNoEffect(
510 CSRData.at(CSR_MARCHID).physIndex);
511 r.mimpid = context->readMiscRegNoEffect(
512 CSRData.at(CSR_MIMPID).physIndex);
513 r.mhartid = context->contextId();
514 r.mstatus = context->readMiscReg(
515 CSRData.at(CSR_MSTATUS).physIndex) & RVxCSRMasks.at(CSR_MSTATUS);
516 r.misa = context->readMiscRegNoEffect(
517 CSRData.at(CSR_MISA).physIndex) & RVxCSRMasks.at(CSR_MISA);
518 r.medeleg = context->readMiscRegNoEffect(
519 CSRData.at(CSR_MEDELEG).physIndex);
520 r.mideleg = context->readMiscRegNoEffect(
521 CSRData.at(CSR_MIDELEG).physIndex);
522 r.mie = context->readMiscReg(
523 CSRData.at(CSR_MIE).physIndex) & RVxCSRMasks.at(CSR_MIE);
524 r.mtvec = context->readMiscRegNoEffect(
525 CSRData.at(CSR_MTVEC).physIndex);
526 r.mcounteren = context->readMiscRegNoEffect(
527 CSRData.at(CSR_MCOUNTEREN).physIndex);
528 r.mscratch = context->readMiscRegNoEffect(
529 CSRData.at(CSR_MSCRATCH).physIndex);
530 r.mepc = context->readMiscReg(
531 CSRData.at(CSR_MEPC).physIndex);
532 r.mcause = context->readMiscRegNoEffect(
533 CSRData.at(CSR_MCAUSE).physIndex);
534 r.mtval = context->readMiscRegNoEffect(
535 CSRData.at(CSR_MTVAL).physIndex);
536 r.mip = context->readMiscReg(
537 CSRData.at(CSR_MIP).physIndex) & RVxCSRMasks.at(CSR_MIP);
538
539 // H mode CSR (to be implemented)
540}
541
542void
543RemoteGDB::Riscv64GdbRegCache::setRegs(ThreadContext *context) const
544{
545 DPRINTF(GDBAcc, "setregs in remotegdb \n");
546 PrivilegeModeSet pms = getPrivilegeModeSet(context);
547 for (int i = 0; i < int_reg::NumArchRegs; i++)
548 context->setReg(intRegClass[i], r.gpr[i]);
549 context->pcState(r.pc);
550
551 // Floating point registers
552 for (int i = 0; i < float_reg::NumRegs; i++)
553 context->setReg(floatRegClass[i], r.fpu[i]);
554
555 setRegNoEffectWithMask(context, RV64, pms, CSR_FFLAGS, r.fflags);
556 setRegNoEffectWithMask(context, RV64, pms, CSR_FRM, r.frm);
557 setRegWithMask(context, RV64, pms, CSR_FCSR, r.fcsr);
558
559 // TODO: implement CSR counter registers for mcycle, minstret
560
561 // U mode CSR
562 setRegNoEffectWithMask(context, RV64, pms, CSR_USTATUS, r.ustatus);
563 setRegWithMask(context, RV64, pms, CSR_UIE, r.uie);
564 setRegWithMask(context, RV64, pms, CSR_UIP, r.uip);
565 context->setMiscRegNoEffect(
566 CSRData.at(CSR_UTVEC).physIndex, r.utvec);
567 context->setMiscRegNoEffect(
568 CSRData.at(CSR_USCRATCH).physIndex, r.uscratch);
569 context->setMiscRegNoEffect(
570 CSRData.at(CSR_UEPC).physIndex, r.uepc);
571 context->setMiscRegNoEffect(
572 CSRData.at(CSR_UCAUSE).physIndex, r.ucause);
573 context->setMiscRegNoEffect(
574 CSRData.at(CSR_UTVAL).physIndex, r.utval);
575
576 // S mode CSR
577 setRegNoEffectWithMask(
578 context, RV64, pms, CSR_SSTATUS, r.sstatus);
579 setRegWithMask(context, RV64, pms, CSR_SIE, r.sie);
580 setRegWithMask(context, RV64, pms, CSR_SIP, r.sip);
581 context->setMiscRegNoEffect(
582 CSRData.at(CSR_SEDELEG).physIndex, r.sedeleg);
583 context->setMiscRegNoEffect(
584 CSRData.at(CSR_SIDELEG).physIndex, r.sideleg);
585 context->setMiscRegNoEffect(
586 CSRData.at(CSR_STVEC).physIndex, r.stvec);
587 context->setMiscRegNoEffect(
588 CSRData.at(CSR_SCOUNTEREN).physIndex, r.scounteren);
589 context->setMiscRegNoEffect(
590 CSRData.at(CSR_SSCRATCH).physIndex, r.sscratch);
591 context->setMiscRegNoEffect(
592 CSRData.at(CSR_SEPC).physIndex, r.sepc);
593 context->setMiscRegNoEffect(
594 CSRData.at(CSR_SCAUSE).physIndex, r.scause);
595 context->setMiscRegNoEffect(
596 CSRData.at(CSR_STVAL).physIndex, r.stval);
597 context->setMiscRegNoEffect(
598 CSRData.at(CSR_SATP).physIndex, r.satp);
599
600 // M mode CSR
601 setRegNoEffectWithMask(
602 context, RV64, pms, CSR_MSTATUS, r.mstatus);
603 setRegNoEffectWithMask(context, RV64, pms, CSR_MISA, r.misa);
604 setRegWithMask(context, RV64, pms, CSR_MIE, r.mie);
605 setRegWithMask(context, RV64, pms, CSR_MIP, r.mip);
606 context->setMiscRegNoEffect(
607 CSRData.at(CSR_MEDELEG).physIndex, r.medeleg);
608 context->setMiscRegNoEffect(
609 CSRData.at(CSR_MIDELEG).physIndex, r.mideleg);
610 context->setMiscRegNoEffect(
611 CSRData.at(CSR_MTVEC).physIndex, r.mtvec);
612 context->setMiscRegNoEffect(
613 CSRData.at(CSR_MCOUNTEREN).physIndex, r.mcounteren);
614 context->setMiscRegNoEffect(
615 CSRData.at(CSR_MSCRATCH).physIndex, r.mscratch);
616 context->setMiscRegNoEffect(
617 CSRData.at(CSR_MEPC).physIndex, r.mepc);
618 context->setMiscRegNoEffect(
619 CSRData.at(CSR_MCAUSE).physIndex, r.mcause);
620 context->setMiscRegNoEffect(
621 CSRData.at(CSR_MTVAL).physIndex, r.mtval);
622
623 // H mode CSR (to be implemented)
624}
625
626bool
627RemoteGDB::getXferFeaturesRead(const std::string &annex, std::string &output)
628{
635#define GDB_XML(x, s) \
636 { \
637 x, std::string(reinterpret_cast<const char *>(Blobs::s), \
638 Blobs::s##_len) \
639 }
640 static const std::map<std::string, std::string> annexMaps[enums::Num_RiscvType] = {
641 [RV32] = {GDB_XML("target.xml", gdb_xml_riscv_32bit_target),
642 GDB_XML("riscv-32bit-cpu.xml", gdb_xml_riscv_32bit_cpu),
643 GDB_XML("riscv-32bit-fpu.xml", gdb_xml_riscv_32bit_fpu),
644 GDB_XML("riscv-32bit-csr.xml", gdb_xml_riscv_32bit_csr)},
645 [RV64] = {GDB_XML("target.xml", gdb_xml_riscv_64bit_target),
646 GDB_XML("riscv-64bit-cpu.xml", gdb_xml_riscv_64bit_cpu),
647 GDB_XML("riscv-64bit-fpu.xml", gdb_xml_riscv_64bit_fpu),
648 GDB_XML("riscv-64bit-csr.xml", gdb_xml_riscv_64bit_csr)},
649 };
650 auto& annexMap = annexMaps[getRvType(context())];
651 auto it = annexMap.find(annex);
652 if (it == annexMap.end())
653 return false;
654 output = it->second;
655 return true;
656}
657
658BaseGdbRegCache *
659RemoteGDB::gdbRegs()
660{
661 BaseGdbRegCache* regs[enums::Num_RiscvType] = {
662 [RV32] = &regCache32,
663 [RV64] = &regCache64,
664 };
665 return regs[getRvType(context())];
666}
667
668} // namespace gem5
GDB_XML
#define GDB_XML(x, s)
remote_gdb.hh
DPRINTF
#define DPRINTF(x,...)
Definition trace.hh:210
gem5::ArmISA::RemoteGDB::RemoteGDB
RemoteGDB(System *_system, ListenSocketConfig _listen_config)
Definition remote_gdb.cc:204
gem5::PCStateBase::instAddr
Addr instAddr() const
Returns the memory address of the instruction this PC points to.
Definition pcstate.hh:108
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition guest_abi.test.cc:41
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
gem5::ThreadContext::getReg
virtual RegVal getReg(const RegId &reg) const
Definition thread_context.cc:180
gem5::ThreadContext::setMiscRegNoEffect
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0
gem5::ThreadContext::getIsaPtr
virtual BaseISA * getIsaPtr() const =0
gem5::ThreadContext::setReg
virtual void setReg(const RegId &reg, RegVal val)
Definition thread_context.cc:188
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gem5::ThreadContext::contextId
virtual ContextID contextId() const =0
full_system.hh
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition logging.hh:214
len
uint16_t len
Definition helpers.cc:83
gem5::ArmISA::mask
Bitfield< 3, 0 > mask
Definition pcstate.hh:63
gem5::ArmISA::i
Bitfield< 7 > i
Definition misc_types.hh:67
gem5::ArmISA::intRegClass
constexpr RegClass intRegClass
Definition int.hh:173
gem5::ArmISA::va
Bitfield< 8 > va
Definition misc_types.hh:356
gem5::RiscvISA::RV32
constexpr enums::RiscvType RV32
Definition pcstate.hh:56
gem5::RiscvISA::PrivilegeModeSet
enums::PrivilegeModeSet PrivilegeModeSet
Definition pcstate.hh:59
gem5::RiscvISA::RiscvType
enums::RiscvType RiscvType
Definition pcstate.hh:55
gem5::RiscvISA::CSRData
const std::unordered_map< int, CSRMetadata > CSRData
Definition misc.hh:536
gem5::RiscvISA::CSRMasks
const std::unordered_map< int, RegVal > CSRMasks[enums::Num_RiscvType][enums::Num_PrivilegeModeSet]
Definition misc.hh:1503
gem5::RiscvISA::RV64
constexpr enums::RiscvType RV64
Definition pcstate.hh:57
gem5::X86ISA::val
Bitfield< 63 > val
Definition misc.hh:804
gem5::X86ISA::floatRegClass
constexpr RegClass floatRegClass
Definition float.hh:143
gem5
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition types.hh:249
gem5::setRegNoEffectWithMask
static void setRegNoEffectWithMask(ThreadContext *context, RiscvType type, PrivilegeModeSet pms, CSRIndex idx, xint val)
Definition remote_gdb.cc:180
gem5::RegVal
uint64_t RegVal
Definition types.hh:173
gem5::getPrivilegeModeSet
static PrivilegeModeSet getPrivilegeModeSet(ThreadContext *tc)
Definition remote_gdb.cc:171
gem5::setRegWithMask
static void setRegWithMask(ThreadContext *context, RiscvType type, PrivilegeModeSet pms, CSRIndex idx, xint val)
Definition remote_gdb.cc:193
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
gem5::getRvType
static RiscvType getRvType(ThreadContext *tc)
Definition remote_gdb.cc:163
page_table.hh
Declarations of a non-full system Page Table.
pagetable_walker.hh
thread_state.hh
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