gem5  v22.1.0.0
remote_gdb.cc
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1 /*
2  * Copyright (c) 2021 Huawei International
3  * Copyright 2015 LabWare
4  * Copyright 2014 Google, Inc.
5  * Copyright (c) 2010 ARM Limited
6  * Copyright (c) 2020 Barkhausen Institut
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17  *
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24  * met: redistributions of source code must retain the above copyright
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45 
46 /*
47  * Copyright (c) 1990, 1993 The Regents of the University of California
48  * All rights reserved
49  *
50  * This software was developed by the Computer Systems Engineering group
51  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
52  * contributed to Berkeley.
53  *
54  * All advertising materials mentioning features or use of this software
55  * must display the following acknowledgement:
56  * This product includes software developed by the University of
57  * California, Lawrence Berkeley Laboratories.
58  *
59  * Redistribution and use in source and binary forms, with or without
60  * modification, are permitted provided that the following conditions
61  * are met:
62  * 1. Redistributions of source code must retain the above copyright
63  * notice, this list of conditions and the following disclaimer.
64  * 2. Redistributions in binary form must reproduce the above copyright
65  * notice, this list of conditions and the following disclaimer in the
66  * documentation and/or other materials provided with the distribution.
67  * 3. All advertising materials mentioning features or use of this software
68  * must display the following acknowledgement:
69  * This product includes software developed by the University of
70  * California, Berkeley and its contributors.
71  * 4. Neither the name of the University nor the names of its contributors
72  * may be used to endorse or promote products derived from this software
73  * without specific prior written permission.
74  *
75  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
76  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
77  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
78  * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
79  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
80  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
81  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
82  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
83  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
84  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
85  * SUCH DAMAGE.
86  *
87  * @(#)kgdb_stub.c 8.4 (Berkeley) 1/12/94
88  */
89 
90 /*-
91  * Copyright (c) 2001 The NetBSD Foundation, Inc.
92  * All rights reserved.
93  *
94  * This code is derived from software contributed to The NetBSD Foundation
95  * by Jason R. Thorpe.
96  *
97  * Redistribution and use in source and binary forms, with or without
98  * modification, are permitted provided that the following conditions
99  * are met:
100  * 1. Redistributions of source code must retain the above copyright
101  * notice, this list of conditions and the following disclaimer.
102  * 2. Redistributions in binary form must reproduce the above copyright
103  * notice, this list of conditions and the following disclaimer in the
104  * documentation and/or other materials provided with the distribution.
105  * 3. All advertising materials mentioning features or use of this software
106  * must display the following acknowledgement:
107  * This product includes software developed by the NetBSD
108  * Foundation, Inc. and its contributors.
109  * 4. Neither the name of The NetBSD Foundation nor the names of its
110  * contributors may be used to endorse or promote products derived
111  * from this software without specific prior written permission.
112  *
113  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
114  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
115  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
116  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
117  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
118  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
119  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
120  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
121  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
122  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
123  * POSSIBILITY OF SUCH DAMAGE.
124  */
125 
126 /*
127  * $NetBSD: kgdb_stub.c,v 1.8 2001/07/07 22:58:00 wdk Exp $
128  *
129  * Taken from NetBSD
130  *
131  * "Stub" to allow remote cpu to debug over a serial line using gdb.
132  */
133 
134 #include "arch/riscv/remote_gdb.hh"
135 
136 #include <string>
137 
138 #include "arch/riscv/gdb-xml/gdb_xml_riscv_cpu.hh"
139 #include "arch/riscv/gdb-xml/gdb_xml_riscv_csr.hh"
140 #include "arch/riscv/gdb-xml/gdb_xml_riscv_fpu.hh"
141 #include "arch/riscv/gdb-xml/gdb_xml_riscv_target.hh"
142 #include "arch/riscv/mmu.hh"
143 #include "arch/riscv/pagetable_walker.hh"
144 #include "arch/riscv/regs/float.hh"
145 #include "arch/riscv/regs/int.hh"
146 #include "arch/riscv/regs/misc.hh"
147 #include "arch/riscv/tlb.hh"
148 #include "cpu/thread_state.hh"
149 #include "debug/GDBAcc.hh"
150 #include "mem/page_table.hh"
151 #include "sim/full_system.hh"
152 
153 namespace gem5
154 {
155 
156 using namespace RiscvISA;
157 
158 RemoteGDB::RemoteGDB(System *_system, int _port)
159  : BaseRemoteGDB(_system, _port), regCache(this)
160 {
161 }
162 
163 bool
164 RemoteGDB::acc(Addr va, size_t len)
165 {
166  if (FullSystem)
167  {
168  MMU *mmu = static_cast<MMU *>(context()->getMMUPtr());
169  unsigned logBytes;
170  Addr paddr = va;
171 
172  PrivilegeMode pmode = mmu->getMemPriv(context(), BaseMMU::Read);
173  SATP satp = context()->readMiscReg(MISCREG_SATP);
174  if (pmode != PrivilegeMode::PRV_M &&
175  satp.mode != AddrXlateMode::BARE) {
176  Walker *walker = mmu->getDataWalker();
177  Fault fault = walker->startFunctional(
178  context(), paddr, logBytes, BaseMMU::Read);
179  if (fault != NoFault)
180  return false;
181  }
182  return true;
183  }
184 
185  return context()->getProcessPtr()->pTable->lookup(va) != nullptr;
186 }
187 
188 void
189 RemoteGDB::RiscvGdbRegCache::getRegs(ThreadContext *context)
190 {
191  DPRINTF(GDBAcc, "getregs in remotegdb, size %lu\n", size());
192 
193  // General registers
194  for (int i = 0; i < int_reg::NumArchRegs; i++) {
195  r.gpr[i] = context->getReg(intRegClass[i]);
196  }
197  r.pc = context->pcState().instAddr();
198 
199  // Floating point registers
200  for (int i = 0; i < float_reg::NumRegs; i++)
201  r.fpu[i] = context->getReg(floatRegClass[i]);
202  r.fflags = context->readMiscRegNoEffect(
203  CSRData.at(CSR_FFLAGS).physIndex) & CSRMasks.at(CSR_FFLAGS);
204  r.frm = context->readMiscRegNoEffect(
205  CSRData.at(CSR_FRM).physIndex) & CSRMasks.at(CSR_FRM);
206  r.fcsr = context->readMiscRegNoEffect(
207  CSRData.at(CSR_FCSR).physIndex) & CSRMasks.at(CSR_FCSR);
208 
209  // CSR registers
210  r.cycle = context->readMiscRegNoEffect(
211  CSRData.at(CSR_CYCLE).physIndex);
212  r.time = context->readMiscRegNoEffect(
213  CSRData.at(CSR_TIME).physIndex);
214 
215  // U mode CSR
216  r.ustatus = context->readMiscRegNoEffect(
217  CSRData.at(CSR_USTATUS).physIndex) & CSRMasks.at(CSR_USTATUS);
218  r.uie = context->readMiscReg(
219  CSRData.at(CSR_UIE).physIndex) & CSRMasks.at(CSR_UIE);
220  r.utvec = context->readMiscRegNoEffect(
221  CSRData.at(CSR_UTVEC).physIndex);
222  r.uscratch = context->readMiscRegNoEffect(
223  CSRData.at(CSR_USCRATCH).physIndex);
224  r.uepc = context->readMiscRegNoEffect(
225  CSRData.at(CSR_UEPC).physIndex);
226  r.ucause = context->readMiscRegNoEffect(
227  CSRData.at(CSR_UCAUSE).physIndex);
228  r.utval = context->readMiscRegNoEffect(
229  CSRData.at(CSR_UTVAL).physIndex);
230  r.uip = context->readMiscReg(
231  CSRData.at(CSR_UIP).physIndex) & CSRMasks.at(CSR_UIP);
232 
233  // S mode CSR
234  r.sstatus = context->readMiscRegNoEffect(
235  CSRData.at(CSR_SSTATUS).physIndex) & CSRMasks.at(CSR_SSTATUS);
236  r.sedeleg = context->readMiscRegNoEffect(
237  CSRData.at(CSR_SEDELEG).physIndex);
238  r.sideleg = context->readMiscRegNoEffect(
239  CSRData.at(CSR_SIDELEG).physIndex);
240  r.sie = context->readMiscReg(
241  CSRData.at(CSR_SIE).physIndex) & CSRMasks.at(CSR_SIE);
242  r.stvec = context->readMiscRegNoEffect(
243  CSRData.at(CSR_STVEC).physIndex);
244  r.scounteren = context->readMiscRegNoEffect(
245  CSRData.at(CSR_SCOUNTEREN).physIndex);
246  r.sscratch = context->readMiscRegNoEffect(
247  CSRData.at(CSR_SSCRATCH).physIndex);
248  r.sepc = context->readMiscRegNoEffect(
249  CSRData.at(CSR_SEPC).physIndex);
250  r.scause = context->readMiscRegNoEffect(
251  CSRData.at(CSR_SCAUSE).physIndex);
252  r.stval = context->readMiscRegNoEffect(
253  CSRData.at(CSR_STVAL).physIndex);
254  r.sip = context->readMiscReg(
255  CSRData.at(CSR_SIP).physIndex) & CSRMasks.at(CSR_SIP);
256  r.satp = context->readMiscRegNoEffect(
257  CSRData.at(CSR_SATP).physIndex);
258 
259  // M mode CSR
260  r.mvendorid = context->readMiscRegNoEffect(
261  CSRData.at(CSR_MVENDORID).physIndex);
262  r.marchid = context->readMiscRegNoEffect(
263  CSRData.at(CSR_MARCHID).physIndex);
264  r.mimpid = context->readMiscRegNoEffect(
265  CSRData.at(CSR_MIMPID).physIndex);
266  r.mhartid = context->readMiscRegNoEffect(
267  CSRData.at(CSR_MHARTID).physIndex);
268  r.mstatus = context->readMiscRegNoEffect(
269  CSRData.at(CSR_MSTATUS).physIndex) & CSRMasks.at(CSR_MSTATUS);
270  r.misa = context->readMiscRegNoEffect(
271  CSRData.at(CSR_MISA).physIndex) & CSRMasks.at(CSR_MISA);
272  r.medeleg = context->readMiscRegNoEffect(
273  CSRData.at(CSR_MEDELEG).physIndex);
274  r.mideleg = context->readMiscRegNoEffect(
275  CSRData.at(CSR_MIDELEG).physIndex);
276  r.mie = context->readMiscReg(
277  CSRData.at(CSR_MIE).physIndex) & CSRMasks.at(CSR_MIE);
278  r.mtvec = context->readMiscRegNoEffect(
279  CSRData.at(CSR_MTVEC).physIndex);
280  r.mcounteren = context->readMiscRegNoEffect(
281  CSRData.at(CSR_MCOUNTEREN).physIndex);
282  r.mscratch = context->readMiscRegNoEffect(
283  CSRData.at(CSR_MSCRATCH).physIndex);
284  r.mepc = context->readMiscRegNoEffect(
285  CSRData.at(CSR_MEPC).physIndex);
286  r.mcause = context->readMiscRegNoEffect(
287  CSRData.at(CSR_MCAUSE).physIndex);
288  r.mtval = context->readMiscRegNoEffect(
289  CSRData.at(CSR_MTVAL).physIndex);
290  r.mip = context->readMiscReg(
291  CSRData.at(CSR_MIP).physIndex) & CSRMasks.at(CSR_MIP);
292 
293  // H mode CSR (to be implemented)
294 }
295 
296 void
297 RemoteGDB::RiscvGdbRegCache::setRegs(ThreadContext *context) const
298 {
299  // NOTE: no error will be reported for attempting to set masked bits.
300  RegVal oldVal;
301  int mask;
302  RegVal newVal;
303 
304  DPRINTF(GDBAcc, "setregs in remotegdb \n");
305  for (int i = 0; i < int_reg::NumArchRegs; i++)
306  context->setReg(intRegClass[i], r.gpr[i]);
307  context->pcState(r.pc);
308 
309  // Floating point registers
310  for (int i = 0; i < float_reg::NumRegs; i++)
311  context->setReg(floatRegClass[i], r.fpu[i]);
312 
313  oldVal = context->readMiscRegNoEffect(
314  CSRData.at(CSR_FFLAGS).physIndex);
315  mask = CSRMasks.at(CSR_FFLAGS);
316  newVal = (oldVal & ~mask) | (r.fflags & mask);
317  context->setMiscRegNoEffect(
318  CSRData.at(CSR_FFLAGS).physIndex, newVal);
319 
320  oldVal = context->readMiscRegNoEffect(
321  CSRData.at(CSR_FRM).physIndex);
322  mask = CSRMasks.at(CSR_FRM);
323  newVal = (oldVal & ~mask) | (r.frm & mask);
324  context->setMiscRegNoEffect(
325  CSRData.at(CSR_FRM).physIndex, newVal);
326 
327  oldVal = context->readMiscRegNoEffect(
328  CSRData.at(CSR_FCSR).physIndex);
329  mask = CSRMasks.at(CSR_FCSR);
330  newVal = (oldVal & ~mask) | (r.fcsr & mask);
331  context->setMiscRegNoEffect(
332  CSRData.at(CSR_FCSR).physIndex, newVal);
333 
334  // CSR registers
335  context->setMiscRegNoEffect(
336  CSRData.at(CSR_CYCLE).physIndex, r.cycle);
337  context->setMiscRegNoEffect(
338  CSRData.at(CSR_TIME).physIndex, r.time);
339 
340  // U mode CSR
341  oldVal = context->readMiscRegNoEffect(
342  CSRData.at(CSR_USTATUS).physIndex);
343  mask = CSRMasks.at(CSR_USTATUS);
344  newVal = (oldVal & ~mask) | (r.ustatus & mask);
345  context->setMiscRegNoEffect(
346  CSRData.at(CSR_USTATUS).physIndex, newVal);
347  oldVal = context->readMiscReg(
348  CSRData.at(CSR_UIE).physIndex);
349  mask = CSRMasks.at(CSR_UIE);
350  newVal = (oldVal & ~mask) | (r.uie & mask);
351  context->setMiscReg(
352  CSRData.at(CSR_UIE).physIndex, newVal);
353  context->setMiscRegNoEffect(
354  CSRData.at(CSR_UTVEC).physIndex, r.utvec);
355  context->setMiscRegNoEffect(
356  CSRData.at(CSR_USCRATCH).physIndex, r.uscratch);
357  context->setMiscRegNoEffect(
358  CSRData.at(CSR_UEPC).physIndex, r.uepc);
359  context->setMiscRegNoEffect(
360  CSRData.at(CSR_UCAUSE).physIndex, r.ucause);
361  context->setMiscRegNoEffect(
362  CSRData.at(CSR_UTVAL).physIndex, r.utval);
363  oldVal = context->readMiscReg(
364  CSRData.at(CSR_UIP).physIndex);
365  mask = CSRMasks.at(CSR_UIP);
366  newVal = (oldVal & ~mask) | (r.uip & mask);
367  context->setMiscReg(
368  CSRData.at(CSR_UIP).physIndex, newVal);
369 
370  // S mode CSR
371  oldVal = context->readMiscRegNoEffect(
372  CSRData.at(CSR_SSTATUS).physIndex);
373  mask = CSRMasks.at(CSR_SSTATUS);
374  newVal = (oldVal & ~mask) | (r.sstatus & mask);
375  context->setMiscRegNoEffect(
376  CSRData.at(CSR_SSTATUS).physIndex, newVal);
377  context->setMiscRegNoEffect(
378  CSRData.at(CSR_SEDELEG).physIndex, r.sedeleg);
379  context->setMiscRegNoEffect(
380  CSRData.at(CSR_SIDELEG).physIndex, r.sideleg);
381  oldVal = context->readMiscReg(
382  CSRData.at(CSR_SIE).physIndex);
383  mask = CSRMasks.at(CSR_SIE);
384  newVal = (oldVal & ~mask) | (r.sie & mask);
385  context->setMiscReg(
386  CSRData.at(CSR_SIE).physIndex, newVal);
387  context->setMiscRegNoEffect(
388  CSRData.at(CSR_STVEC).physIndex, r.stvec);
389  context->setMiscRegNoEffect(
390  CSRData.at(CSR_SCOUNTEREN).physIndex, r.scounteren);
391  context->setMiscRegNoEffect(
392  CSRData.at(CSR_SSCRATCH).physIndex, r.sscratch);
393  context->setMiscRegNoEffect(
394  CSRData.at(CSR_SEPC).physIndex, r.sepc);
395  context->setMiscRegNoEffect(
396  CSRData.at(CSR_SCAUSE).physIndex, r.scause);
397  context->setMiscRegNoEffect(
398  CSRData.at(CSR_STVAL).physIndex, r.stval);
399  oldVal = context->readMiscReg(
400  CSRData.at(CSR_SIP).physIndex);
401  mask = CSRMasks.at(CSR_SIP);
402  newVal = (oldVal & ~mask) | (r.sip & mask);
403  context->setMiscReg(
404  CSRData.at(CSR_SIP).physIndex, newVal);
405  context->setMiscRegNoEffect(
406  CSRData.at(CSR_SATP).physIndex, r.satp);
407 
408  // M mode CSR
409  context->setMiscRegNoEffect(
410  CSRData.at(CSR_MVENDORID).physIndex, r.mvendorid);
411  context->setMiscRegNoEffect(
412  CSRData.at(CSR_MARCHID).physIndex, r.marchid);
413  context->setMiscRegNoEffect(
414  CSRData.at(CSR_MIMPID).physIndex, r.mimpid);
415  context->setMiscRegNoEffect(
416  CSRData.at(CSR_MHARTID).physIndex, r.mhartid);
417  oldVal = context->readMiscRegNoEffect(
418  CSRData.at(CSR_MSTATUS).physIndex);
419  mask = CSRMasks.at(CSR_MSTATUS);
420  newVal = (oldVal & ~mask) | (r.mstatus & mask);
421  context->setMiscRegNoEffect(
422  CSRData.at(CSR_MSTATUS).physIndex, newVal);
423  oldVal = context->readMiscRegNoEffect(
424  CSRData.at(CSR_MISA).physIndex);
425  mask = CSRMasks.at(CSR_MISA);
426  newVal = (oldVal & ~mask) | (r.misa & mask);
427  context->setMiscRegNoEffect(
428  CSRData.at(CSR_MISA).physIndex, newVal);
429  context->setMiscRegNoEffect(
430  CSRData.at(CSR_MEDELEG).physIndex, r.medeleg);
431  context->setMiscRegNoEffect(
432  CSRData.at(CSR_MIDELEG).physIndex, r.mideleg);
433  oldVal = context->readMiscReg(
434  CSRData.at(CSR_MIE).physIndex);
435  mask = CSRMasks.at(CSR_MIE);
436  newVal = (oldVal & ~mask) | (r.mie & mask);
437  context->setMiscReg(
438  CSRData.at(CSR_MIE).physIndex, newVal);
439  context->setMiscRegNoEffect(
440  CSRData.at(CSR_MTVEC).physIndex, r.mtvec);
441  context->setMiscRegNoEffect(
442  CSRData.at(CSR_MCOUNTEREN).physIndex, r.mcounteren);
443  context->setMiscRegNoEffect(
444  CSRData.at(CSR_MSCRATCH).physIndex, r.mscratch);
445  context->setMiscRegNoEffect(
446  CSRData.at(CSR_MEPC).physIndex, r.mepc);
447  context->setMiscRegNoEffect(
448  CSRData.at(CSR_MCAUSE).physIndex, r.mcause);
449  context->setMiscRegNoEffect(
450  CSRData.at(CSR_MTVAL).physIndex, r.mtval);
451  oldVal = context->readMiscReg(
452  CSRData.at(CSR_MIP).physIndex);
453  mask = CSRMasks.at(CSR_MIP);
454  newVal = (oldVal & ~mask) | (r.mip & mask);
455  context->setMiscReg(
456  CSRData.at(CSR_MIP).physIndex, newVal);
457 
458  // H mode CSR (to be implemented)
459 }
460 
461 bool
462 RemoteGDB::getXferFeaturesRead(const std::string &annex, std::string &output)
463 {
470 #define GDB_XML(x, s) \
471  { \
472  x, std::string(reinterpret_cast<const char *>(Blobs::s), \
473  Blobs::s##_len) \
474  }
475  static const std::map<std::string, std::string> annexMap{
476  GDB_XML("target.xml", gdb_xml_riscv_target),
477  GDB_XML("riscv-64bit-cpu.xml", gdb_xml_riscv_cpu),
478  GDB_XML("riscv-64bit-fpu.xml", gdb_xml_riscv_fpu),
479  GDB_XML("riscv-64bit-csr.xml", gdb_xml_riscv_csr)};
480 #undef GDB_XML
481  auto it = annexMap.find(annex);
482  if (it == annexMap.end())
483  return false;
484  output = it->second;
485  return true;
486 }
487 
488 BaseGdbRegCache *
489 RemoteGDB::gdbRegs()
490 {
491  return &regCache;
492 }
493 
494 } // namespace gem5
GDB_XML
#define GDB_XML(x, s)
remote_gdb.hh
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::BaseGdbRegCache
Concrete subclasses of this abstract class represent how the register values are transmitted on the w...
Definition: remote_gdb.hh:86
gem5::PCStateBase::instAddr
Addr instAddr() const
Returns the memory address of the instruction this PC points to.
Definition: pcstate.hh:107
gem5::RiscvISA::RemoteGDB::RemoteGDB
RemoteGDB(System *_system, int _port)
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:89
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
gem5::ThreadContext::getReg
virtual RegVal getReg(const RegId &reg) const
Definition: thread_context.cc:166
gem5::ThreadContext::setMiscRegNoEffect
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::ThreadContext::setReg
virtual void setReg(const RegId &reg, RegVal val)
Definition: thread_context.cc:174
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
full_system.hh
len
uint16_t len
Definition: helpers.cc:62
gem5::ArmISA::cc_reg::NumRegs
@ NumRegs
Definition: cc.hh:61
gem5::ArmISA::mask
Bitfield< 3, 0 > mask
Definition: pcstate.hh:63
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::ArmISA::intRegClass
constexpr RegClass intRegClass
Definition: int.hh:173
gem5::ArmISA::va
Bitfield< 8 > va
Definition: misc_types.hh:282
gem5::MipsISA::float_reg::NumArchRegs
@ NumArchRegs
Definition: float.hh:79
gem5::RiscvISA::CSR_SSCRATCH
@ CSR_SSCRATCH
Definition: misc.hh:261
gem5::RiscvISA::CSR_USCRATCH
@ CSR_USCRATCH
Definition: misc.hh:213
gem5::RiscvISA::CSR_MSCRATCH
@ CSR_MSCRATCH
Definition: misc.hh:279
gem5::RiscvISA::CSR_MVENDORID
@ CSR_MVENDORID
Definition: misc.hh:268
gem5::RiscvISA::CSR_MCOUNTEREN
@ CSR_MCOUNTEREN
Definition: misc.hh:278
gem5::RiscvISA::CSR_SCOUNTEREN
@ CSR_SCOUNTEREN
Definition: misc.hh:260
gem5::RiscvISA::CSRData
const std::unordered_map< int, CSRMetadata > CSRData
Definition: misc.hh:381
gem5::RiscvISA::CSRMasks
const std::unordered_map< int, RegVal > CSRMasks
Definition: misc.hh:664
gem5::RiscvISA::MISCREG_SATP
@ MISCREG_SATP
Definition: misc.hh:182
gem5::VegaISA::r
Bitfield< 5 > r
Definition: pagetable.hh:60
gem5::X86ISA::floatRegClass
constexpr RegClass floatRegClass
Definition: float.hh:143
gem5::trace::output
std::ostream & output()
Get the ostream from the current global logger.
Definition: trace.cc:79
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:38
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:220
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:253
page_table.hh
Declarations of a non-full system Page Table.
pagetable_walker.hh
thread_state.hh
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