gem5  v22.0.0.2
hetero_mem_ctrl.cc
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14  * Copyright (c) 2013 Amin Farmahini-Farahani
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40 
41 #include "mem/hetero_mem_ctrl.hh"
42 
43 #include "base/trace.hh"
44 #include "debug/DRAM.hh"
45 #include "debug/Drain.hh"
46 #include "debug/MemCtrl.hh"
47 #include "debug/NVM.hh"
48 #include "debug/QOS.hh"
49 #include "mem/dram_interface.hh"
50 #include "mem/mem_interface.hh"
51 #include "mem/nvm_interface.hh"
52 #include "sim/system.hh"
53 
54 namespace gem5
55 {
56 
57 namespace memory
58 {
59 
60 HeteroMemCtrl::HeteroMemCtrl(const HeteroMemCtrlParams &p) :
61  MemCtrl(p),
62  nvm(p.nvm)
63 {
64  DPRINTF(MemCtrl, "Setting up controller\n");
65  readQueue.resize(p.qos_priorities);
66  writeQueue.resize(p.qos_priorities);
67 
68  fatal_if(dynamic_cast<DRAMInterface*>(dram) == nullptr,
69  "HeteroMemCtrl's dram interface must be of type DRAMInterface.\n");
70  fatal_if(dynamic_cast<NVMInterface*>(nvm) == nullptr,
71  "HeteroMemCtrl's nvm interface must be of type NVMInterface.\n");
72 
73  // hook up interfaces to the controller
74  dram->setCtrl(this, commandWindow);
75  nvm->setCtrl(this, commandWindow);
76 
79 
80  writeHighThreshold = writeBufferSize * p.write_high_thresh_perc / 100.0;
81  writeLowThreshold = writeBufferSize * p.write_low_thresh_perc / 100.0;
82 
83  // perform a basic check of the write thresholds
84  if (p.write_low_thresh_perc >= p.write_high_thresh_perc)
85  fatal("Write buffer low threshold %d must be smaller than the "
86  "high threshold %d\n", p.write_low_thresh_perc,
87  p.write_high_thresh_perc);
88 }
89 
90 Tick
92 {
93  Tick latency = 0;
94 
95  if (dram->getAddrRange().contains(pkt->getAddr())) {
96  latency = MemCtrl::recvAtomicLogic(pkt, dram);
97  } else if (nvm->getAddrRange().contains(pkt->getAddr())) {
98  latency = MemCtrl::recvAtomicLogic(pkt, nvm);
99  } else {
100  panic("Can't handle address range for packet %s\n", pkt->print());
101  }
102 
103  return latency;
104 }
105 
106 bool
108 {
109  // This is where we enter from the outside world
110  DPRINTF(MemCtrl, "recvTimingReq: request %s addr %#x size %d\n",
111  pkt->cmdString(), pkt->getAddr(), pkt->getSize());
112 
113  panic_if(pkt->cacheResponding(), "Should not see packets where cache "
114  "is responding");
115 
116  panic_if(!(pkt->isRead() || pkt->isWrite()),
117  "Should only see read and writes at memory controller\n");
118 
119  // Calc avg gap between requests
120  if (prevArrival != 0) {
122  }
123  prevArrival = curTick();
124 
125  // What type of media does this packet access?
126  bool is_dram;
127  if (dram->getAddrRange().contains(pkt->getAddr())) {
128  is_dram = true;
129  } else if (nvm->getAddrRange().contains(pkt->getAddr())) {
130  is_dram = false;
131  } else {
132  panic("Can't handle address range for packet %s\n",
133  pkt->print());
134  }
135 
136  // Find out how many memory packets a pkt translates to
137  // If the burst size is equal or larger than the pkt size, then a pkt
138  // translates to only one memory packet. Otherwise, a pkt translates to
139  // multiple memory packets
140  unsigned size = pkt->getSize();
141  uint32_t burst_size = is_dram ? dram->bytesPerBurst() :
142  nvm->bytesPerBurst();
143  unsigned offset = pkt->getAddr() & (burst_size - 1);
144  unsigned int pkt_count = divCeil(offset + size, burst_size);
145 
146  // run the QoS scheduler and assign a QoS priority value to the packet
147  qosSchedule( { &readQueue, &writeQueue }, burst_size, pkt);
148 
149  // check local buffers and do not accept if full
150  if (pkt->isWrite()) {
151  assert(size != 0);
152  if (writeQueueFull(pkt_count)) {
153  DPRINTF(MemCtrl, "Write queue full, not accepting\n");
154  // remember that we have to retry this port
155  retryWrReq = true;
156  stats.numWrRetry++;
157  return false;
158  } else {
159  addToWriteQueue(pkt, pkt_count, is_dram ? dram : nvm);
160  // If we are not already scheduled to get a request out of the
161  // queue, do so now
162  if (!nextReqEvent.scheduled()) {
163  DPRINTF(MemCtrl, "Request scheduled immediately\n");
165  }
166  stats.writeReqs++;
167  stats.bytesWrittenSys += size;
168  }
169  } else {
170  assert(pkt->isRead());
171  assert(size != 0);
172  if (readQueueFull(pkt_count)) {
173  DPRINTF(MemCtrl, "Read queue full, not accepting\n");
174  // remember that we have to retry this port
175  retryRdReq = true;
176  stats.numRdRetry++;
177  return false;
178  } else {
179  if (!addToReadQueue(pkt, pkt_count, is_dram ? dram : nvm)) {
180  // If we are not already scheduled to get a request out of the
181  // queue, do so now
182  if (!nextReqEvent.scheduled()) {
183  DPRINTF(MemCtrl, "Request scheduled immediately\n");
185  }
186  }
187  stats.readReqs++;
188  stats.bytesReadSys += size;
189  }
190  }
191 
192  return true;
193 }
194 
195 void
197  MemPacketQueue& queue,
198  EventFunctionWrapper& resp_event,
199  bool& retry_rd_req)
200 {
202  "processRespondEvent(): Some req has reached its readyTime\n");
203 
204  if (queue.front()->isDram()) {
205  MemCtrl::processRespondEvent(dram, queue, resp_event, retry_rd_req);
206  } else {
207  MemCtrl::processRespondEvent(nvm, queue, resp_event, retry_rd_req);
208  }
209 }
210 
211 MemPacketQueue::iterator
213  MemInterface* mem_int)
214 {
215  // This method does the arbitration between requests.
216 
217  MemPacketQueue::iterator ret = queue.end();
218 
219  if (!queue.empty()) {
220  if (queue.size() == 1) {
221  // available rank corresponds to state refresh idle
222  MemPacket* mem_pkt = *(queue.begin());
223  if (packetReady(mem_pkt, mem_pkt->isDram()? dram : nvm)) {
224  ret = queue.begin();
225  DPRINTF(MemCtrl, "Single request, going to a free rank\n");
226  } else {
227  DPRINTF(MemCtrl, "Single request, going to a busy rank\n");
228  }
229  } else if (memSchedPolicy == enums::fcfs) {
230  // check if there is a packet going to a free rank
231  for (auto i = queue.begin(); i != queue.end(); ++i) {
232  MemPacket* mem_pkt = *i;
233  if (packetReady(mem_pkt, mem_pkt->isDram()? dram : nvm)) {
234  ret = i;
235  break;
236  }
237  }
238  } else if (memSchedPolicy == enums::frfcfs) {
239  Tick col_allowed_at;
240  std::tie(ret, col_allowed_at)
241  = chooseNextFRFCFS(queue, extra_col_delay, mem_int);
242  } else {
243  panic("No scheduling policy chosen\n");
244  }
245  }
246  return ret;
247 }
248 
251  MemInterface* mem_intr)
252 {
253 
254  auto selected_pkt_it = queue.end();
255  auto nvm_pkt_it = queue.end();
256  Tick col_allowed_at = MaxTick;
257  Tick nvm_col_allowed_at = MaxTick;
258 
259  std::tie(selected_pkt_it, col_allowed_at) =
260  MemCtrl::chooseNextFRFCFS(queue, extra_col_delay, dram);
261 
262  std::tie(nvm_pkt_it, nvm_col_allowed_at) =
263  MemCtrl::chooseNextFRFCFS(queue, extra_col_delay, nvm);
264 
265 
266  // Compare DRAM and NVM and select NVM if it can issue
267  // earlier than the DRAM packet
268  if (col_allowed_at > nvm_col_allowed_at) {
269  selected_pkt_it = nvm_pkt_it;
270  col_allowed_at = nvm_col_allowed_at;
271  }
272 
273  return std::make_pair(selected_pkt_it, col_allowed_at);
274 }
275 
276 
277 Tick
279 {
280  // mem_intr will be dram by default in HeteroMemCtrl
281 
282  // When was command issued?
283  Tick cmd_at;
284 
285  if (mem_pkt->isDram()) {
286  cmd_at = MemCtrl::doBurstAccess(mem_pkt, mem_intr);
287  // Update timing for NVM ranks if NVM is configured on this channel
288  nvm->addRankToRankDelay(cmd_at);
289  // Since nextBurstAt and nextReqAt are part of the interface, making
290  // sure that they are same for both nvm and dram interfaces
293 
294  } else {
295  cmd_at = MemCtrl::doBurstAccess(mem_pkt, nvm);
296  // Update timing for NVM ranks if NVM is configured on this channel
297  dram->addRankToRankDelay(cmd_at);
300  }
301 
302  return cmd_at;
303 }
304 
305 bool
307 
308  // mem_intr in case of HeteroMemCtrl will always be dram
309 
310  // check ranks for refresh/wakeup - uses busStateNext, so done after
311  // turnaround decisions
312  // Default to busy status and update based on interface specifics
313  bool dram_busy, nvm_busy = true;
314  // DRAM
315  dram_busy = mem_intr->isBusy(false, false);
316  // NVM
317  bool read_queue_empty = totalReadQueueSize == 0;
318  bool all_writes_nvm = nvm->numWritesQueued == totalWriteQueueSize;
319  nvm_busy = nvm->isBusy(read_queue_empty, all_writes_nvm);
320 
321  // Default state of unused interface is 'true'
322  // Simply AND the busy signals to determine if system is busy
323  if (dram_busy && nvm_busy) {
324  // if all ranks are refreshing wait for them to finish
325  // and stall this state machine without taking any further
326  // action, and do not schedule a new nextReqEvent
327  return true;
328  } else {
329  return false;
330  }
331 }
332 
333 void
335 {
336  // mem_intr by default points to dram in case
337  // of HeteroMemCtrl, therefore, calling nonDetermReads
338  // from MemCtrl using nvm interace
340 }
341 
342 bool
344 {
345  // mem_intr by default points to dram in case
346  // of HeteroMemCtrl, therefore, calling nvmWriteBlock
347  // from MemCtrl using nvm interface
348  return MemCtrl::nvmWriteBlock(nvm);
349 }
350 
351 Tick
353 {
354  return std::min(dram->minReadToWriteDataGap(),
356 }
357 
358 Tick
360 {
361  return std::min(dram->minWriteToReadDataGap(),
363 }
364 
365 Addr
367 {
368  // mem_intr will point to dram interface in HeteroMemCtrl
369  if (mem_intr->getAddrRange().contains(addr)) {
370  return (addr & ~(Addr(mem_intr->bytesPerBurst() - 1)));
371  } else {
372  assert(nvm->getAddrRange().contains(addr));
373  return (addr & ~(Addr(nvm->bytesPerBurst() - 1)));
374  }
375 }
376 
377 bool
379 {
380  // mem_intr will point to dram interface in HeteroMemCtrl
381  if (mem_pkt->isDram()) {
382  return (mem_pkt->size <= mem_intr->bytesPerBurst());
383  } else {
384  return (mem_pkt->size <= nvm->bytesPerBurst());
385  }
386 }
387 
388 void
390 {
391  bool found;
392 
393  found = MemCtrl::recvFunctionalLogic(pkt, dram);
394 
395  if (!found) {
396  found = MemCtrl::recvFunctionalLogic(pkt, nvm);
397  }
398 
399  if (!found) {
400  panic("Can't handle address range for packet %s\n", pkt->print());
401  }
402 }
403 
404 bool
406 {
407  // ensure dram is in power down and refresh IDLE states
408  bool dram_drained = dram->allRanksDrained();
409  // No outstanding NVM writes
410  // All other queues verified as needed with calling logic
411  bool nvm_drained = nvm->allRanksDrained();
412  return (dram_drained && nvm_drained);
413 }
414 
417 {
418  // if there is anything in any of our internal queues, keep track
419  // of that as well
420  if (!(!totalWriteQueueSize && !totalReadQueueSize && respQueue.empty() &&
421  allIntfDrained())) {
422 
423  DPRINTF(Drain, "Memory controller not drained, write: %d, read: %d,"
424  " resp: %d\n", totalWriteQueueSize, totalReadQueueSize,
425  respQueue.size());
426 
427  // the only queue that is not drained automatically over time
428  // is the write queue, thus kick things into action if needed
431  }
432 
433  dram->drainRanks();
434 
435  return DrainState::Draining;
436  } else {
437  return DrainState::Drained;
438  }
439 }
440 
441 void
443 {
444  if (!isTimingMode && system()->isTimingMode()) {
445  // if we switched to timing mode, kick things into action,
446  // and behave as if we restored from a checkpoint
447  startup();
448  dram->startup();
449  } else if (isTimingMode && !system()->isTimingMode()) {
450  // if we switch from timing mode, stop the refresh events to
451  // not cause issues with KVM
452  dram->suspend();
453  }
454 
455  // update the mode
457 }
458 
461 {
462  AddrRangeList ranges;
463  ranges.push_back(dram->getAddrRange());
464  ranges.push_back(nvm->getAddrRange());
465  return ranges;
466 }
467 
468 } // namespace memory
469 } // namespace gem5
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:190
gem5::Packet::cmdString
const std::string & cmdString() const
Return the string name of the cmd field (for debugging and tracing).
Definition: packet.hh:585
gem5::memory::qos::MemCtrl::totalReadQueueSize
uint64_t totalReadQueueSize
Total read request packets queue length in #packets.
Definition: mem_ctrl.hh:131
gem5::memory::HeteroMemCtrl::minWriteToReadDataGap
Tick minWriteToReadDataGap() override
Calculate the minimum delay used when scheduling a write-to-read transision.
Definition: hetero_mem_ctrl.cc:359
gem5::memory::HeteroMemCtrl::processRespondEvent
virtual void processRespondEvent(MemInterface *mem_intr, MemPacketQueue &queue, EventFunctionWrapper &resp_event, bool &retry_rd_req) override
Definition: hetero_mem_ctrl.cc:196
gem5::memory::NVMInterface
Interface to NVM devices with media specific parameters, statistics, and functions.
Definition: nvm_interface.hh:64
gem5::memory::MemCtrl::addToReadQueue
bool addToReadQueue(PacketPtr pkt, unsigned int pkt_count, MemInterface *mem_intr)
When a new read comes in, first check if the write q has a pending request to the same address....
Definition: mem_ctrl.cc:187
gem5::memory::MemCtrl::writeLowThreshold
uint32_t writeLowThreshold
Definition: mem_ctrl.hh:514
gem5::memory::MemCtrl::nextReqEvent
EventFunctionWrapper nextReqEvent
Definition: mem_ctrl.hh:304
system.hh
gem5::memory::HeteroMemCtrl::nonDetermReads
virtual void nonDetermReads(MemInterface *mem_intr) override
Will access nvm memory interface and select non-deterministic reads to issue.
Definition: hetero_mem_ctrl.cc:334
gem5::memory::MemPacket::size
unsigned int size
The size of this dram packet in bytes It is always equal or smaller than the burst size.
Definition: mem_ctrl.hh:146
gem5::memory::MemInterface::numWritesQueued
uint32_t numWritesQueued
NVM specific variable, but declaring it here allows treating different interfaces in a more genral wa...
Definition: mem_interface.hh:184
gem5::memory::MemInterface::suspend
virtual void suspend()
This function is DRAM specific.
Definition: mem_interface.hh:360
nvm_interface.hh
memory
Definition: mem.h:38
gem5::memory::AbstractMemory::getAddrRange
AddrRange getAddrRange() const
Get the address range.
Definition: abstract_mem.cc:249
gem5::AddrRange::contains
bool contains(const Addr &a) const
Determine if the range contains an address.
Definition: addr_range.hh:471
gem5::memory::MemInterface::allRanksDrained
virtual bool allRanksDrained() const =0
Check drain state of interface.
gem5::memory::MemCtrl
The memory controller is a single-channel memory controller capturing the most important timing const...
Definition: mem_ctrl.hh:246
gem5::memory::NVMInterface::addRankToRankDelay
void addRankToRankDelay(Tick cmd_at) override
Add rank to rank delay to bus timing to all NVM banks in alli ranks when access to an alternate inter...
Definition: nvm_interface.cc:588
gem5::Packet::cacheResponding
bool cacheResponding() const
Definition: packet.hh:655
gem5::memory::MemInterface::addRankToRankDelay
virtual void addRankToRankDelay(Tick cmd_at)=0
Add rank to rank delay to bus timing to all banks in all ranks when access to an alternate interface ...
gem5::memory::NVMInterface::allRanksDrained
bool allRanksDrained() const override
Check drain state of NVM interface.
Definition: nvm_interface.hh:213
gem5::MaxTick
const Tick MaxTick
Definition: types.hh:60
gem5::Packet::isWrite
bool isWrite() const
Definition: packet.hh:591
gem5::memory::MemCtrl::writeHighThreshold
uint32_t writeHighThreshold
Definition: mem_ctrl.hh:513
gem5::memory::MemCtrl::startup
virtual void startup() override
startup() is the final initialization call before simulation.
Definition: mem_ctrl.cc:108
gem5::memory::MemCtrl::prevArrival
Tick prevArrival
Definition: mem_ctrl.hh:551
gem5::memory::MemCtrl::doBurstAccess
virtual Tick doBurstAccess(MemPacket *mem_pkt, MemInterface *mem_intr)
Actually do the burst based on media specific access function.
Definition: mem_ctrl.cc:787
gem5::memory::HeteroMemCtrl::drain
DrainState drain() override
Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are pa...
Definition: hetero_mem_ctrl.cc:416
gem5::memory::MemCtrl::memSchedPolicy
enums::MemSched memSchedPolicy
Memory controller configuration initialized based on parameter values.
Definition: mem_ctrl.hh:524
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::memory::qos::MemCtrl::qosSchedule
uint8_t qosSchedule(std::initializer_list< Queues * > queues_ptr, uint64_t queue_entry_size, const PacketPtr pkt)
Assign priority to a packet by executing the configured QoS policy.
Definition: mem_ctrl.hh:496
gem5::memory::HeteroMemCtrl::doBurstAccess
Tick doBurstAccess(MemPacket *mem_pkt, MemInterface *mem_int) override
Actually do the burst based on media specific access function.
Definition: hetero_mem_ctrl.cc:278
gem5::memory::MemCtrl::readBufferSize
uint32_t readBufferSize
The following are basic design parameters of the memory controller, and are initialized based on para...
Definition: mem_ctrl.hh:511
gem5::memory::MemCtrl::CtrlStats::bytesReadSys
statistics::Scalar bytesReadSys
Definition: mem_ctrl.hh:591
gem5::memory::MemInterface::readBufferSize
const uint32_t readBufferSize
Buffer sizes for read and write queues in the controller These are passed to the controller on instan...
Definition: mem_interface.hh:176
gem5::memory::MemCtrl::retryRdReq
bool retryRdReq
Remember if we have to retry a request when available.
Definition: mem_ctrl.hh:290
gem5::memory::DRAMInterface
Interface to DRAM devices with media specific parameters, statistics, and functions.
Definition: dram_interface.hh:65
gem5::memory::HeteroMemCtrl::pktSizeCheck
virtual bool pktSizeCheck(MemPacket *mem_pkt, MemInterface *mem_intr) const override
Check if mem pkt's size is sane.
Definition: hetero_mem_ctrl.cc:378
gem5::memory::MemInterface::minWriteToReadDataGap
Tick minWriteToReadDataGap() const
Definition: mem_interface.hh:287
gem5::memory::HeteroMemCtrl::allIntfDrained
bool allIntfDrained() const override
Ensure that all interfaced have drained commands.
Definition: hetero_mem_ctrl.cc:405
gem5::memory::MemCtrl::writeQueue
std::vector< MemPacketQueue > writeQueue
Definition: mem_ctrl.hh:470
gem5::memory::MemInterface::drainRanks
virtual void drainRanks()
This function is DRAM specific.
Definition: mem_interface.hh:351
gem5::memory::HeteroMemCtrl::nvmWriteBlock
virtual bool nvmWriteBlock(MemInterface *mem_intr) override
Will check if all writes are for nvm interface and nvm's write resp queue is full.
Definition: hetero_mem_ctrl.cc:343
gem5::DrainState
DrainState
Object drain/handover states.
Definition: drain.hh:74
gem5::memory::HeteroMemCtrl::recvFunctional
void recvFunctional(PacketPtr pkt) override
Definition: hetero_mem_ctrl.cc:389
gem5::memory::qos::MemCtrl::schedule
uint8_t schedule(RequestorID id, uint64_t data)
Definition: mem_ctrl.cc:218
mem_interface.hh
gem5::Packet::isRead
bool isRead() const
Definition: packet.hh:590
gem5::memory::MemCtrl::processRespondEvent
virtual void processRespondEvent(MemInterface *mem_intr, MemPacketQueue &queue, EventFunctionWrapper &resp_event, bool &retry_rd_req)
Definition: mem_ctrl.cc:482
gem5::memory::MemInterface
General interface to memory device Includes functions and parameters shared across media types.
Definition: mem_interface.hh:74
gem5::memory::MemInterface::isBusy
virtual bool isBusy(bool read_queue_empty, bool all_writes_nvm)=0
This function checks if ranks are busy.
gem5::memory::MemCtrl::CtrlStats::numWrRetry
statistics::Scalar numWrRetry
Definition: mem_ctrl.hh:582
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::Packet::print
void print(std::ostream &o, int verbosity=0, const std::string &prefix="") const
Definition: packet.cc:364
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
hetero_mem_ctrl.hh
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::memory::MemCtrl::readQueueFull
bool readQueueFull(unsigned int pkt_count) const
Check if the read queue has room for more entries.
Definition: mem_ctrl.cc:164
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::memory::MemPacket::isDram
bool isDram() const
Return true if its a DRAM access.
Definition: mem_ctrl.hh:204
gem5::memory::MemCtrl::packetReady
virtual bool packetReady(MemPacket *pkt, MemInterface *mem_intr)
Determine if there is a packet that can issue.
Definition: mem_ctrl.cc:1133
gem5::memory::MemPacket
A memory packet stores packets along with the timestamp of when the packet entered the queue,...
Definition: mem_ctrl.hh:98
gem5::memory::MemCtrl::stats
CtrlStats stats
Definition: mem_ctrl.hh:621
gem5::memory::MemCtrl::writeBufferSize
uint32_t writeBufferSize
Definition: mem_ctrl.hh:512
gem5::memory::qos::MemCtrl::system
System * system() const
read the system pointer
Definition: mem_ctrl.hh:371
gem5::memory::HeteroMemCtrl::chooseNextFRFCFS
virtual std::pair< MemPacketQueue::iterator, Tick > chooseNextFRFCFS(MemPacketQueue &queue, Tick extra_col_delay, MemInterface *mem_intr) override
Definition: hetero_mem_ctrl.cc:250
gem5::memory::MemCtrl::recvFunctionalLogic
bool recvFunctionalLogic(PacketPtr pkt, MemInterface *mem_intr)
Definition: mem_ctrl.cc:1365
gem5::memory::HeteroMemCtrl::chooseNext
MemPacketQueue::iterator chooseNext(MemPacketQueue &queue, Tick extra_col_delay, MemInterface *mem_int) override
Definition: hetero_mem_ctrl.cc:212
gem5::memory::MemCtrl::retryWrReq
bool retryWrReq
Definition: mem_ctrl.hh:291
gem5::memory::HeteroMemCtrl::recvTimingReq
bool recvTimingReq(PacketPtr pkt) override
Definition: hetero_mem_ctrl.cc:107
gem5::memory::qos::MemCtrl::totalWriteQueueSize
uint64_t totalWriteQueueSize
Total write request packets queue length in #packets.
Definition: mem_ctrl.hh:134
gem5::ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:144
gem5::memory::MemInterface::writeBufferSize
const uint32_t writeBufferSize
Definition: mem_interface.hh:177
gem5::memory::MemCtrl::CtrlStats::bytesWrittenSys
statistics::Scalar bytesWrittenSys
Definition: mem_ctrl.hh:592
gem5::memory::HeteroMemCtrl::getAddrRanges
AddrRangeList getAddrRanges() override
Definition: hetero_mem_ctrl.cc:460
gem5::memory::MemCtrl::CtrlStats::writeReqs
statistics::Scalar writeReqs
Definition: mem_ctrl.hh:571
gem5::DrainState::Drained
@ Drained
Buffers drained, ready for serialization/handover.
gem5::System::isTimingMode
bool isTimingMode() const
Is the system in timing mode?
Definition: system.hh:274
gem5::memory::MemInterface::minReadToWriteDataGap
Tick minReadToWriteDataGap() const
Definition: mem_interface.hh:281
gem5::memory::MemCtrl::dram
MemInterface * dram
Definition: mem_ctrl.hh:501
gem5::memory::MemCtrl::isTimingMode
bool isTimingMode
Remember if the memory system is in timing mode.
Definition: mem_ctrl.hh:285
gem5::memory::HeteroMemCtrl::HeteroMemCtrl
HeteroMemCtrl(const HeteroMemCtrlParams &p)
Definition: hetero_mem_ctrl.cc:60
gem5::memory::HeteroMemCtrl::recvAtomic
Tick recvAtomic(PacketPtr pkt) override
Definition: hetero_mem_ctrl.cc:91
std::pair
STL pair class.
Definition: stl.hh:58
gem5::memory::MemCtrl::CtrlStats::numRdRetry
statistics::Scalar numRdRetry
Definition: mem_ctrl.hh:581
gem5::memory::NVMInterface::isBusy
bool isBusy(bool read_queue_empty, bool all_writes_nvm) override
This function checks if ranks are busy.
Definition: nvm_interface.cc:605
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::memory::MemCtrl::respQueue
std::deque< MemPacket * > respQueue
Response queue where read packets wait after we're done working with them, but it's not time to send ...
Definition: mem_ctrl.hh:489
gem5::memory::MemCtrl::CtrlStats::totGap
statistics::Scalar totGap
Definition: mem_ctrl.hh:597
gem5::memory::MemInterface::nextBurstAt
Tick nextBurstAt
Till when the controller must wait before issuing next RD/WR burst?
Definition: mem_interface.hh:189
gem5::memory::MemCtrl::chooseNextFRFCFS
virtual std::pair< MemPacketQueue::iterator, Tick > chooseNextFRFCFS(MemPacketQueue &queue, Tick extra_col_delay, MemInterface *mem_intr)
For FR-FCFS policy reorder the read/write queue depending on row buffer hits and earliest bursts avai...
Definition: mem_ctrl.cc:592
gem5::memory::MemCtrl::readQueue
std::vector< MemPacketQueue > readQueue
The controller's main read and write queues, with support for QoS reordering.
Definition: mem_ctrl.hh:469
gem5::divCeil
static constexpr T divCeil(const T &a, const U &b)
Definition: intmath.hh:110
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::memory::HeteroMemCtrl::minReadToWriteDataGap
Tick minReadToWriteDataGap() override
Calculate the minimum delay used when scheduling a read-to-write transision.
Definition: hetero_mem_ctrl.cc:352
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:204
gem5::memory::MemCtrl::CtrlStats::readReqs
statistics::Scalar readReqs
Definition: mem_ctrl.hh:570
gem5::memory::MemInterface::setCtrl
void setCtrl(MemCtrl *_ctrl, unsigned int command_window, uint8_t pseudo_channel=0)
Set a pointer to the controller and initialize interface based on controller parameters.
Definition: mem_interface.cc:77
gem5::memory::HeteroMemCtrl::burstAlign
virtual Addr burstAlign(Addr addr, MemInterface *mem_intr) const override
Burst-align an address.
Definition: hetero_mem_ctrl.cc:366
gem5::memory::MemCtrl::recvAtomicLogic
Tick recvAtomicLogic(PacketPtr pkt, MemInterface *mem_intr)
Definition: mem_ctrl.cc:134
gem5::SimObject::startup
virtual void startup()
startup() is the final initialization call before simulation.
Definition: sim_object.cc:99
dram_interface.hh
std::deque
STL deque class.
Definition: stl.hh:44
gem5::memory::MemInterface::nextReqTime
Tick nextReqTime
Definition: mem_interface.hh:190
gem5::memory::MemCtrl::writeQueueFull
bool writeQueueFull(unsigned int pkt_count) const
Check if the write queue has room for more entries.
Definition: mem_ctrl.cc:176
gem5::memory::HeteroMemCtrl::drainResume
void drainResume() override
Resume execution after a successful drain.
Definition: hetero_mem_ctrl.cc:442
gem5::memory::MemCtrl::addToWriteQueue
void addToWriteQueue(PacketPtr pkt, unsigned int pkt_count, MemInterface *mem_intr)
Decode the incoming pkt, create a mem_pkt and push to the back of the write queue.
Definition: mem_ctrl.cc:300
trace.hh
gem5::memory::MemInterface::bytesPerBurst
uint32_t bytesPerBurst() const
Definition: mem_interface.hh:256
std::list< AddrRange >
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:790
gem5::memory::MemCtrl::commandWindow
const Tick commandWindow
Length of a command window, used to check command bandwidth.
Definition: mem_ctrl.hh:544
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:226
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::memory::MemCtrl::nonDetermReads
virtual void nonDetermReads(MemInterface *mem_intr)
Will access memory interface and select non-deterministic reads to issue.
Definition: mem_ctrl.cc:857
gem5::memory::HeteroMemCtrl::nvm
NVMInterface * nvm
Create pointer to interface of the actual nvm media when connected.
Definition: hetero_mem_ctrl.hh:64
gem5::Packet::getSize
unsigned getSize() const
Definition: packet.hh:800
gem5::DrainState::Draining
@ Draining
Draining buffers pending serialization/handover.
gem5::Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:465
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::memory::HeteroMemCtrl::memBusy
virtual bool memBusy(MemInterface *mem_intr) override
Checks if the memory interface is already busy.
Definition: hetero_mem_ctrl.cc:306
gem5::memory::MemCtrl::nvmWriteBlock
virtual bool nvmWriteBlock(MemInterface *mem_intr)
Will check if all writes are for nvm interface and nvm's write resp queue is full.
Definition: mem_ctrl.cc:850

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