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42 #ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__
43 #define __CPU_CHECKER_THREAD_CONTEXT_HH__
46 #include "config/the_isa.hh"
50 #include "debug/Checker.hh"
95 assert(actual_ret == check_ret);
104 assert(actual_ret == check_ret);
121 return actualTC->getCurrentInstCount();
232 return actualTC->readIntReg(reg_idx);
238 return actualTC->readFloatReg(reg_idx);
277 return actualTC->readCCReg(reg_idx);
346 return actualTC->readMiscRegNoEffect(misc_reg);
352 return actualTC->readMiscReg(misc_reg);
358 DPRINTF(
Checker,
"Setting misc reg with no effect: %d to both Checker"
359 " and O3..\n", misc_reg);
367 DPRINTF(
Checker,
"Setting misc reg with effect: %d to both Checker"
368 " and O3..\n", misc_reg);
376 return actualTC->flattenRegId(regId);
382 return actualTC->readStCondFailures();
388 actualTC->setStCondFailures(sc_failures);
394 return actualTC->readIntRegFlat(idx);
406 return actualTC->readFloatRegFlat(idx);
418 return actualTC->readVecRegFlat(idx);
427 return actualTC->getWritableVecRegFlat(idx);
439 return actualTC->readVecElemFlat(idx, elem_idx);
452 return actualTC->readVecPredRegFlat(idx);
458 return actualTC->getWritableVecPredRegFlat(idx);
471 return actualTC->readCCRegFlat(idx);
484 panic(
"function not implemented");
490 return actualTC->getHtmCheckpointPtr();
496 panic(
"function not implemented");
503 #endif // __CPU_CHECKER_EXEC_CONTEXT_HH__
TheISA::VecRegContainer & getWritableVecRegFlat(RegIndex idx) override
Read vector register for modification, flat indexing.
void setIntReg(RegIndex reg_idx, RegVal val) override
RegVal readIntRegFlat(RegIndex idx) const override
Flat register interfaces.
int cpuId() const override
CheckerThreadContext(TC *actual_tc, CheckerCPU *checker_cpu)
std::unique_ptr< BaseHTMCheckpoint > BaseHTMCheckpointPtr
void setMiscReg(RegIndex misc_reg, RegVal val) override
void setIntReg(RegIndex reg_idx, RegVal val) override
Tick getCurrentInstCount() override
VecPredReg::Container VecPredRegContainer
const TheISA::VecPredRegContainer & readVecPredReg(const RegId ®) const override
void halt() override
Set the status to Halted.
RegVal readVecElem(const RegId ®) const override
void descheduleInstCountEvent(Event *event) override
const PCStateBase & pcState() const override
Reads this thread's PC state.
void setIntRegFlat(RegIndex idx, RegVal val) override
uint32_t socketId() const override
void copyArchRegs(ThreadContext *tc) override
void setVecElemFlat(RegIndex idx, const ElemIndex &elem_idx, RegVal val) override
SimpleThread * checkerTC
The checker's own SimpleThread.
void setMiscReg(RegIndex misc_reg, RegVal val) override
void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
void setVecReg(const RegId ®, const TheISA::VecRegContainer &val) override
bool remove(PCEvent *e) override
void setCCRegFlat(RegIndex idx, RegVal val) override
void clearArchRegs() override
virtual void regStats(const std::string &name)
void setContextId(ContextID id) override
bool remove(PCEvent *e) override
TC * actualTC
The main CPU's ThreadContext, or class that implements the ThreadContext interface.
Derived ThreadContext class for use with the Checker.
void scheduleInstCountEvent(Event *event, Tick count) override
RegVal readMiscReg(RegIndex misc_reg) override
void setVecReg(const RegId ®, const TheISA::VecRegContainer &val) override
The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interf...
void setThreadId(int id) override
void setVecPredReg(const RegId ®, const TheISA::VecPredRegContainer &val) override
RegVal readIntReg(RegIndex reg_idx) const override
Tick readLastActivate() override
System * getSystemPtr() override
RegId flattenRegId(const RegId ®Id) const override
BaseCPU * getCpuPtr() override
void setFloatRegFlat(RegIndex idx, RegVal val) override
void suspend() override
Set the status to Suspended.
RegVal readCCRegFlat(RegIndex idx) const override
CheckerCPU * getCheckerCpuPtr() override
Tick readLastSuspend() override
const TheISA::VecRegContainer & readVecRegFlat(RegIndex idx) const override
void takeOverFrom(ThreadContext *oldContext) override
void copyState(ThreadContext *oldContext)
ThreadContext is the external interface to all thread state for anything outside of the CPU.
void clearArchRegs() override
void connectMemPorts(ThreadContext *tc)
BaseISA * getIsaPtr() override
uint64_t Tick
Tick count type.
void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
RegVal readCCReg(RegIndex reg_idx) const override
TheISA::VecRegContainer & getWritableVecReg(const RegId ®) override
Read vector register for modification, hierarchical indexing.
void setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) override
void setProcessPtr(Process *p) override
void copyArchRegs(ThreadContext *tc) override
gem5::VecRegContainer< NumVecElemPerVecReg *sizeof(VecElem)> VecRegContainer
bool schedule(PCEvent *e) override
ContextID contextId() const override
void htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) override
const PCStateBase & pcState() const override
void recordPCChange(const PCStateBase &val)
void setFloatReg(RegIndex reg_idx, RegVal val) override
uint16_t ElemIndex
Logical vector register elem index type.
const std::string & name()
void setStatus(Status newStatus) override
CheckerCPU * checkerCPU
Pointer to the checker CPU.
void pcStateNoRecord(const PCStateBase &val) override
void setVecPredReg(const RegId ®, const TheISA::VecPredRegContainer &val) override
const TheISA::VecRegContainer & readVecReg(const RegId ®) const override
void setVecElem(const RegId ®, RegVal val) override
RegVal readFloatRegFlat(RegIndex idx) const override
void pcState(const PCStateBase &val) override
Sets this thread's PC state.
bool schedule(PCEvent *e) override
int ContextID
Globally unique thread context ID.
void setCCReg(RegIndex reg_idx, RegVal val) override
Status status() const override
const TheISA::VecPredRegContainer & readVecPredRegFlat(RegIndex idx) const override
BaseHTMCheckpointPtr & getHtmCheckpointPtr() override
void activate() override
Set the status to Active.
TheISA::VecPredRegContainer & getWritableVecPredRegFlat(RegIndex idx) override
void setContextId(ContextID id) override
TheISA::VecPredRegContainer & getWritableVecPredReg(const RegId ®) override
void setStCondFailures(unsigned sc_failures) override
void setVecRegFlat(RegIndex idx, const TheISA::VecRegContainer &val) override
void setVecPredRegFlat(RegIndex idx, const TheISA::VecPredRegContainer &val) override
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
void regStats(const std::string &name) override
void setStatus(Status new_status) override
RegVal readVecElemFlat(RegIndex idx, const ElemIndex &elem_idx) const override
RegVal readMiscRegNoEffect(RegIndex misc_reg) const override
RegVal readFloatReg(RegIndex reg_idx) const override
InstDecoder * getDecoderPtr() override
void setVecElem(const RegId ®, RegVal val) override
unsigned readStCondFailures() const override
int threadId() const override
Returns this thread's ID number.
BaseMMU * getMMUPtr() override
void setCCReg(RegIndex reg_idx, RegVal val) override
void setFloatReg(RegIndex reg_idx, RegVal val) override
Process * getProcessPtr() override
Register ID: describe an architectural register with its class and index.
#define panic(...)
This implements a cprintf based panic() function.
void setThreadId(int id) override
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