gem5  v21.2.1.1
thread_context.hh
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41 
42 #ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__
43 #define __CPU_CHECKER_THREAD_CONTEXT_HH__
44 
45 #include "arch/generic/pcstate.hh"
46 #include "config/the_isa.hh"
47 #include "cpu/checker/cpu.hh"
48 #include "cpu/simple_thread.hh"
49 #include "cpu/thread_context.hh"
50 #include "debug/Checker.hh"
51 
52 namespace gem5
53 {
54 
55 namespace TheISA
56 {
57  class Decoder;
58 } // namespace TheISA
59 
68 template <class TC>
70 {
71  public:
72  CheckerThreadContext(TC *actual_tc,
73  CheckerCPU *checker_cpu)
74  : actualTC(actual_tc), checkerTC(checker_cpu->thread),
75  checkerCPU(checker_cpu)
76  { }
77 
78  private:
81  TC *actualTC;
88 
89  public:
90  bool
91  schedule(PCEvent *e) override
92  {
93  [[maybe_unused]] bool check_ret = checkerTC->schedule(e);
94  bool actual_ret = actualTC->schedule(e);
95  assert(actual_ret == check_ret);
96  return actual_ret;
97  }
98 
99  bool
100  remove(PCEvent *e) override
101  {
102  [[maybe_unused]] bool check_ret = checkerTC->remove(e);
103  bool actual_ret = actualTC->remove(e);
104  assert(actual_ret == check_ret);
105  return actual_ret;
106  }
107 
108  void
110  {
111  actualTC->scheduleInstCountEvent(event, count);
112  }
113  void
115  {
116  actualTC->descheduleInstCountEvent(event);
117  }
118  Tick
120  {
121  return actualTC->getCurrentInstCount();
122  }
123 
124  BaseCPU *getCpuPtr() override { return actualTC->getCpuPtr(); }
125 
126  uint32_t socketId() const override { return actualTC->socketId(); }
127 
128  int cpuId() const override { return actualTC->cpuId(); }
129 
130  ContextID contextId() const override { return actualTC->contextId(); }
131 
132  void
133  setContextId(ContextID id) override
134  {
135  actualTC->setContextId(id);
136  checkerTC->setContextId(id);
137  }
138 
140  int threadId() const override { return actualTC->threadId(); }
141  void
142  setThreadId(int id) override
143  {
144  checkerTC->setThreadId(id);
145  actualTC->setThreadId(id);
146  }
147 
148  BaseMMU *getMMUPtr() override { return actualTC->getMMUPtr(); }
149 
150  CheckerCPU *
151  getCheckerCpuPtr() override
152  {
153  return checkerCPU;
154  }
155 
156  BaseISA *getIsaPtr() override { return actualTC->getIsaPtr(); }
157 
158  InstDecoder *
159  getDecoderPtr() override
160  {
161  return actualTC->getDecoderPtr();
162  }
163 
164  System *getSystemPtr() override { return actualTC->getSystemPtr(); }
165 
166  Process *getProcessPtr() override { return actualTC->getProcessPtr(); }
167 
168  void setProcessPtr(Process *p) override { actualTC->setProcessPtr(p); }
169 
170  void
172  {
173  actualTC->connectMemPorts(tc);
174  }
175 
176  Status status() const override { return actualTC->status(); }
177 
178  void
179  setStatus(Status new_status) override
180  {
181  actualTC->setStatus(new_status);
182  checkerTC->setStatus(new_status);
183  }
184 
186  void activate() override { actualTC->activate(); }
187 
189  void suspend() override { actualTC->suspend(); }
190 
192  void halt() override { actualTC->halt(); }
193 
194  void
195  takeOverFrom(ThreadContext *oldContext) override
196  {
197  actualTC->takeOverFrom(oldContext);
198  checkerTC->copyState(oldContext);
199  }
200 
201  void
202  regStats(const std::string &name) override
203  {
204  actualTC->regStats(name);
206  }
207 
208  Tick readLastActivate() override { return actualTC->readLastActivate(); }
209  Tick readLastSuspend() override { return actualTC->readLastSuspend(); }
210 
211  // @todo: Do I need this?
212  void
214  {
215  actualTC->copyArchRegs(tc);
216  checkerTC->copyArchRegs(tc);
217  }
218 
219  void
220  clearArchRegs() override
221  {
222  actualTC->clearArchRegs();
224  }
225 
226  //
227  // New accessors for new decoder.
228  //
229  RegVal
230  readIntReg(RegIndex reg_idx) const override
231  {
232  return actualTC->readIntReg(reg_idx);
233  }
234 
235  RegVal
236  readFloatReg(RegIndex reg_idx) const override
237  {
238  return actualTC->readFloatReg(reg_idx);
239  }
240 
242  readVecReg (const RegId &reg) const override
243  {
244  return actualTC->readVecReg(reg);
245  }
246 
251  getWritableVecReg (const RegId &reg) override
252  {
253  return actualTC->getWritableVecReg(reg);
254  }
255 
256  RegVal
257  readVecElem(const RegId& reg) const override
258  {
259  return actualTC->readVecElem(reg);
260  }
261 
263  readVecPredReg(const RegId& reg) const override
264  {
265  return actualTC->readVecPredReg(reg);
266  }
267 
269  getWritableVecPredReg(const RegId& reg) override
270  {
271  return actualTC->getWritableVecPredReg(reg);
272  }
273 
274  RegVal
275  readCCReg(RegIndex reg_idx) const override
276  {
277  return actualTC->readCCReg(reg_idx);
278  }
279 
280  void
281  setIntReg(RegIndex reg_idx, RegVal val) override
282  {
283  actualTC->setIntReg(reg_idx, val);
284  checkerTC->setIntReg(reg_idx, val);
285  }
286 
287  void
288  setFloatReg(RegIndex reg_idx, RegVal val) override
289  {
290  actualTC->setFloatReg(reg_idx, val);
291  checkerTC->setFloatReg(reg_idx, val);
292  }
293 
294  void
295  setVecReg(const RegId& reg, const TheISA::VecRegContainer& val) override
296  {
297  actualTC->setVecReg(reg, val);
299  }
300 
301  void
302  setVecElem(const RegId& reg, RegVal val) override
303  {
304  actualTC->setVecElem(reg, val);
306  }
307 
308  void
310  const TheISA::VecPredRegContainer& val) override
311  {
312  actualTC->setVecPredReg(reg, val);
314  }
315 
316  void
317  setCCReg(RegIndex reg_idx, RegVal val) override
318  {
319  actualTC->setCCReg(reg_idx, val);
320  checkerTC->setCCReg(reg_idx, val);
321  }
322 
324  const PCStateBase &pcState() const override { return actualTC->pcState(); }
325 
327  void
328  pcState(const PCStateBase &val) override
329  {
330  DPRINTF(Checker, "Changing PC to %s, old PC %s\n",
331  val, checkerTC->pcState());
334  return actualTC->pcState(val);
335  }
336 
337  void
338  pcStateNoRecord(const PCStateBase &val) override
339  {
340  return actualTC->pcState(val);
341  }
342 
343  RegVal
344  readMiscRegNoEffect(RegIndex misc_reg) const override
345  {
346  return actualTC->readMiscRegNoEffect(misc_reg);
347  }
348 
349  RegVal
350  readMiscReg(RegIndex misc_reg) override
351  {
352  return actualTC->readMiscReg(misc_reg);
353  }
354 
355  void
356  setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
357  {
358  DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker"
359  " and O3..\n", misc_reg);
360  checkerTC->setMiscRegNoEffect(misc_reg, val);
361  actualTC->setMiscRegNoEffect(misc_reg, val);
362  }
363 
364  void
365  setMiscReg(RegIndex misc_reg, RegVal val) override
366  {
367  DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
368  " and O3..\n", misc_reg);
369  checkerTC->setMiscReg(misc_reg, val);
370  actualTC->setMiscReg(misc_reg, val);
371  }
372 
373  RegId
374  flattenRegId(const RegId& regId) const override
375  {
376  return actualTC->flattenRegId(regId);
377  }
378 
379  unsigned
380  readStCondFailures() const override
381  {
382  return actualTC->readStCondFailures();
383  }
384 
385  void
386  setStCondFailures(unsigned sc_failures) override
387  {
388  actualTC->setStCondFailures(sc_failures);
389  }
390 
391  RegVal
392  readIntRegFlat(RegIndex idx) const override
393  {
394  return actualTC->readIntRegFlat(idx);
395  }
396 
397  void
399  {
400  actualTC->setIntRegFlat(idx, val);
401  }
402 
403  RegVal
404  readFloatRegFlat(RegIndex idx) const override
405  {
406  return actualTC->readFloatRegFlat(idx);
407  }
408 
409  void
411  {
412  actualTC->setFloatRegFlat(idx, val);
413  }
414 
416  readVecRegFlat(RegIndex idx) const override
417  {
418  return actualTC->readVecRegFlat(idx);
419  }
420 
426  {
427  return actualTC->getWritableVecRegFlat(idx);
428  }
429 
430  void
432  {
433  actualTC->setVecRegFlat(idx, val);
434  }
435 
436  RegVal
437  readVecElemFlat(RegIndex idx, const ElemIndex& elem_idx) const override
438  {
439  return actualTC->readVecElemFlat(idx, elem_idx);
440  }
441 
442  void
443  setVecElemFlat(RegIndex idx, const ElemIndex& elem_idx,
444  RegVal val) override
445  {
446  actualTC->setVecElemFlat(idx, elem_idx, val);
447  }
448 
450  readVecPredRegFlat(RegIndex idx) const override
451  {
452  return actualTC->readVecPredRegFlat(idx);
453  }
454 
457  {
458  return actualTC->getWritableVecPredRegFlat(idx);
459  }
460 
461  void
463  const TheISA::VecPredRegContainer& val) override
464  {
465  actualTC->setVecPredRegFlat(idx, val);
466  }
467 
468  RegVal
469  readCCRegFlat(RegIndex idx) const override
470  {
471  return actualTC->readCCRegFlat(idx);
472  }
473 
474  void
476  {
477  actualTC->setCCRegFlat(idx, val);
478  }
479 
480  // hardware transactional memory
481  void
482  htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) override
483  {
484  panic("function not implemented");
485  }
486 
489  {
490  return actualTC->getHtmCheckpointPtr();
491  }
492 
493  void
495  {
496  panic("function not implemented");
497  }
498 
499 };
500 
501 } // namespace gem5
502 
503 #endif // __CPU_CHECKER_EXEC_CONTEXT_HH__
gem5::CheckerThreadContext::getWritableVecRegFlat
TheISA::VecRegContainer & getWritableVecRegFlat(RegIndex idx) override
Read vector register for modification, flat indexing.
Definition: thread_context.hh:425
gem5::CheckerThreadContext::setIntReg
void setIntReg(RegIndex reg_idx, RegVal val) override
Definition: thread_context.hh:281
gem5::CheckerThreadContext::readIntRegFlat
RegVal readIntRegFlat(RegIndex idx) const override
Flat register interfaces.
Definition: thread_context.hh:392
gem5::CheckerThreadContext::cpuId
int cpuId() const override
Definition: thread_context.hh:128
gem5::CheckerThreadContext::CheckerThreadContext
CheckerThreadContext(TC *actual_tc, CheckerCPU *checker_cpu)
Definition: thread_context.hh:72
gem5::BaseHTMCheckpointPtr
std::unique_ptr< BaseHTMCheckpoint > BaseHTMCheckpointPtr
Definition: htm.hh:125
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::CheckerThreadContext::setMiscReg
void setMiscReg(RegIndex misc_reg, RegVal val) override
Definition: thread_context.hh:365
gem5::SimpleThread::setIntReg
void setIntReg(RegIndex reg_idx, RegVal val) override
Definition: simple_thread.hh:359
gem5::CheckerThreadContext::getCurrentInstCount
Tick getCurrentInstCount() override
Definition: thread_context.hh:119
gem5::ArmISA::VecPredRegContainer
VecPredReg::Container VecPredRegContainer
Definition: vec.hh:68
gem5::HtmFailureFaultCause
HtmFailureFaultCause
Definition: htm.hh:47
gem5::CheckerThreadContext::readVecPredReg
const TheISA::VecPredRegContainer & readVecPredReg(const RegId &reg) const override
Definition: thread_context.hh:263
gem5::CheckerThreadContext::halt
void halt() override
Set the status to Halted.
Definition: thread_context.hh:192
gem5::CheckerThreadContext::readVecElem
RegVal readVecElem(const RegId &reg) const override
Definition: thread_context.hh:257
gem5::CheckerThreadContext::descheduleInstCountEvent
void descheduleInstCountEvent(Event *event) override
Definition: thread_context.hh:114
gem5::CheckerThreadContext::pcState
const PCStateBase & pcState() const override
Reads this thread's PC state.
Definition: thread_context.hh:324
gem5::CheckerThreadContext::setIntRegFlat
void setIntRegFlat(RegIndex idx, RegVal val) override
Definition: thread_context.hh:398
gem5::CheckerThreadContext::socketId
uint32_t socketId() const override
Definition: thread_context.hh:126
gem5::SimpleThread::copyArchRegs
void copyArchRegs(ThreadContext *tc) override
Definition: simple_thread.cc:167
gem5::CheckerThreadContext::setVecElemFlat
void setVecElemFlat(RegIndex idx, const ElemIndex &elem_idx, RegVal val) override
Definition: thread_context.hh:443
gem5::MipsISA::event
Bitfield< 10, 5 > event
Definition: pra_constants.hh:300
gem5::CheckerThreadContext::checkerTC
SimpleThread * checkerTC
The checker's own SimpleThread.
Definition: thread_context.hh:85
gem5::ArmISA::e
Bitfield< 9 > e
Definition: misc_types.hh:65
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::SimpleThread::setMiscReg
void setMiscReg(RegIndex misc_reg, RegVal val) override
Definition: simple_thread.hh:453
gem5::ThreadContext::Status
Status
Definition: thread_context.hh:105
gem5::CheckerThreadContext::setMiscRegNoEffect
void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
Definition: thread_context.hh:356
gem5::SimpleThread::setVecReg
void setVecReg(const RegId &reg, const TheISA::VecRegContainer &val) override
Definition: simple_thread.hh:382
gem5::SimpleThread::remove
bool remove(PCEvent *e) override
Definition: simple_thread.hh:182
gem5::CheckerThreadContext::setCCRegFlat
void setCCRegFlat(RegIndex idx, RegVal val) override
Definition: thread_context.hh:475
gem5::SimpleThread::clearArchRegs
void clearArchRegs() override
Definition: simple_thread.hh:249
gem5::ThreadContext::regStats
virtual void regStats(const std::string &name)
Definition: thread_context.hh:178
gem5::SimpleThread::setContextId
void setContextId(ContextID id) override
Definition: simple_thread.hh:207
gem5::CheckerThreadContext::remove
bool remove(PCEvent *e) override
Definition: thread_context.hh:100
gem5::CheckerThreadContext::actualTC
TC * actualTC
The main CPU's ThreadContext, or class that implements the ThreadContext interface.
Definition: thread_context.hh:81
gem5::CheckerThreadContext
Derived ThreadContext class for use with the Checker.
Definition: thread_context.hh:69
gem5::CheckerThreadContext::scheduleInstCountEvent
void scheduleInstCountEvent(Event *event, Tick count) override
Definition: thread_context.hh:109
gem5::CheckerThreadContext::readMiscReg
RegVal readMiscReg(RegIndex misc_reg) override
Definition: thread_context.hh:350
gem5::CheckerThreadContext::setVecReg
void setVecReg(const RegId &reg, const TheISA::VecRegContainer &val) override
Definition: thread_context.hh:295
gem5::SimpleThread
The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interf...
Definition: simple_thread.hh:93
gem5::SimpleThread::setThreadId
void setThreadId(int id) override
Definition: simple_thread.hh:205
gem5::SimpleThread::setVecPredReg
void setVecPredReg(const RegId &reg, const TheISA::VecPredRegContainer &val) override
Definition: simple_thread.hh:402
gem5::CheckerThreadContext::readIntReg
RegVal readIntReg(RegIndex reg_idx) const override
Definition: thread_context.hh:230
gem5::BaseMMU
Definition: mmu.hh:53
gem5::CheckerThreadContext::readLastActivate
Tick readLastActivate() override
Definition: thread_context.hh:208
gem5::CheckerThreadContext::getSystemPtr
System * getSystemPtr() override
Definition: thread_context.hh:164
gem5::CheckerThreadContext::flattenRegId
RegId flattenRegId(const RegId &regId) const override
Definition: thread_context.hh:374
gem5::CheckerThreadContext::getCpuPtr
BaseCPU * getCpuPtr() override
Definition: thread_context.hh:124
gem5::CheckerThreadContext::setFloatRegFlat
void setFloatRegFlat(RegIndex idx, RegVal val) override
Definition: thread_context.hh:410
gem5::CheckerThreadContext::suspend
void suspend() override
Set the status to Suspended.
Definition: thread_context.hh:189
gem5::CheckerThreadContext::readCCRegFlat
RegVal readCCRegFlat(RegIndex idx) const override
Definition: thread_context.hh:469
gem5::CheckerThreadContext::getCheckerCpuPtr
CheckerCPU * getCheckerCpuPtr() override
Definition: thread_context.hh:151
gem5::CheckerThreadContext::readLastSuspend
Tick readLastSuspend() override
Definition: thread_context.hh:209
gem5::CheckerThreadContext::readVecRegFlat
const TheISA::VecRegContainer & readVecRegFlat(RegIndex idx) const override
Definition: thread_context.hh:416
gem5::System
Definition: system.hh:75
gem5::CheckerThreadContext::takeOverFrom
void takeOverFrom(ThreadContext *oldContext) override
Definition: thread_context.hh:195
gem5::SimpleThread::copyState
void copyState(ThreadContext *oldContext)
Definition: simple_thread.cc:107
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::CheckerThreadContext::clearArchRegs
void clearArchRegs() override
Definition: thread_context.hh:220
gem5::InstDecoder
Definition: decoder.hh:42
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::CheckerThreadContext::connectMemPorts
void connectMemPorts(ThreadContext *tc)
Definition: thread_context.hh:171
gem5::Event
Definition: eventq.hh:251
gem5::X86ISA::count
count
Definition: misc.hh:709
gem5::CheckerThreadContext::getIsaPtr
BaseISA * getIsaPtr() override
Definition: thread_context.hh:156
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::PCEvent
Definition: pc_event.hh:45
gem5::CheckerCPU
CheckerCPU class.
Definition: cpu.hh:84
gem5::SimpleThread::setMiscRegNoEffect
void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
Definition: simple_thread.hh:447
cpu.hh
gem5::CheckerThreadContext::readCCReg
RegVal readCCReg(RegIndex reg_idx) const override
Definition: thread_context.hh:275
gem5::ArmISA::Decoder
Definition: decoder.hh:63
gem5::CheckerThreadContext::getWritableVecReg
TheISA::VecRegContainer & getWritableVecReg(const RegId &reg) override
Read vector register for modification, hierarchical indexing.
Definition: thread_context.hh:251
gem5::CheckerThreadContext::setHtmCheckpointPtr
void setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) override
Definition: thread_context.hh:494
gem5::CheckerThreadContext::setProcessPtr
void setProcessPtr(Process *p) override
Definition: thread_context.hh:168
gem5::CheckerThreadContext::copyArchRegs
void copyArchRegs(ThreadContext *tc) override
Definition: thread_context.hh:213
gem5::ArmISA::VecRegContainer
gem5::VecRegContainer< NumVecElemPerVecReg *sizeof(VecElem)> VecRegContainer
Definition: vec.hh:62
gem5::SimpleThread::schedule
bool schedule(PCEvent *e) override
Definition: simple_thread.hh:181
gem5::CheckerThreadContext::contextId
ContextID contextId() const override
Definition: thread_context.hh:130
gem5::CheckerThreadContext::htmAbortTransaction
void htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) override
Definition: thread_context.hh:482
gem5::SimpleThread::pcState
const PCStateBase & pcState() const override
Definition: simple_thread.hh:422
gem5::CheckerCPU::recordPCChange
void recordPCChange(const PCStateBase &val)
Definition: cpu.hh:420
gem5::SimpleThread::setFloatReg
void setFloatReg(RegIndex reg_idx, RegVal val) override
Definition: simple_thread.hh:369
gem5::ElemIndex
uint16_t ElemIndex
Logical vector register elem index type.
Definition: types.hh:179
name
const std::string & name()
Definition: trace.cc:49
gem5::SimpleThread::setStatus
void setStatus(Status newStatus) override
Definition: simple_thread.hh:224
gem5::CheckerThreadContext::checkerCPU
CheckerCPU * checkerCPU
Pointer to the checker CPU.
Definition: thread_context.hh:87
gem5::CheckerThreadContext::pcStateNoRecord
void pcStateNoRecord(const PCStateBase &val) override
Definition: thread_context.hh:338
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::Process
Definition: process.hh:68
pcstate.hh
gem5::CheckerThreadContext::setVecPredReg
void setVecPredReg(const RegId &reg, const TheISA::VecPredRegContainer &val) override
Definition: thread_context.hh:309
simple_thread.hh
gem5::CheckerThreadContext::readVecReg
const TheISA::VecRegContainer & readVecReg(const RegId &reg) const override
Definition: thread_context.hh:242
gem5::SimpleThread::setVecElem
void setVecElem(const RegId &reg, RegVal val) override
Definition: simple_thread.hh:392
gem5::CheckerThreadContext::readFloatRegFlat
RegVal readFloatRegFlat(RegIndex idx) const override
Definition: thread_context.hh:404
gem5::CheckerThreadContext::pcState
void pcState(const PCStateBase &val) override
Sets this thread's PC state.
Definition: thread_context.hh:328
gem5::CheckerThreadContext::schedule
bool schedule(PCEvent *e) override
Definition: thread_context.hh:91
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:246
gem5::CheckerThreadContext::setCCReg
void setCCReg(RegIndex reg_idx, RegVal val) override
Definition: thread_context.hh:317
gem5::CheckerThreadContext::status
Status status() const override
Definition: thread_context.hh:176
gem5::CheckerThreadContext::readVecPredRegFlat
const TheISA::VecPredRegContainer & readVecPredRegFlat(RegIndex idx) const override
Definition: thread_context.hh:450
gem5::CheckerThreadContext::getHtmCheckpointPtr
BaseHTMCheckpointPtr & getHtmCheckpointPtr() override
Definition: thread_context.hh:488
gem5::CheckerThreadContext::activate
void activate() override
Set the status to Active.
Definition: thread_context.hh:186
gem5::CheckerThreadContext::getWritableVecPredRegFlat
TheISA::VecPredRegContainer & getWritableVecPredRegFlat(RegIndex idx) override
Definition: thread_context.hh:456
gem5::CheckerThreadContext::setContextId
void setContextId(ContextID id) override
Definition: thread_context.hh:133
gem5::CheckerThreadContext::getWritableVecPredReg
TheISA::VecPredRegContainer & getWritableVecPredReg(const RegId &reg) override
Definition: thread_context.hh:269
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::BaseISA
Definition: isa.hh:57
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::CheckerThreadContext::setStCondFailures
void setStCondFailures(unsigned sc_failures) override
Definition: thread_context.hh:386
gem5::CheckerThreadContext::setVecRegFlat
void setVecRegFlat(RegIndex idx, const TheISA::VecRegContainer &val) override
Definition: thread_context.hh:431
gem5::CheckerThreadContext::setVecPredRegFlat
void setVecPredRegFlat(RegIndex idx, const TheISA::VecPredRegContainer &val) override
Definition: thread_context.hh:462
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::CheckerThreadContext::regStats
void regStats(const std::string &name) override
Definition: thread_context.hh:202
gem5::CheckerThreadContext::setStatus
void setStatus(Status new_status) override
Definition: thread_context.hh:179
gem5::CheckerThreadContext::readVecElemFlat
RegVal readVecElemFlat(RegIndex idx, const ElemIndex &elem_idx) const override
Definition: thread_context.hh:437
gem5::CheckerThreadContext::readMiscRegNoEffect
RegVal readMiscRegNoEffect(RegIndex misc_reg) const override
Definition: thread_context.hh:344
gem5::Checker
Templated Checker class.
Definition: cpu.hh:531
gem5::CheckerThreadContext::readFloatReg
RegVal readFloatReg(RegIndex reg_idx) const override
Definition: thread_context.hh:236
gem5::CheckerThreadContext::getDecoderPtr
InstDecoder * getDecoderPtr() override
Definition: thread_context.hh:159
thread_context.hh
gem5::CheckerThreadContext::setVecElem
void setVecElem(const RegId &reg, RegVal val) override
Definition: thread_context.hh:302
gem5::CheckerThreadContext::readStCondFailures
unsigned readStCondFailures() const override
Definition: thread_context.hh:380
gem5::CheckerThreadContext::threadId
int threadId() const override
Returns this thread's ID number.
Definition: thread_context.hh:140
gem5::CheckerThreadContext::getMMUPtr
BaseMMU * getMMUPtr() override
Definition: thread_context.hh:148
gem5::SimpleThread::setCCReg
void setCCReg(RegIndex reg_idx, RegVal val) override
Definition: simple_thread.hh:413
gem5::CheckerThreadContext::setFloatReg
void setFloatReg(RegIndex reg_idx, RegVal val) override
Definition: thread_context.hh:288
gem5::CheckerThreadContext::getProcessPtr
Process * getProcessPtr() override
Definition: thread_context.hh:166
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:113
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::CheckerThreadContext::setThreadId
void setThreadId(int id) override
Definition: thread_context.hh:142

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