gem5 v24.0.0.0
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thread_context.hh
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1/*
2 * Copyright (c) 2011-2012, 2016-2018, 2020-2021 Arm Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
42#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__
43#define __CPU_CHECKER_THREAD_CONTEXT_HH__
44
46#include "cpu/checker/cpu.hh"
47#include "cpu/simple_thread.hh"
48#include "cpu/thread_context.hh"
49#include "debug/Checker.hh"
50
51namespace gem5
52{
53
62template <class TC>
64{
65 public:
66 CheckerThreadContext(TC *actual_tc,
67 CheckerCPU *checker_cpu)
68 : actualTC(actual_tc), checkerTC(checker_cpu->thread),
69 checkerCPU(checker_cpu)
70 { }
71
72 private:
82
83 public:
84 bool
85 schedule(PCEvent *e) override
86 {
87 [[maybe_unused]] bool check_ret = checkerTC->schedule(e);
88 bool actual_ret = actualTC->schedule(e);
89 assert(actual_ret == check_ret);
90 return actual_ret;
91 }
92
93 bool
94 remove(PCEvent *e) override
95 {
96 [[maybe_unused]] bool check_ret = checkerTC->remove(e);
97 bool actual_ret = actualTC->remove(e);
98 assert(actual_ret == check_ret);
99 return actual_ret;
100 }
101
102 void
104 {
105 actualTC->scheduleInstCountEvent(event, count);
106 }
107 void
109 {
110 actualTC->descheduleInstCountEvent(event);
111 }
112 Tick
114 {
115 return actualTC->getCurrentInstCount();
116 }
117
118 BaseCPU *getCpuPtr() override { return actualTC->getCpuPtr(); }
119
120 uint32_t socketId() const override { return actualTC->socketId(); }
121
122 int cpuId() const override { return actualTC->cpuId(); }
123
124 ContextID contextId() const override { return actualTC->contextId(); }
125
126 void
128 {
129 actualTC->setContextId(id);
131 }
132
134 int threadId() const override { return actualTC->threadId(); }
135 void
136 setThreadId(int id) override
137 {
139 actualTC->setThreadId(id);
140 }
141
142 BaseMMU *getMMUPtr() override { return actualTC->getMMUPtr(); }
143
144 CheckerCPU *
146 {
147 return checkerCPU;
148 }
149
150 BaseISA *getIsaPtr() const override { return actualTC->getIsaPtr(); }
151
153 getDecoderPtr() override
154 {
155 return actualTC->getDecoderPtr();
156 }
157
158 System *getSystemPtr() override { return actualTC->getSystemPtr(); }
159
160 Process *getProcessPtr() override { return actualTC->getProcessPtr(); }
161
162 void setProcessPtr(Process *p) override { actualTC->setProcessPtr(p); }
163
164 void
166 {
167 actualTC->connectMemPorts(tc);
168 }
169
170 Status status() const override { return actualTC->status(); }
171
172 void
173 setStatus(Status new_status) override
174 {
175 actualTC->setStatus(new_status);
176 checkerTC->setStatus(new_status);
177 }
178
180 void activate() override { actualTC->activate(); }
181
183 void suspend() override { actualTC->suspend(); }
184
186 void halt() override { actualTC->halt(); }
187
188 void
189 takeOverFrom(ThreadContext *oldContext) override
190 {
191 actualTC->takeOverFrom(oldContext);
192 checkerTC->copyState(oldContext);
193 }
194
195 void
196 regStats(const std::string &name) override
197 {
198 actualTC->regStats(name);
200 }
201
202 Tick readLastActivate() override { return actualTC->readLastActivate(); }
203 Tick readLastSuspend() override { return actualTC->readLastSuspend(); }
204
205 // @todo: Do I need this?
206 void
208 {
209 actualTC->copyArchRegs(tc);
211 }
212
213 void
214 clearArchRegs() override
215 {
216 actualTC->clearArchRegs();
218 }
219
220 //
221 // New accessors for new decoder.
222 //
223 RegVal
224 getReg(const RegId &reg) const override
225 {
226 return actualTC->getReg(reg);
227 }
228
229 void
230 getReg(const RegId &reg, void *val) const override
231 {
232 actualTC->getReg(reg, val);
233 }
234
235 void *
236 getWritableReg(const RegId &reg) override
237 {
238 return actualTC->getWritableReg(reg);
239 }
240
241 void
242 setReg(const RegId &reg, RegVal val) override
243 {
244 actualTC->setReg(reg, val);
246 }
247
248 void
249 setReg(const RegId &reg, const void *val) override
250 {
251 actualTC->setReg(reg, val);
253 }
254
256 const PCStateBase &pcState() const override { return actualTC->pcState(); }
257
259 void
260 pcState(const PCStateBase &val) override
261 {
262 DPRINTF(Checker, "Changing PC to %s, old PC %s\n",
263 val, checkerTC->pcState());
266 return actualTC->pcState(val);
267 }
268
269 void
271 {
272 return actualTC->pcState(val);
273 }
274
275 RegVal
276 readMiscRegNoEffect(RegIndex misc_reg) const override
277 {
278 return actualTC->readMiscRegNoEffect(misc_reg);
279 }
280
281 RegVal
282 readMiscReg(RegIndex misc_reg) override
283 {
284 return actualTC->readMiscReg(misc_reg);
285 }
286
287 void
289 {
290 DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker"
291 " and O3..\n", misc_reg);
292 checkerTC->setMiscRegNoEffect(misc_reg, val);
293 actualTC->setMiscRegNoEffect(misc_reg, val);
294 }
295
296 void
297 setMiscReg(RegIndex misc_reg, RegVal val) override
298 {
299 DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
300 " and O3..\n", misc_reg);
301 checkerTC->setMiscReg(misc_reg, val);
302 actualTC->setMiscReg(misc_reg, val);
303 }
304
305 unsigned
306 readStCondFailures() const override
307 {
308 return actualTC->readStCondFailures();
309 }
310
311 void
312 setStCondFailures(unsigned sc_failures) override
313 {
314 actualTC->setStCondFailures(sc_failures);
315 }
316
317 // hardware transactional memory
318 void
319 htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) override
320 {
321 panic("function not implemented");
322 }
323
326 {
327 return actualTC->getHtmCheckpointPtr();
328 }
329
330 void
332 {
333 panic("function not implemented");
334 }
335
336};
337
338} // namespace gem5
339
340#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__
#define DPRINTF(x,...)
Definition trace.hh:210
CheckerCPU class.
Definition cpu.hh:85
void recordPCChange(const PCStateBase &val)
Definition cpu.hh:336
Derived ThreadContext class for use with the Checker.
int cpuId() const override
void connectMemPorts(ThreadContext *tc)
uint32_t socketId() const override
BaseMMU * getMMUPtr() override
bool schedule(PCEvent *e) override
void setContextId(ContextID id) override
void htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) override
RegVal readMiscRegNoEffect(RegIndex misc_reg) const override
void takeOverFrom(ThreadContext *oldContext) override
CheckerThreadContext(TC *actual_tc, CheckerCPU *checker_cpu)
void setStCondFailures(unsigned sc_failures) override
void halt() override
Set the status to Halted.
void setThreadId(int id) override
void setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) override
void pcStateNoRecord(const PCStateBase &val) override
void pcState(const PCStateBase &val) override
Sets this thread's PC state.
System * getSystemPtr() override
Status status() const override
CheckerCPU * checkerCPU
Pointer to the checker CPU.
void regStats(const std::string &name) override
InstDecoder * getDecoderPtr() override
TC * actualTC
The main CPU's ThreadContext, or class that implements the ThreadContext interface.
ContextID contextId() const override
bool remove(PCEvent *e) override
void setReg(const RegId &reg, RegVal val) override
RegVal getReg(const RegId &reg) const override
Process * getProcessPtr() override
void setMiscReg(RegIndex misc_reg, RegVal val) override
SimpleThread * checkerTC
The checker's own SimpleThread.
BaseHTMCheckpointPtr & getHtmCheckpointPtr() override
BaseISA * getIsaPtr() const override
void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
void copyArchRegs(ThreadContext *tc) override
const PCStateBase & pcState() const override
Reads this thread's PC state.
void * getWritableReg(const RegId &reg) override
Tick getCurrentInstCount() override
void setReg(const RegId &reg, const void *val) override
void activate() override
Set the status to Active.
RegVal readMiscReg(RegIndex misc_reg) override
void getReg(const RegId &reg, void *val) const override
CheckerCPU * getCheckerCpuPtr() override
void scheduleInstCountEvent(Event *event, Tick count) override
void setStatus(Status new_status) override
void setProcessPtr(Process *p) override
unsigned readStCondFailures() const override
BaseCPU * getCpuPtr() override
void suspend() override
Set the status to Suspended.
void descheduleInstCountEvent(Event *event) override
int threadId() const override
Returns this thread's ID number.
Templated Checker class.
Definition cpu.hh:77
Register ID: describe an architectural register with its class and index.
Definition reg_class.hh:94
The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interf...
void setContextId(ContextID id) override
bool remove(PCEvent *e) override
const PCStateBase & pcState() const override
void setMiscReg(RegIndex misc_reg, RegVal val) override
void copyState(ThreadContext *oldContext)
void copyArchRegs(ThreadContext *tc) override
void clearArchRegs() override
void setStatus(Status newStatus) override
void setThreadId(int id) override
void setReg(const RegId &arch_reg, RegVal val) override
bool schedule(PCEvent *e) override
void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
ThreadContext is the external interface to all thread state for anything outside of the CPU.
virtual void regStats(const std::string &name)
#define panic(...)
This implements a cprintf based panic() function.
Definition logging.hh:188
Bitfield< 9 > e
Definition misc_types.hh:65
Bitfield< 10, 5 > event
Bitfield< 0 > p
Bitfield< 5, 3 > reg
Definition types.hh:92
Bitfield< 63 > val
Definition misc.hh:804
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
uint16_t RegIndex
Definition types.hh:176
uint64_t RegVal
Definition types.hh:173
uint64_t Tick
Tick count type.
Definition types.hh:58
int ContextID
Globally unique thread context ID.
Definition types.hh:239
std::unique_ptr< BaseHTMCheckpoint > BaseHTMCheckpointPtr
Definition htm.hh:127
HtmFailureFaultCause
Definition htm.hh:48
const std::string & name()
Definition trace.cc:48

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