gem5  v21.1.0.2
thread_context.hh
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41 
42 #ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__
43 #define __CPU_CHECKER_THREAD_CONTEXT_HH__
44 
45 #include "arch/pcstate.hh"
46 #include "config/the_isa.hh"
47 #include "cpu/checker/cpu.hh"
48 #include "cpu/simple_thread.hh"
49 #include "cpu/thread_context.hh"
50 #include "debug/Checker.hh"
51 
52 namespace gem5
53 {
54 
55 namespace TheISA
56 {
57  class Decoder;
58 } // namespace TheISA
59 
68 template <class TC>
70 {
71  public:
72  CheckerThreadContext(TC *actual_tc,
73  CheckerCPU *checker_cpu)
74  : actualTC(actual_tc), checkerTC(checker_cpu->thread),
75  checkerCPU(checker_cpu)
76  { }
77 
78  private:
81  TC *actualTC;
88 
89  public:
90  bool
91  schedule(PCEvent *e) override
92  {
93  GEM5_VAR_USED bool check_ret = checkerTC->schedule(e);
94  bool actual_ret = actualTC->schedule(e);
95  assert(actual_ret == check_ret);
96  return actual_ret;
97  }
98 
99  bool
100  remove(PCEvent *e) override
101  {
102  GEM5_VAR_USED bool check_ret = checkerTC->remove(e);
103  bool actual_ret = actualTC->remove(e);
104  assert(actual_ret == check_ret);
105  return actual_ret;
106  }
107 
108  void
110  {
111  actualTC->scheduleInstCountEvent(event, count);
112  }
113  void
115  {
116  actualTC->descheduleInstCountEvent(event);
117  }
118  Tick
120  {
121  return actualTC->getCurrentInstCount();
122  }
123 
124  BaseCPU *getCpuPtr() override { return actualTC->getCpuPtr(); }
125 
126  uint32_t socketId() const override { return actualTC->socketId(); }
127 
128  int cpuId() const override { return actualTC->cpuId(); }
129 
130  ContextID contextId() const override { return actualTC->contextId(); }
131 
132  void
133  setContextId(ContextID id) override
134  {
135  actualTC->setContextId(id);
136  checkerTC->setContextId(id);
137  }
138 
140  int threadId() const override { return actualTC->threadId(); }
141  void
142  setThreadId(int id) override
143  {
144  checkerTC->setThreadId(id);
145  actualTC->setThreadId(id);
146  }
147 
148  BaseMMU *getMMUPtr() override { return actualTC->getMMUPtr(); }
149 
150  CheckerCPU *
151  getCheckerCpuPtr() override
152  {
153  return checkerCPU;
154  }
155 
156  BaseISA *getIsaPtr() override { return actualTC->getIsaPtr(); }
157 
158  TheISA::Decoder *
159  getDecoderPtr() override
160  {
161  return actualTC->getDecoderPtr();
162  }
163 
164  System *getSystemPtr() override { return actualTC->getSystemPtr(); }
165 
166  Process *getProcessPtr() override { return actualTC->getProcessPtr(); }
167 
168  void setProcessPtr(Process *p) override { actualTC->setProcessPtr(p); }
169 
170  PortProxy &
171  getVirtProxy() override
172  {
173  return actualTC->getVirtProxy();
174  }
175 
176  void
178  {
179  actualTC->initMemProxies(tc);
180  }
181 
182  void
184  {
185  actualTC->connectMemPorts(tc);
186  }
187 
188  Status status() const override { return actualTC->status(); }
189 
190  void
191  setStatus(Status new_status) override
192  {
193  actualTC->setStatus(new_status);
194  checkerTC->setStatus(new_status);
195  }
196 
198  void activate() override { actualTC->activate(); }
199 
201  void suspend() override { actualTC->suspend(); }
202 
204  void halt() override { actualTC->halt(); }
205 
206  void
207  takeOverFrom(ThreadContext *oldContext) override
208  {
209  actualTC->takeOverFrom(oldContext);
210  checkerTC->copyState(oldContext);
211  }
212 
213  void
214  regStats(const std::string &name) override
215  {
216  actualTC->regStats(name);
218  }
219 
220  Tick readLastActivate() override { return actualTC->readLastActivate(); }
221  Tick readLastSuspend() override { return actualTC->readLastSuspend(); }
222 
223  // @todo: Do I need this?
224  void
226  {
227  actualTC->copyArchRegs(tc);
228  checkerTC->copyArchRegs(tc);
229  }
230 
231  void
232  clearArchRegs() override
233  {
234  actualTC->clearArchRegs();
236  }
237 
238  //
239  // New accessors for new decoder.
240  //
241  RegVal
242  readIntReg(RegIndex reg_idx) const override
243  {
244  return actualTC->readIntReg(reg_idx);
245  }
246 
247  RegVal
248  readFloatReg(RegIndex reg_idx) const override
249  {
250  return actualTC->readFloatReg(reg_idx);
251  }
252 
254  readVecReg (const RegId &reg) const override
255  {
256  return actualTC->readVecReg(reg);
257  }
258 
263  getWritableVecReg (const RegId &reg) override
264  {
265  return actualTC->getWritableVecReg(reg);
266  }
267 
268  const TheISA::VecElem &
269  readVecElem(const RegId& reg) const override
270  {
271  return actualTC->readVecElem(reg);
272  }
273 
275  readVecPredReg(const RegId& reg) const override
276  {
277  return actualTC->readVecPredReg(reg);
278  }
279 
281  getWritableVecPredReg(const RegId& reg) override
282  {
283  return actualTC->getWritableVecPredReg(reg);
284  }
285 
286  RegVal
287  readCCReg(RegIndex reg_idx) const override
288  {
289  return actualTC->readCCReg(reg_idx);
290  }
291 
292  void
293  setIntReg(RegIndex reg_idx, RegVal val) override
294  {
295  actualTC->setIntReg(reg_idx, val);
296  checkerTC->setIntReg(reg_idx, val);
297  }
298 
299  void
300  setFloatReg(RegIndex reg_idx, RegVal val) override
301  {
302  actualTC->setFloatReg(reg_idx, val);
303  checkerTC->setFloatReg(reg_idx, val);
304  }
305 
306  void
307  setVecReg(const RegId& reg, const TheISA::VecRegContainer& val) override
308  {
309  actualTC->setVecReg(reg, val);
311  }
312 
313  void
314  setVecElem(const RegId& reg, const TheISA::VecElem& val) override
315  {
316  actualTC->setVecElem(reg, val);
318  }
319 
320  void
322  const TheISA::VecPredRegContainer& val) override
323  {
324  actualTC->setVecPredReg(reg, val);
326  }
327 
328  void
329  setCCReg(RegIndex reg_idx, RegVal val) override
330  {
331  actualTC->setCCReg(reg_idx, val);
332  checkerTC->setCCReg(reg_idx, val);
333  }
334 
336  TheISA::PCState pcState() const override { return actualTC->pcState(); }
337 
339  void
340  pcState(const TheISA::PCState &val) override
341  {
342  DPRINTF(Checker, "Changing PC to %s, old PC %s\n",
343  val, checkerTC->pcState());
346  return actualTC->pcState(val);
347  }
348 
349  void
351  {
352  checkerTC->setNPC(val);
353  actualTC->setNPC(val);
354  }
355 
356  void
358  {
359  return actualTC->pcState(val);
360  }
361 
363  Addr instAddr() const override { return actualTC->instAddr(); }
364 
366  Addr nextInstAddr() const override { return actualTC->nextInstAddr(); }
367 
369  MicroPC microPC() const override { return actualTC->microPC(); }
370 
371  RegVal
372  readMiscRegNoEffect(RegIndex misc_reg) const override
373  {
374  return actualTC->readMiscRegNoEffect(misc_reg);
375  }
376 
377  RegVal
378  readMiscReg(RegIndex misc_reg) override
379  {
380  return actualTC->readMiscReg(misc_reg);
381  }
382 
383  void
384  setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
385  {
386  DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker"
387  " and O3..\n", misc_reg);
388  checkerTC->setMiscRegNoEffect(misc_reg, val);
389  actualTC->setMiscRegNoEffect(misc_reg, val);
390  }
391 
392  void
393  setMiscReg(RegIndex misc_reg, RegVal val) override
394  {
395  DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
396  " and O3..\n", misc_reg);
397  checkerTC->setMiscReg(misc_reg, val);
398  actualTC->setMiscReg(misc_reg, val);
399  }
400 
401  RegId
402  flattenRegId(const RegId& regId) const override
403  {
404  return actualTC->flattenRegId(regId);
405  }
406 
407  unsigned
408  readStCondFailures() const override
409  {
410  return actualTC->readStCondFailures();
411  }
412 
413  void
414  setStCondFailures(unsigned sc_failures) override
415  {
416  actualTC->setStCondFailures(sc_failures);
417  }
418 
419  RegVal
420  readIntRegFlat(RegIndex idx) const override
421  {
422  return actualTC->readIntRegFlat(idx);
423  }
424 
425  void
427  {
428  actualTC->setIntRegFlat(idx, val);
429  }
430 
431  RegVal
432  readFloatRegFlat(RegIndex idx) const override
433  {
434  return actualTC->readFloatRegFlat(idx);
435  }
436 
437  void
439  {
440  actualTC->setFloatRegFlat(idx, val);
441  }
442 
444  readVecRegFlat(RegIndex idx) const override
445  {
446  return actualTC->readVecRegFlat(idx);
447  }
448 
454  {
455  return actualTC->getWritableVecRegFlat(idx);
456  }
457 
458  void
460  {
461  actualTC->setVecRegFlat(idx, val);
462  }
463 
464  const TheISA::VecElem &
465  readVecElemFlat(RegIndex idx, const ElemIndex& elem_idx) const override
466  {
467  return actualTC->readVecElemFlat(idx, elem_idx);
468  }
469 
470  void
471  setVecElemFlat(RegIndex idx, const ElemIndex& elem_idx,
472  const TheISA::VecElem& val) override
473  {
474  actualTC->setVecElemFlat(idx, elem_idx, val);
475  }
476 
478  readVecPredRegFlat(RegIndex idx) const override
479  {
480  return actualTC->readVecPredRegFlat(idx);
481  }
482 
485  {
486  return actualTC->getWritableVecPredRegFlat(idx);
487  }
488 
489  void
491  const TheISA::VecPredRegContainer& val) override
492  {
493  actualTC->setVecPredRegFlat(idx, val);
494  }
495 
496  RegVal
497  readCCRegFlat(RegIndex idx) const override
498  {
499  return actualTC->readCCRegFlat(idx);
500  }
501 
502  void
504  {
505  actualTC->setCCRegFlat(idx, val);
506  }
507 
508  // hardware transactional memory
509  void
510  htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) override
511  {
512  panic("function not implemented");
513  }
514 
517  {
518  return actualTC->getHtmCheckpointPtr();
519  }
520 
521  void
523  {
524  panic("function not implemented");
525  }
526 
527 };
528 
529 } // namespace gem5
530 
531 #endif // __CPU_CHECKER_EXEC_CONTEXT_HH__
gem5::CheckerThreadContext::getWritableVecRegFlat
TheISA::VecRegContainer & getWritableVecRegFlat(RegIndex idx) override
Read vector register for modification, flat indexing.
Definition: thread_context.hh:453
gem5::CheckerThreadContext::setIntReg
void setIntReg(RegIndex reg_idx, RegVal val) override
Definition: thread_context.hh:293
gem5::CheckerThreadContext::readIntRegFlat
RegVal readIntRegFlat(RegIndex idx) const override
Flat register interfaces.
Definition: thread_context.hh:420
gem5::CheckerThreadContext::cpuId
int cpuId() const override
Definition: thread_context.hh:128
gem5::CheckerThreadContext::CheckerThreadContext
CheckerThreadContext(TC *actual_tc, CheckerCPU *checker_cpu)
Definition: thread_context.hh:72
gem5::BaseHTMCheckpointPtr
std::unique_ptr< BaseHTMCheckpoint > BaseHTMCheckpointPtr
Definition: htm.hh:125
gem5::CheckerThreadContext::nextInstAddr
Addr nextInstAddr() const override
Reads this thread's next PC.
Definition: thread_context.hh:366
gem5::CheckerThreadContext::getDecoderPtr
TheISA::Decoder * getDecoderPtr() override
Definition: thread_context.hh:159
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::CheckerThreadContext::setMiscReg
void setMiscReg(RegIndex misc_reg, RegVal val) override
Definition: thread_context.hh:393
gem5::SimpleThread::setIntReg
void setIntReg(RegIndex reg_idx, RegVal val) override
Definition: simple_thread.hh:367
gem5::CheckerThreadContext::instAddr
Addr instAddr() const override
Reads this thread's PC.
Definition: thread_context.hh:363
gem5::CheckerThreadContext::getCurrentInstCount
Tick getCurrentInstCount() override
Definition: thread_context.hh:119
gem5::ArmISA::VecPredRegContainer
VecPredReg::Container VecPredRegContainer
Definition: vec.hh:68
gem5::HtmFailureFaultCause
HtmFailureFaultCause
Definition: htm.hh:47
gem5::CheckerThreadContext::readVecPredReg
const TheISA::VecPredRegContainer & readVecPredReg(const RegId &reg) const override
Definition: thread_context.hh:275
gem5::CheckerThreadContext::halt
void halt() override
Set the status to Halted.
Definition: thread_context.hh:204
gem5::CheckerThreadContext::descheduleInstCountEvent
void descheduleInstCountEvent(Event *event) override
Definition: thread_context.hh:114
gem5::CheckerThreadContext::setIntRegFlat
void setIntRegFlat(RegIndex idx, RegVal val) override
Definition: thread_context.hh:426
gem5::CheckerThreadContext::socketId
uint32_t socketId() const override
Definition: thread_context.hh:126
gem5::CheckerThreadContext::setNPC
void setNPC(Addr val)
Definition: thread_context.hh:350
gem5::SimpleThread::copyArchRegs
void copyArchRegs(ThreadContext *tc) override
Definition: simple_thread.cc:165
gem5::MipsISA::event
Bitfield< 10, 5 > event
Definition: pra_constants.hh:300
gem5::CheckerThreadContext::checkerTC
SimpleThread * checkerTC
The checker's own SimpleThread.
Definition: thread_context.hh:85
gem5::ArmISA::e
Bitfield< 9 > e
Definition: misc_types.hh:64
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::SimpleThread::setMiscReg
void setMiscReg(RegIndex misc_reg, RegVal val) override
Definition: simple_thread.hh:464
gem5::ThreadContext::Status
Status
Definition: thread_context.hh:104
gem5::CheckerThreadContext::setMiscRegNoEffect
void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
Definition: thread_context.hh:384
gem5::CheckerThreadContext::setVecElem
void setVecElem(const RegId &reg, const TheISA::VecElem &val) override
Definition: thread_context.hh:314
gem5::SimpleThread::setVecReg
void setVecReg(const RegId &reg, const TheISA::VecRegContainer &val) override
Definition: simple_thread.hh:390
gem5::CheckerThreadContext::initMemProxies
void initMemProxies(ThreadContext *tc) override
Initialise the physical and virtual port proxies and tie them to the data port of the CPU.
Definition: thread_context.hh:177
gem5::SimpleThread::remove
bool remove(PCEvent *e) override
Definition: simple_thread.hh:182
gem5::CheckerThreadContext::setCCRegFlat
void setCCRegFlat(RegIndex idx, RegVal val) override
Definition: thread_context.hh:503
gem5::SimpleThread::clearArchRegs
void clearArchRegs() override
Definition: simple_thread.hh:257
gem5::ThreadContext::regStats
virtual void regStats(const std::string &name)
Definition: thread_context.hh:187
gem5::SimpleThread::setContextId
void setContextId(ContextID id) override
Definition: simple_thread.hh:207
gem5::CheckerThreadContext::remove
bool remove(PCEvent *e) override
Definition: thread_context.hh:100
gem5::CheckerThreadContext::actualTC
TC * actualTC
The main CPU's ThreadContext, or class that implements the ThreadContext interface.
Definition: thread_context.hh:81
gem5::CheckerThreadContext
Derived ThreadContext class for use with the Checker.
Definition: thread_context.hh:69
gem5::CheckerThreadContext::scheduleInstCountEvent
void scheduleInstCountEvent(Event *event, Tick count) override
Definition: thread_context.hh:109
gem5::CheckerThreadContext::readMiscReg
RegVal readMiscReg(RegIndex misc_reg) override
Definition: thread_context.hh:378
gem5::CheckerThreadContext::setVecReg
void setVecReg(const RegId &reg, const TheISA::VecRegContainer &val) override
Definition: thread_context.hh:307
gem5::SimpleThread
The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interf...
Definition: simple_thread.hh:94
gem5::SimpleThread::setThreadId
void setThreadId(int id) override
Definition: simple_thread.hh:205
gem5::SimpleThread::setVecElem
void setVecElem(const RegId &reg, const TheISA::VecElem &val) override
Definition: simple_thread.hh:400
gem5::SimpleThread::setVecPredReg
void setVecPredReg(const RegId &reg, const TheISA::VecPredRegContainer &val) override
Definition: simple_thread.hh:410
gem5::CheckerThreadContext::readIntReg
RegVal readIntReg(RegIndex reg_idx) const override
Definition: thread_context.hh:242
gem5::BaseMMU
Definition: mmu.hh:50
gem5::CheckerThreadContext::readLastActivate
Tick readLastActivate() override
Definition: thread_context.hh:220
gem5::CheckerThreadContext::getSystemPtr
System * getSystemPtr() override
Definition: thread_context.hh:164
gem5::CheckerThreadContext::flattenRegId
RegId flattenRegId(const RegId &regId) const override
Definition: thread_context.hh:402
gem5::CheckerCPU::recordPCChange
void recordPCChange(const TheISA::PCState &val)
Definition: cpu.hh:457
gem5::CheckerThreadContext::getCpuPtr
BaseCPU * getCpuPtr() override
Definition: thread_context.hh:124
gem5::CheckerThreadContext::setFloatRegFlat
void setFloatRegFlat(RegIndex idx, RegVal val) override
Definition: thread_context.hh:438
gem5::CheckerThreadContext::pcStateNoRecord
void pcStateNoRecord(const TheISA::PCState &val) override
Definition: thread_context.hh:357
gem5::CheckerThreadContext::pcState
void pcState(const TheISA::PCState &val) override
Sets this thread's PC state.
Definition: thread_context.hh:340
gem5::CheckerThreadContext::suspend
void suspend() override
Set the status to Suspended.
Definition: thread_context.hh:201
gem5::CheckerThreadContext::readCCRegFlat
RegVal readCCRegFlat(RegIndex idx) const override
Definition: thread_context.hh:497
gem5::MicroPC
uint16_t MicroPC
Definition: types.hh:149
gem5::CheckerThreadContext::pcState
TheISA::PCState pcState() const override
Reads this thread's PC state.
Definition: thread_context.hh:336
gem5::CheckerThreadContext::getCheckerCpuPtr
CheckerCPU * getCheckerCpuPtr() override
Definition: thread_context.hh:151
gem5::CheckerThreadContext::readLastSuspend
Tick readLastSuspend() override
Definition: thread_context.hh:221
gem5::CheckerThreadContext::readVecRegFlat
const TheISA::VecRegContainer & readVecRegFlat(RegIndex idx) const override
Definition: thread_context.hh:444
gem5::System
Definition: system.hh:77
gem5::CheckerThreadContext::takeOverFrom
void takeOverFrom(ThreadContext *oldContext) override
Definition: thread_context.hh:207
gem5::SimpleThread::copyState
void copyState(ThreadContext *oldContext)
Definition: simple_thread.cc:105
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::CheckerThreadContext::clearArchRegs
void clearArchRegs() override
Definition: thread_context.hh:232
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::CheckerThreadContext::connectMemPorts
void connectMemPorts(ThreadContext *tc)
Definition: thread_context.hh:183
gem5::Event
Definition: eventq.hh:251
gem5::X86ISA::count
count
Definition: misc.hh:709
gem5::CheckerThreadContext::getIsaPtr
BaseISA * getIsaPtr() override
Definition: thread_context.hh:156
gem5::ThreadContext::setNPC
void setNPC(Addr val)
Definition: thread_context.hh:241
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::PCEvent
Definition: pc_event.hh:45
gem5::CheckerCPU
CheckerCPU class.
Definition: cpu.hh:84
gem5::SimpleThread::setMiscRegNoEffect
void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
Definition: simple_thread.hh:458
cpu.hh
gem5::CheckerThreadContext::setVecElemFlat
void setVecElemFlat(RegIndex idx, const ElemIndex &elem_idx, const TheISA::VecElem &val) override
Definition: thread_context.hh:471
gem5::CheckerThreadContext::readCCReg
RegVal readCCReg(RegIndex reg_idx) const override
Definition: thread_context.hh:287
gem5::ArmISA::Decoder
Definition: decoder.hh:62
gem5::PortProxy
This object is a proxy for a port or other object which implements the functional response protocol,...
Definition: port_proxy.hh:86
gem5::CheckerThreadContext::getWritableVecReg
TheISA::VecRegContainer & getWritableVecReg(const RegId &reg) override
Read vector register for modification, hierarchical indexing.
Definition: thread_context.hh:263
gem5::CheckerThreadContext::setHtmCheckpointPtr
void setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) override
Definition: thread_context.hh:522
gem5::BaseCPU
Definition: base.hh:107
gem5::CheckerThreadContext::setProcessPtr
void setProcessPtr(Process *p) override
Definition: thread_context.hh:168
gem5::CheckerThreadContext::copyArchRegs
void copyArchRegs(ThreadContext *tc) override
Definition: thread_context.hh:225
gem5::ArmISA::VecRegContainer
gem5::VecRegContainer< NumVecElemPerVecReg *sizeof(VecElem)> VecRegContainer
Definition: vec.hh:62
gem5::SimpleThread::pcState
TheISA::PCState pcState() const override
Definition: simple_thread.hh:430
gem5::SimpleThread::schedule
bool schedule(PCEvent *e) override
Definition: simple_thread.hh:181
gem5::CheckerThreadContext::contextId
ContextID contextId() const override
Definition: thread_context.hh:130
gem5::CheckerThreadContext::htmAbortTransaction
void htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) override
Definition: thread_context.hh:510
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::SimpleThread::setFloatReg
void setFloatReg(RegIndex reg_idx, RegVal val) override
Definition: simple_thread.hh:377
gem5::ElemIndex
uint16_t ElemIndex
Logical vector register elem index type.
Definition: types.hh:179
name
const std::string & name()
Definition: trace.cc:49
gem5::SimpleThread::setStatus
void setStatus(Status newStatus) override
Definition: simple_thread.hh:232
gem5::CheckerThreadContext::checkerCPU
CheckerCPU * checkerCPU
Pointer to the checker CPU.
Definition: thread_context.hh:87
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::Process
Definition: process.hh:67
gem5::CheckerThreadContext::getVirtProxy
PortProxy & getVirtProxy() override
Definition: thread_context.hh:171
gem5::CheckerThreadContext::setVecPredReg
void setVecPredReg(const RegId &reg, const TheISA::VecPredRegContainer &val) override
Definition: thread_context.hh:321
simple_thread.hh
gem5::CheckerThreadContext::readVecReg
const TheISA::VecRegContainer & readVecReg(const RegId &reg) const override
Definition: thread_context.hh:254
gem5::ArmISA::VecElem
uint32_t VecElem
Definition: vec.hh:60
gem5::CheckerThreadContext::readFloatRegFlat
RegVal readFloatRegFlat(RegIndex idx) const override
Definition: thread_context.hh:432
gem5::CheckerThreadContext::schedule
bool schedule(PCEvent *e) override
Definition: thread_context.hh:91
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:246
gem5::CheckerThreadContext::setCCReg
void setCCReg(RegIndex reg_idx, RegVal val) override
Definition: thread_context.hh:329
gem5::CheckerThreadContext::status
Status status() const override
Definition: thread_context.hh:188
gem5::CheckerThreadContext::readVecPredRegFlat
const TheISA::VecPredRegContainer & readVecPredRegFlat(RegIndex idx) const override
Definition: thread_context.hh:478
gem5::CheckerThreadContext::getHtmCheckpointPtr
BaseHTMCheckpointPtr & getHtmCheckpointPtr() override
Definition: thread_context.hh:516
gem5::CheckerThreadContext::activate
void activate() override
Set the status to Active.
Definition: thread_context.hh:198
gem5::CheckerThreadContext::readVecElem
const TheISA::VecElem & readVecElem(const RegId &reg) const override
Definition: thread_context.hh:269
gem5::CheckerThreadContext::getWritableVecPredRegFlat
TheISA::VecPredRegContainer & getWritableVecPredRegFlat(RegIndex idx) override
Definition: thread_context.hh:484
gem5::CheckerThreadContext::setContextId
void setContextId(ContextID id) override
Definition: thread_context.hh:133
gem5::CheckerThreadContext::getWritableVecPredReg
TheISA::VecPredRegContainer & getWritableVecPredReg(const RegId &reg) override
Definition: thread_context.hh:281
gem5::BaseISA
Definition: isa.hh:54
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::CheckerThreadContext::setStCondFailures
void setStCondFailures(unsigned sc_failures) override
Definition: thread_context.hh:414
gem5::CheckerThreadContext::setVecRegFlat
void setVecRegFlat(RegIndex idx, const TheISA::VecRegContainer &val) override
Definition: thread_context.hh:459
gem5::CheckerThreadContext::setVecPredRegFlat
void setVecPredRegFlat(RegIndex idx, const TheISA::VecPredRegContainer &val) override
Definition: thread_context.hh:490
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::CheckerThreadContext::regStats
void regStats(const std::string &name) override
Definition: thread_context.hh:214
gem5::CheckerThreadContext::setStatus
void setStatus(Status new_status) override
Definition: thread_context.hh:191
gem5::CheckerThreadContext::microPC
MicroPC microPC() const override
Reads this thread's next PC.
Definition: thread_context.hh:369
gem5::CheckerThreadContext::readMiscRegNoEffect
RegVal readMiscRegNoEffect(RegIndex misc_reg) const override
Definition: thread_context.hh:372
gem5::Checker
Templated Checker class.
Definition: cpu.hh:565
gem5::CheckerThreadContext::readVecElemFlat
const TheISA::VecElem & readVecElemFlat(RegIndex idx, const ElemIndex &elem_idx) const override
Definition: thread_context.hh:465
gem5::CheckerThreadContext::readFloatReg
RegVal readFloatReg(RegIndex reg_idx) const override
Definition: thread_context.hh:248
thread_context.hh
gem5::CheckerThreadContext::readStCondFailures
unsigned readStCondFailures() const override
Definition: thread_context.hh:408
gem5::CheckerThreadContext::threadId
int threadId() const override
Returns this thread's ID number.
Definition: thread_context.hh:140
gem5::CheckerThreadContext::getMMUPtr
BaseMMU * getMMUPtr() override
Definition: thread_context.hh:148
gem5::SimpleThread::setCCReg
void setCCReg(RegIndex reg_idx, RegVal val) override
Definition: simple_thread.hh:421
gem5::CheckerThreadContext::setFloatReg
void setFloatReg(RegIndex reg_idx, RegVal val) override
Definition: thread_context.hh:300
gem5::CheckerThreadContext::getProcessPtr
Process * getProcessPtr() override
Definition: thread_context.hh:166
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::CheckerThreadContext::setThreadId
void setThreadId(int id) override
Definition: thread_context.hh:142

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