This is an implementation of a KVM-based ARMv8-compatible CPU. More...

#include <armv8_cpu.hh>

Inheritance diagram for gem5::ArmV8KvmCPU:

Classes
struct	IntRegInfo
	Mapping between integer registers in gem5 and KVM. More...

struct	MiscRegInfo
	Mapping between misc registers in gem5 and registers in KVM. More...

Public Member Functions
	ArmV8KvmCPU (const ArmV8KvmCPUParams &params)

virtual	~ArmV8KvmCPU ()

void	startup () override
	startup() is the final initialization call before simulation.

void	dump () const override
	Dump the internal state to the terminal.

Public Member Functions inherited from gem5::BaseArmKvmCPU
	BaseArmKvmCPU (const BaseArmKvmCPUParams &params)

virtual	~BaseArmKvmCPU ()

void	startup () override
	startup() is the final initialization call before simulation.

Public Member Functions inherited from gem5::BaseKvmCPU
	BaseKvmCPU (const BaseKvmCPUParams &params)

virtual	~BaseKvmCPU ()

void	init () override
	init() is called after all C++ SimObjects have been created and all ports are connected.

void	startup () override
	startup() is the final initialization call before simulation.

void	serializeThread (CheckpointOut &cp, ThreadID tid) const override
	Serialize a single thread.

void	unserializeThread (CheckpointIn &cp, ThreadID tid) override
	Unserialize one thread.

DrainState	drain () override
	Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are partially executed or are partially in flight.

void	drainResume () override
	Resume execution after a successful drain.

void	notifyFork () override
	Notify a child process of a fork.

void	switchOut () override
	Prepare for another CPU to take over execution.

void	takeOverFrom (BaseCPU *cpu) override
	Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be switched in.

void	verifyMemoryMode () const override
	Verify that the system is in a memory mode supported by the CPU.

Port &	getDataPort () override
	Purely virtual method that returns a reference to the data port.

Port &	getInstPort () override
	Purely virtual method that returns a reference to the instruction port.

void	wakeup (ThreadID tid=0) override

void	activateContext (ThreadID thread_num) override
	Notify the CPU that the indicated context is now active.

void	suspendContext (ThreadID thread_num) override
	Notify the CPU that the indicated context is now suspended.

void	deallocateContext (ThreadID thread_num)

void	haltContext (ThreadID thread_num) override
	Notify the CPU that the indicated context is now halted.

long	getVCpuID () const

ThreadContext *	getContext (int tn) override
	Given a thread num get tho thread context for it.

Counter	totalInsts () const override

Counter	totalOps () const override

void	finishMMIOPending ()
	Callback from KvmCPUPort to transition the CPU out of RunningMMIOPending when all timing requests have completed.

void	kick () const
	Force an exit from KVM.

Public Member Functions inherited from gem5::BaseCPU
int	cpuId () const
	Reads this CPU's ID.

uint32_t	socketId () const
	Reads this CPU's Socket ID.

RequestorID	dataRequestorId () const
	Reads this CPU's unique data requestor ID.

RequestorID	instRequestorId () const
	Reads this CPU's unique instruction requestor ID.

Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID) override
	Get a port on this CPU.

uint32_t	taskId () const
	Get cpu task id.

void	taskId (uint32_t id)
	Set cpu task id.

uint32_t	getPid () const

void	setPid (uint32_t pid)

void	workItemBegin ()

void	workItemEnd ()

Tick	instCount ()

BaseInterrupts *	getInterruptController (ThreadID tid)

void	postInterrupt (ThreadID tid, int int_num, int index)

void	clearInterrupt (ThreadID tid, int int_num, int index)

void	clearInterrupts (ThreadID tid)

bool	checkInterrupts (ThreadID tid) const

trace::InstTracer *	getTracer ()
	Provide access to the tracer pointer.

int	findContext (ThreadContext *tc)
	Given a Thread Context pointer return the thread num.

unsigned	numContexts ()
	Get the number of thread contexts available.

ThreadID	contextToThread (ContextID cid)
	Convert ContextID to threadID.

	PARAMS (BaseCPU)

	BaseCPU (const Params &params, bool is_checker=false)

virtual	~BaseCPU ()

void	regStats () override
	Callback to set stat parameters.

void	regProbePoints () override
	Register probe points for this object.

void	registerThreadContexts ()

void	deschedulePowerGatingEvent ()

void	schedulePowerGatingEvent ()

virtual void	setReset (bool state)
	Set the reset of the CPU to be either asserted or deasserted.

void	flushTLBs ()
	Flush all TLBs in the CPU.

bool	switchedOut () const
	Determine if the CPU is switched out.

Addr	cacheLineSize () const
	Get the cache line size of the system.

void	serialize (CheckpointOut &cp) const override
	Serialize this object to the given output stream.

void	unserialize (CheckpointIn &cp) override
	Reconstruct the state of this object from a checkpoint.

void	scheduleInstStop (ThreadID tid, Counter insts, std::string cause)
	Schedule an event that exits the simulation loops after a predefined number of instructions.

void	scheduleSimpointsInstStop (std::vector< Counter > inst_starts)
	Schedule simpoint events using the scheduleInstStop function.

void	scheduleInstStopAnyThread (Counter max_insts)
	Schedule an exit event when any threads in the core reach the max_insts instructions using the scheduleInstStop function.

uint64_t	getCurrentInstCount (ThreadID tid)
	Get the number of instructions executed by the specified thread on this CPU.

void	traceFunctions (Addr pc)

void	armMonitor (ThreadID tid, Addr address)

bool	mwait (ThreadID tid, PacketPtr pkt)

void	mwaitAtomic (ThreadID tid, ThreadContext tc, BaseMMU mmu)

AddressMonitor *	getCpuAddrMonitor (ThreadID tid)

virtual void	htmSendAbortSignal (ThreadID tid, uint64_t htm_uid, HtmFailureFaultCause cause)
	This function is used to instruct the memory subsystem that a transaction should be aborted and the speculative state should be thrown away.

virtual void	probeInstCommit (const StaticInstPtr &inst, Addr pc)
	Helper method to trigger PMU probes for a committed instruction.

Public Member Functions inherited from gem5::ClockedObject
	ClockedObject (const ClockedObjectParams &p)

void	serialize (CheckpointOut &cp) const override
	Serialize an object.

void	unserialize (CheckpointIn &cp) override
	Unserialize an object.

Public Member Functions inherited from gem5::SimObject
const Params &	params () const

	SimObject (const Params &p)

virtual	~SimObject ()

virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint.

virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint.

virtual void	regProbeListeners ()
	Register probe listeners for this object.

ProbeManager *	getProbeManager ()
	Get the probe manager for this object.

DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining.

virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes.

virtual void	memInvalidate ()
	Invalidate the contents of memory buffers.

void	serialize (CheckpointOut &cp) const override
	Serialize an object.

void	unserialize (CheckpointIn &cp) override
	Unserialize an object.

Public Member Functions inherited from gem5::EventManager
EventQueue *	eventQueue () const

void	schedule (Event &event, Tick when)

void	deschedule (Event &event)

void	reschedule (Event &event, Tick when, bool always=false)

void	schedule (Event *event, Tick when)

void	deschedule (Event *event)

void	reschedule (Event *event, Tick when, bool always=false)

void	wakeupEventQueue (Tick when=(Tick) -1)
	This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers.

void	setCurTick (Tick newVal)

	EventManager (EventManager &em)
	Event manger manages events in the event queue.

	EventManager (EventManager *em)

	EventManager (EventQueue *eq)

Public Member Functions inherited from gem5::Serializable
	Serializable ()

virtual	~Serializable ()

void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section.

void	serializeSection (CheckpointOut &cp, const std::string &name) const

void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object.

void	unserializeSection (CheckpointIn &cp, const std::string &name)

Public Member Functions inherited from gem5::Drainable
DrainState	drainState () const
	Return the current drain state of an object.

Public Member Functions inherited from gem5::statistics::Group
	Group (Group parent, const char name=nullptr)
	Construct a new statistics group.

virtual	~Group ()

virtual void	resetStats ()
	Callback to reset stats.

virtual void	preDumpStats ()
	Callback before stats are dumped.

void	addStat (statistics::Info *info)
	Register a stat with this group.

const std::map< std::string, Group * > &	getStatGroups () const
	Get all child groups associated with this object.

const std::vector< Info * > &	getStats () const
	Get all stats associated with this object.

void	addStatGroup (const char name, Group block)
	Add a stat block as a child of this block.

const Info *	resolveStat (std::string name) const
	Resolve a stat by its name within this group.

void	mergeStatGroup (Group *block)
	Merge the contents (stats & children) of a block to this block.

	Group ()=delete

	Group (const Group &)=delete

Group &	operator= (const Group &)=delete

Public Member Functions inherited from gem5::Named
	Named (const std::string &name_)

virtual	~Named ()=default

virtual std::string	name () const

Public Member Functions inherited from gem5::Clocked
void	updateClockPeriod ()
	Update the tick to the current tick.

Tick	clockEdge (Cycles cycles=Cycles(0)) const
	Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle.

Cycles	curCycle () const
	Determine the current cycle, corresponding to a tick aligned to a clock edge.

Tick	nextCycle () const
	Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future.

uint64_t	frequency () const

Tick	clockPeriod () const

double	voltage () const

Cycles	ticksToCycles (Tick t) const

Tick	cyclesToTicks (Cycles c) const

Protected Member Functions
void	updateKvmState () override
	Update the KVM state from the current thread context.

void	updateThreadContext () override
	Update the current thread context with the KVM state.

const std::vector< ArmV8KvmCPU::MiscRegInfo > &	getSysRegMap () const
	Get a map between system registers in kvm and gem5 registers.

Protected Member Functions inherited from gem5::BaseArmKvmCPU
Tick	kvmRun (Tick ticks) override
	Request KVM to run the guest for a given number of ticks.

void	stutterPC (PCStateBase &pc) const override
	Modify a PCStatePtr's value so that its next PC is the current PC.

void	ioctlRun () override
	Override for synchronizing state in kvm_run.

const RegIndexVector &	getRegList () const
	Get a list of registers supported by getOneReg() and setOneReg().

void	kvmArmVCpuInit (const kvm_vcpu_init &init)
	Tell the kernel to initialize this CPU.

Protected Member Functions inherited from gem5::BaseKvmCPU
void	tick ()
	Execute the CPU until the next event in the main event queue or until the guest needs service from gem5.

virtual uint64_t	getHostCycles () const
	Get the value of the hardware cycle counter in the guest.

virtual Tick	kvmRunDrain ()
	Request the CPU to run until draining completes.

struct kvm_run *	getKvmRunState ()
	Get a pointer to the kvm_run structure containing all the input and output parameters from kvmRun().

uint8_t *	getGuestData (uint64_t offset) const
	Retrieve a pointer to guest data stored at the end of the kvm_run structure.

void	kvmNonMaskableInterrupt ()
	Send a non-maskable interrupt to the guest.

void	kvmInterrupt (const struct kvm_interrupt &interrupt)
	Send a normal interrupt to the guest.

std::string	getAndFormatOneReg (uint64_t id) const
	Get and format one register for printout.

virtual bool	archIsDrained () const
	Is the architecture specific code in a state that prevents draining?

Tick	doMMIOAccess (Addr paddr, void *data, int size, bool write)
	Inject a memory mapped IO request into gem5.

int	ioctl (int request, long p1) const
	vCPU ioctl interface.

int	ioctl (int request, void *p1) const

int	ioctl (int request) const

void	getRegisters (struct kvm_regs &regs) const
	Get/Set the register state of the guest vCPU.

void	setRegisters (const struct kvm_regs &regs)

void	getSpecialRegisters (struct kvm_sregs &regs) const

void	setSpecialRegisters (const struct kvm_sregs &regs)

void	getFPUState (struct kvm_fpu &state) const
	Get/Set the guest FPU/vector state.

void	setFPUState (const struct kvm_fpu &state)

void	setOneReg (uint64_t id, const void *addr)
	Get/Set single register using the KVM_(SET\|GET)_ONE_REG API.

void	setOneReg (uint64_t id, uint64_t value)

void	setOneReg (uint64_t id, uint32_t value)

void	getOneReg (uint64_t id, void *addr) const

uint64_t	getOneRegU64 (uint64_t id) const

uint32_t	getOneRegU32 (uint64_t id) const

void	syncThreadContext ()
	Update a thread context if the KVM state is dirty with respect to the cached thread context.

EventQueue *	deviceEventQueue ()
	Get a pointer to the event queue owning devices.

void	syncKvmState ()
	Update the KVM if the thread context is dirty.

virtual Tick	handleKvmExit ()
	Main kvmRun exit handler, calls the relevant handleKvmExit* depending on exit type.

virtual Tick	handleKvmExitIO ()
	The guest performed a legacy IO request (out/inp on x86)

virtual Tick	handleKvmExitHypercall ()
	The guest requested a monitor service using a hypercall.

virtual Tick	handleKvmExitIRQWindowOpen ()
	The guest exited because an interrupt window was requested.

virtual Tick	handleKvmExitUnknown ()
	An unknown architecture dependent error occurred when starting the vCPU.

virtual Tick	handleKvmExitException ()
	An unhandled virtualization exception occured.

virtual Tick	handleKvmExitFailEntry ()
	KVM failed to start the virtualized CPU.

void	setSignalMask (const sigset_t *mask)
	Set the signal mask used in kvmRun()

Protected Member Functions inherited from gem5::BaseCPU
void	updateCycleCounters (CPUState state)
	base method keeping track of cycle progression

void	enterPwrGating ()

probing::PMUUPtr	pmuProbePoint (const char *name)
	Helper method to instantiate probe points belonging to this object.

Protected Member Functions inherited from gem5::Drainable
	Drainable ()

virtual	~Drainable ()

void	signalDrainDone () const
	Signal that an object is drained.

Protected Member Functions inherited from gem5::Clocked
	Clocked (ClockDomain &clk_domain)
	Create a clocked object and set the clock domain based on the parameters.

	Clocked (Clocked &)=delete

Clocked &	operator= (Clocked &)=delete

virtual	~Clocked ()
	Virtual destructor due to inheritance.

void	resetClock () const
	Reset the object's clock using the current global tick value.

virtual void	clockPeriodUpdated ()
	A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed.

Protected Attributes
std::vector< ArmV8KvmCPU::MiscRegInfo >	sysRegMap
	Cached mapping between system registers in kvm and misc regs in gem5.

Protected Attributes inherited from gem5::BaseArmKvmCPU
bool	irqAsserted
	Cached state of the IRQ line.

bool	fiqAsserted
	Cached state of the FIQ line.

ArmInterruptPin *	virtTimerPin
	If the user-space GIC and the kernel-space timer are used simultaneously, set up this interrupt pin to forward interrupt from the timer to the GIC when timer IRQ level change is intercepted.

uint64_t	prevDeviceIRQLevel
	KVM records whether each in-kernel device IRQ is asserted or disasserted in the kvmRunState->s.regs.device_irq_level bit map, and guarantees at least one KVM exit when the level changes.

Protected Attributes inherited from gem5::BaseKvmCPU
Status	_status
	CPU run state.

KVMCpuPort	dataPort
	Port for data requests.

KVMCpuPort	instPort
	Unused dummy port for the instruction interface.

const bool	alwaysSyncTC
	Be conservative and always synchronize the thread context on KVM entry/exit.

bool	threadContextDirty
	Is the gem5 context dirty? Set to true to force an update of the KVM vCPU state upon the next call to kvmRun().

bool	kvmStateDirty
	Is the KVM state dirty? Set to true to force an update of the KVM vCPU state upon the next call to kvmRun().

bool	usePerf
	True if using perf; False otherwise.

long	vcpuID
	KVM internal ID of the vCPU.

pthread_t	vcpuThread
	ID of the vCPU thread.

Protected Attributes inherited from gem5::BaseCPU
Tick	instCnt
	Instruction count used for SPARC misc register.

int	_cpuId

const uint32_t	_socketId
	Each cpu will have a socket ID that corresponds to its physical location in the system.

RequestorID	_instRequestorId
	instruction side request id that must be placed in all requests

RequestorID	_dataRequestorId
	data side request id that must be placed in all requests

uint32_t	_taskId
	An intrenal representation of a task identifier within gem5.

uint32_t	_pid
	The current OS process ID that is executing on this processor.

bool	_switchedOut
	Is the CPU switched out or active?

const Addr	_cacheLineSize
	Cache the cache line size that we get from the system.

SignalSinkPort< bool >	modelResetPort

std::vector< BaseInterrupts * >	interrupts

std::vector< ThreadContext * >	threadContexts

trace::InstTracer *	tracer

Cycles	previousCycle

CPUState	previousState

const Cycles	pwrGatingLatency

const bool	powerGatingOnIdle

EventFunctionWrapper	enterPwrGatingEvent

probing::PMUUPtr	ppRetiredInsts
	Instruction commit probe point.

probing::PMUUPtr	ppRetiredInstsPC

probing::PMUUPtr	ppRetiredLoads
	Retired load instructions.

probing::PMUUPtr	ppRetiredStores
	Retired store instructions.

probing::PMUUPtr	ppRetiredBranches
	Retired branches (any type)

probing::PMUUPtr	ppAllCycles
	CPU cycle counter even if any thread Context is suspended.

probing::PMUUPtr	ppActiveCycles
	CPU cycle counter, only counts if any thread contexts is active.

ProbePointArg< bool > *	ppSleeping
	ProbePoint that signals transitions of threadContexts sets.

Protected Attributes inherited from gem5::SimObject
const SimObjectParams &	_params
	Cached copy of the object parameters.

Protected Attributes inherited from gem5::EventManager
EventQueue *	eventq
	A pointer to this object's event queue.

Static Protected Attributes
static const std::vector< ArmV8KvmCPU::IntRegInfo >	intRegMap
	Mapping between gem5 integer registers and integer registers in kvm.

static const std::vector< ArmV8KvmCPU::MiscRegInfo >	miscRegMap
	Mapping between gem5 misc registers and registers in kvm.

static const std::set< ArmISA::MiscRegIndex >	deviceRegSet
	Device registers (needing "effectful" MiscReg writes)

static const std::vector< ArmV8KvmCPU::MiscRegInfo >	miscRegIdMap
	Mapping between gem5 ID misc registers and registers in kvm.

Static Protected Attributes inherited from gem5::BaseCPU
static std::unique_ptr< GlobalStats >	globalStats
	Pointer to the global stat structure.

Additional Inherited Members
Public Types inherited from gem5::ClockedObject
using	Params = ClockedObjectParams
	Parameters of ClockedObject.

Public Types inherited from gem5::SimObject
typedef SimObjectParams	Params

Static Public Member Functions inherited from gem5::BaseCPU
static int	numSimulatedCPUs ()

static Counter	numSimulatedInsts ()

static Counter	numSimulatedOps ()

Static Public Member Functions inherited from gem5::SimObject
static void	serializeAll (const std::string &cpt_dir)
	Create a checkpoint by serializing all SimObjects in the system.

static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it.

static void	setSimObjectResolver (SimObjectResolver *resolver)
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints.

static SimObjectResolver *	getSimObjectResolver ()
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints.

Static Public Member Functions inherited from gem5::Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section.

static void	generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
	Generate a checkpoint file so that the serialization can be routed to it.

Public Attributes inherited from gem5::BaseKvmCPU
SimpleThread *	thread
	A cached copy of a thread's state in the form of a SimpleThread object.

ThreadContext *	tc
	ThreadContext object, provides an interface for external objects to modify this thread's state.

KvmVM *	vm

gem5::BaseKvmCPU::StatGroup	stats

Counter	ctrInsts
	Number of instructions executed by the CPU.

Public Attributes inherited from gem5::BaseCPU
ThreadID	numThreads
	Number of threads we're actually simulating (<= SMT_MAX_THREADS).

System *	system

gem5::BaseCPU::BaseCPUStats	baseStats

Cycles	syscallRetryLatency

std::vector< std::unique_ptr< FetchCPUStats > >	fetchStats

std::vector< std::unique_ptr< ExecuteCPUStats > >	executeStats

std::vector< std::unique_ptr< CommitCPUStats > >	commitStats

Public Attributes inherited from gem5::ClockedObject
PowerState *	powerState

Static Public Attributes inherited from gem5::BaseCPU
static const uint32_t	invldPid = std::numeric_limits<uint32_t>::max()
	Invalid or unknown Pid.

Protected Types inherited from gem5::BaseArmKvmCPU
typedef std::vector< uint64_t >	RegIndexVector

Protected Types inherited from gem5::BaseKvmCPU
enum	Status { Idle , Running , RunningService , RunningMMIOPending , RunningServiceCompletion }

Protected Types inherited from gem5::BaseCPU
enum	CPUState { CPU_STATE_ON , CPU_STATE_SLEEP , CPU_STATE_WAKEUP }

Detailed Description

This is an implementation of a KVM-based ARMv8-compatible CPU.

Known limitations:

The system-register-based generic timer can only be simulated by the host kernel. Workaround: Use a memory mapped timer instead to simulate the timer in gem5.
Simulating devices (e.g., the generic timer) in the host kernel requires that the host kernel also simulates the GIC.
ID registers in the host and in gem5 must match for switching between simulated CPUs and KVM. This is particularly important for ID registers describing memory system capabilities (e.g., ASID size, physical address size).
Switching between a virtualized CPU and a simulated CPU is currently not supported if in-kernel device emulation is used. This could be worked around by adding support for switching to the gem5 (e.g., the KvmGic) side of the device models. A simpler workaround is to avoid in-kernel device models altogether.

Definition at line 82 of file armv8_cpu.hh.

Constructor & Destructor Documentation

◆ ArmV8KvmCPU()

gem5::ArmV8KvmCPU::ArmV8KvmCPU ( const ArmV8KvmCPUParams & params )

Definition at line 135 of file armv8_cpu.cc.

◆ ~ArmV8KvmCPU()

gem5::ArmV8KvmCPU::~ArmV8KvmCPU ( )

virtual

Definition at line 140 of file armv8_cpu.cc.

Member Function Documentation

◆ dump()

void gem5::ArmV8KvmCPU::dump ( ) const

overridevirtual

Dump the internal state to the terminal.

Reimplemented from gem5::BaseKvmCPU.

Definition at line 158 of file armv8_cpu.cc.

References gem5::ArmISA::decodeAArch64SysReg(), EXTRACT_FIELD, gem5::BaseKvmCPU::getAndFormatOneReg(), gem5::BaseArmKvmCPU::getRegList(), gem5::ArmISA::i, gem5::ArmISA::id, inform, INT_REG, intRegMap, gem5::kvmFPReg(), gem5::kvmXReg(), miscRegIdMap, miscRegMap, gem5::ArmISA::miscRegName, gem5::NUM_QREGS, gem5::NUM_XREGS, gem5::X86ISA::reg, gem5::PowerISA::ri, gem5::X86ISA::type, and gem5::X86ISA::val.

◆ getSysRegMap()

const std::vector< ArmV8KvmCPU::MiscRegInfo > & gem5::ArmV8KvmCPU::getSysRegMap ( ) const

protected

Get a map between system registers in kvm and gem5 registers.

This method returns a mapping between system registers in kvm and misc regs in gem5. The actual mapping is only created the first time the method is called and stored in a cache (ArmV8KvmCPU::sysRegMap).

Returns: Vector of kvm<->misc reg mappings.

Definition at line 376 of file armv8_cpu.cc.

Referenced by updateKvmState(), and updateThreadContext().

◆ startup()

void gem5::ArmV8KvmCPU::startup ( )

overridevirtual

startup() is the final initialization call before simulation.

All state is initialized (including unserialized state, if any, such as the curTick() value), so this is the appropriate place to schedule initial event(s) for objects that need them.

Reimplemented from gem5::SimObject.

Definition at line 145 of file armv8_cpu.cc.

References DPRINTF, miscRegIdMap, gem5::ThreadContext::readMiscReg(), gem5::PowerISA::ri, gem5::BaseKvmCPU::setOneReg(), gem5::BaseArmKvmCPU::startup(), and gem5::BaseKvmCPU::tc.

◆ updateKvmState()

void gem5::ArmV8KvmCPU::updateKvmState ( )

overrideprotectedvirtual

Update the KVM state from the current thread context.

The base CPU calls this method before starting the guest CPU when the contextDirty flag is set. The architecture dependent CPU implementation is expected to update all guest state (registers, special registers, and FPU state).

Implements gem5::BaseKvmCPU.

Definition at line 225 of file armv8_cpu.cc.

References gem5::VecRegContainer< SIZE >::as(), gem5::ArmISA::cc_reg::C, gem5::BaseKvmCPU::deviceEventQueue(), DPRINTF, FP_REGS_PER_VFP_REG, gem5::ArmISA::cc_reg::Ge, gem5::BaseKvmCPU::getAndFormatOneReg(), gem5::ThreadContext::getReg(), getSysRegMap(), gem5::ArmISA::i, gem5::ArmISA::inAArch64(), gem5::PCStateBase::instAddr(), INT_REG, gem5::ArmISA::intRegClass, intRegMap, gem5::kvmFPReg(), gem5::kvmXReg(), gem5::ArmISA::MISCREG_CPSR, miscRegMap, gem5::NUM_QREGS, gem5::NUM_XREGS, gem5::ArmISA::cc_reg::Nz, gem5::ThreadContext::pcState(), gem5::ThreadContext::readMiscReg(), gem5::X86ISA::reg, gem5::PowerISA::ri, gem5::BaseKvmCPU::setOneReg(), gem5::ArmISA::syncVecElemsToRegs(), gem5::BaseKvmCPU::tc, gem5::ArmISA::cc_reg::V, gem5::ArmISA::v, gem5::ArmISA::vecRegClass, and gem5::ArmISA::int_reg::x().

◆ updateThreadContext()

void gem5::ArmV8KvmCPU::updateThreadContext ( )

overrideprotectedvirtual

Update the current thread context with the KVM state.

The base CPU after the guest updates any of the KVM state. In practice, this happens after kvmRun is called. The architecture dependent code is expected to read the state of the guest CPU and update gem5's thread state.

Implements gem5::BaseKvmCPU.

Definition at line 295 of file armv8_cpu.cc.

References gem5::VecRegContainer< SIZE >::as(), gem5::ArmISA::cc_reg::C, gem5::BaseKvmCPU::deviceEventQueue(), DPRINTF, gem5::ArmISA::flatIntRegClass, FP_REGS_PER_VFP_REG, gem5::ArmISA::cc_reg::Ge, gem5::BaseKvmCPU::getAndFormatOneReg(), gem5::BaseKvmCPU::getOneReg(), gem5::BaseKvmCPU::getOneRegU64(), getSysRegMap(), gem5::ThreadContext::getWritableReg(), gem5::ArmISA::i, gem5::ArmISA::inAArch64(), INT_REG, gem5::ArmISA::intRegClass, intRegMap, gem5::kvmFPReg(), gem5::kvmXReg(), gem5::ArmISA::MISCREG_CPSR, miscRegMap, gem5::NUM_QREGS, gem5::NUM_XREGS, gem5::ArmISA::cc_reg::Nz, gem5::MipsISA::pc, gem5::ThreadContext::pcState(), gem5::X86ISA::reg, gem5::PowerISA::ri, gem5::ThreadContext::setMiscReg(), gem5::ThreadContext::setMiscRegNoEffect(), gem5::ThreadContext::setReg(), gem5::ArmISA::syncVecRegsToElems(), gem5::BaseKvmCPU::tc, gem5::ArmISA::cc_reg::V, gem5::ArmISA::v, gem5::ArmISA::vecRegClass, and gem5::ArmISA::int_reg::x().

Member Data Documentation

◆ deviceRegSet

const std::set< MiscRegIndex > gem5::ArmV8KvmCPU::deviceRegSet

staticprotected

Initial value:

= {
    MISCREG_CNTV_CTL_EL0,
    MISCREG_CNTV_CVAL_EL0,
    MISCREG_CNTKCTL_EL1,
}

Device registers (needing "effectful" MiscReg writes)

Definition at line 145 of file armv8_cpu.hh.

Referenced by getSysRegMap().

◆ intRegMap

const std::vector< ArmV8KvmCPU::IntRegInfo > gem5::ArmV8KvmCPU::intRegMap

staticprotected

Initial value:

= {
    { INT_REG(regs.sp), int_reg::Sp0, "SP(EL0)" },
    { INT_REG(sp_el1), int_reg::Sp1, "SP(EL1)" },
}

Mapping between gem5 integer registers and integer registers in kvm.

Definition at line 141 of file armv8_cpu.hh.

Referenced by dump(), updateKvmState(), and updateThreadContext().

◆ miscRegIdMap

const std::vector< ArmV8KvmCPU::MiscRegInfo > gem5::ArmV8KvmCPU::miscRegIdMap

staticprotected

Initial value:

= {
    MiscRegInfo(SYS_MPIDR_EL1, MISCREG_MPIDR_EL1, "MPIDR(EL1)"),
}

Mapping between gem5 ID misc registers and registers in kvm.

Definition at line 147 of file armv8_cpu.hh.

Referenced by dump(), and startup().

◆ miscRegMap

const std::vector< ArmV8KvmCPU::MiscRegInfo > gem5::ArmV8KvmCPU::miscRegMap

staticprotected

Initial value:

= {
    MiscRegInfo(INT_REG(elr_el1), MISCREG_ELR_EL1, "ELR(EL1)"),
    MiscRegInfo(INT_REG(spsr[KVM_SPSR_EL1]), MISCREG_SPSR_EL1, "SPSR(EL1)"),
    MiscRegInfo(INT_REG(spsr[KVM_SPSR_ABT]), MISCREG_SPSR_ABT, "SPSR(ABT)"),
    MiscRegInfo(INT_REG(spsr[KVM_SPSR_UND]), MISCREG_SPSR_UND, "SPSR(UND)"),
    MiscRegInfo(INT_REG(spsr[KVM_SPSR_IRQ]), MISCREG_SPSR_IRQ, "SPSR(IRQ)"),
    MiscRegInfo(INT_REG(spsr[KVM_SPSR_FIQ]), MISCREG_SPSR_FIQ, "SPSR(FIQ)"),
    MiscRegInfo(CORE_REG(fp_regs.fpsr, U32), MISCREG_FPSR, "FPSR"),
    MiscRegInfo(CORE_REG(fp_regs.fpcr, U32), MISCREG_FPCR, "FPCR"),
}

Mapping between gem5 misc registers and registers in kvm.

Definition at line 143 of file armv8_cpu.hh.

Referenced by dump(), updateKvmState(), and updateThreadContext().

◆ sysRegMap

std::vector<ArmV8KvmCPU::MiscRegInfo> gem5::ArmV8KvmCPU::sysRegMap

mutableprotected

Cached mapping between system registers in kvm and misc regs in gem5.

Definition at line 150 of file armv8_cpu.hh.

Referenced by getSysRegMap().

The documentation for this class was generated from the following files:

arch/arm/kvm/armv8_cpu.hh
arch/arm/kvm/armv8_cpu.cc

Classes

Public Member Functions

Protected Member Functions

Protected Attributes

Static Protected Attributes

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

◆ ArmV8KvmCPU()

◆ ~ArmV8KvmCPU()

Member Function Documentation

◆ dump()

◆ getSysRegMap()

◆ startup()

◆ updateKvmState()

◆ updateThreadContext()

Member Data Documentation

◆ deviceRegSet

◆ intRegMap

◆ miscRegIdMap

◆ miscRegMap

◆ sysRegMap