gem5  v21.1.0.2
Classes | Public Member Functions | Protected Member Functions | Protected Attributes | Static Protected Attributes | List of all members
gem5::ArmV8KvmCPU Class Reference

This is an implementation of a KVM-based ARMv8-compatible CPU. More...

#include <armv8_cpu.hh>

Inheritance diagram for gem5::ArmV8KvmCPU:
gem5::BaseArmKvmCPU gem5::BaseKvmCPU gem5::BaseCPU gem5::ClockedObject gem5::SimObject gem5::Clocked gem5::EventManager gem5::Serializable gem5::Drainable gem5::statistics::Group gem5::Named

Classes

struct  IntRegInfo
 Mapping between integer registers in gem5 and KVM. More...
 
struct  MiscRegInfo
 Mapping between misc registers in gem5 and registers in KVM. More...
 

Public Member Functions

 ArmV8KvmCPU (const ArmV8KvmCPUParams &params)
 
virtual ~ArmV8KvmCPU ()
 
void startup () override
 startup() is the final initialization call before simulation. More...
 
void dump () const override
 Dump the internal state to the terminal. More...
 
- Public Member Functions inherited from gem5::BaseArmKvmCPU
 BaseArmKvmCPU (const BaseArmKvmCPUParams &params)
 
virtual ~BaseArmKvmCPU ()
 
void startup () override
 startup() is the final initialization call before simulation. More...
 
- Public Member Functions inherited from gem5::BaseKvmCPU
 BaseKvmCPU (const BaseKvmCPUParams &params)
 
virtual ~BaseKvmCPU ()
 
void init () override
 init() is called after all C++ SimObjects have been created and all ports are connected. More...
 
void startup () override
 startup() is the final initialization call before simulation. More...
 
void serializeThread (CheckpointOut &cp, ThreadID tid) const override
 Serialize a single thread. More...
 
void unserializeThread (CheckpointIn &cp, ThreadID tid) override
 Unserialize one thread. More...
 
DrainState drain () override
 Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are partially executed or are partially in flight. More...
 
void drainResume () override
 Resume execution after a successful drain. More...
 
void notifyFork () override
 Notify a child process of a fork. More...
 
void switchOut () override
 Prepare for another CPU to take over execution. More...
 
void takeOverFrom (BaseCPU *cpu) override
 Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be switched in. More...
 
void verifyMemoryMode () const override
 Verify that the system is in a memory mode supported by the CPU. More...
 
PortgetDataPort () override
 Purely virtual method that returns a reference to the data port. More...
 
PortgetInstPort () override
 Purely virtual method that returns a reference to the instruction port. More...
 
void wakeup (ThreadID tid=0) override
 
void activateContext (ThreadID thread_num) override
 Notify the CPU that the indicated context is now active. More...
 
void suspendContext (ThreadID thread_num) override
 Notify the CPU that the indicated context is now suspended. More...
 
void deallocateContext (ThreadID thread_num)
 
void haltContext (ThreadID thread_num) override
 Notify the CPU that the indicated context is now halted. More...
 
long getVCpuID () const
 
ThreadContextgetContext (int tn) override
 Given a thread num get tho thread context for it. More...
 
Counter totalInsts () const override
 
Counter totalOps () const override
 
void finishMMIOPending ()
 Callback from KvmCPUPort to transition the CPU out of RunningMMIOPending when all timing requests have completed. More...
 
void kick () const
 Force an exit from KVM. More...
 
- Public Member Functions inherited from gem5::BaseCPU
int cpuId () const
 Reads this CPU's ID. More...
 
uint32_t socketId () const
 Reads this CPU's Socket ID. More...
 
RequestorID dataRequestorId () const
 Reads this CPU's unique data requestor ID. More...
 
RequestorID instRequestorId () const
 Reads this CPU's unique instruction requestor ID. More...
 
PortgetPort (const std::string &if_name, PortID idx=InvalidPortID) override
 Get a port on this CPU. More...
 
uint32_t taskId () const
 Get cpu task id. More...
 
void taskId (uint32_t id)
 Set cpu task id. More...
 
uint32_t getPid () const
 
void setPid (uint32_t pid)
 
void workItemBegin ()
 
void workItemEnd ()
 
Tick instCount ()
 
BaseInterruptsgetInterruptController (ThreadID tid)
 
void postInterrupt (ThreadID tid, int int_num, int index)
 
void clearInterrupt (ThreadID tid, int int_num, int index)
 
void clearInterrupts (ThreadID tid)
 
bool checkInterrupts (ThreadID tid) const
 
Trace::InstTracergetTracer ()
 Provide access to the tracer pointer. More...
 
int findContext (ThreadContext *tc)
 Given a Thread Context pointer return the thread num. More...
 
unsigned numContexts ()
 Get the number of thread contexts available. More...
 
ThreadID contextToThread (ContextID cid)
 Convert ContextID to threadID. More...
 
 PARAMS (BaseCPU)
 
 BaseCPU (const Params &params, bool is_checker=false)
 
virtual ~BaseCPU ()
 
void regStats () override
 Callback to set stat parameters. More...
 
void regProbePoints () override
 Register probe points for this object. More...
 
void registerThreadContexts ()
 
void deschedulePowerGatingEvent ()
 
void schedulePowerGatingEvent ()
 
void flushTLBs ()
 Flush all TLBs in the CPU. More...
 
bool switchedOut () const
 Determine if the CPU is switched out. More...
 
unsigned int cacheLineSize () const
 Get the cache line size of the system. More...
 
void serialize (CheckpointOut &cp) const override
 Serialize this object to the given output stream. More...
 
void unserialize (CheckpointIn &cp) override
 Reconstruct the state of this object from a checkpoint. More...
 
void scheduleInstStop (ThreadID tid, Counter insts, const char *cause)
 Schedule an event that exits the simulation loops after a predefined number of instructions. More...
 
uint64_t getCurrentInstCount (ThreadID tid)
 Get the number of instructions executed by the specified thread on this CPU. More...
 
void traceFunctions (Addr pc)
 
void armMonitor (ThreadID tid, Addr address)
 
bool mwait (ThreadID tid, PacketPtr pkt)
 
void mwaitAtomic (ThreadID tid, ThreadContext *tc, BaseMMU *mmu)
 
AddressMonitorgetCpuAddrMonitor (ThreadID tid)
 
virtual void probeInstCommit (const StaticInstPtr &inst, Addr pc)
 Helper method to trigger PMU probes for a committed instruction. More...
 
- Public Member Functions inherited from gem5::ClockedObject
 ClockedObject (const ClockedObjectParams &p)
 
void serialize (CheckpointOut &cp) const override
 Serialize an object. More...
 
void unserialize (CheckpointIn &cp) override
 Unserialize an object. More...
 
- Public Member Functions inherited from gem5::SimObject
const Paramsparams () const
 
 SimObject (const Params &p)
 
virtual ~SimObject ()
 
virtual void loadState (CheckpointIn &cp)
 loadState() is called on each SimObject when restoring from a checkpoint. More...
 
virtual void initState ()
 initState() is called on each SimObject when not restoring from a checkpoint. More...
 
virtual void regProbeListeners ()
 Register probe listeners for this object. More...
 
ProbeManagergetProbeManager ()
 Get the probe manager for this object. More...
 
DrainState drain () override
 Provide a default implementation of the drain interface for objects that don't need draining. More...
 
virtual void memWriteback ()
 Write back dirty buffers to memory using functional writes. More...
 
virtual void memInvalidate ()
 Invalidate the contents of memory buffers. More...
 
void serialize (CheckpointOut &cp) const override
 Serialize an object. More...
 
void unserialize (CheckpointIn &cp) override
 Unserialize an object. More...
 
- Public Member Functions inherited from gem5::EventManager
EventQueueeventQueue () const
 
void schedule (Event &event, Tick when)
 
void deschedule (Event &event)
 
void reschedule (Event &event, Tick when, bool always=false)
 
void schedule (Event *event, Tick when)
 
void deschedule (Event *event)
 
void reschedule (Event *event, Tick when, bool always=false)
 
void wakeupEventQueue (Tick when=(Tick) -1)
 This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. More...
 
void setCurTick (Tick newVal)
 
 EventManager (EventManager &em)
 Event manger manages events in the event queue. More...
 
 EventManager (EventManager *em)
 
 EventManager (EventQueue *eq)
 
- Public Member Functions inherited from gem5::Serializable
 Serializable ()
 
virtual ~Serializable ()
 
void serializeSection (CheckpointOut &cp, const char *name) const
 Serialize an object into a new section. More...
 
void serializeSection (CheckpointOut &cp, const std::string &name) const
 
void unserializeSection (CheckpointIn &cp, const char *name)
 Unserialize an a child object. More...
 
void unserializeSection (CheckpointIn &cp, const std::string &name)
 
- Public Member Functions inherited from gem5::Drainable
DrainState drainState () const
 Return the current drain state of an object. More...
 
- Public Member Functions inherited from gem5::statistics::Group
 Group (Group *parent, const char *name=nullptr)
 Construct a new statistics group. More...
 
virtual ~Group ()
 
virtual void resetStats ()
 Callback to reset stats. More...
 
virtual void preDumpStats ()
 Callback before stats are dumped. More...
 
void addStat (statistics::Info *info)
 Register a stat with this group. More...
 
const std::map< std::string, Group * > & getStatGroups () const
 Get all child groups associated with this object. More...
 
const std::vector< Info * > & getStats () const
 Get all stats associated with this object. More...
 
void addStatGroup (const char *name, Group *block)
 Add a stat block as a child of this block. More...
 
const InforesolveStat (std::string name) const
 Resolve a stat by its name within this group. More...
 
void mergeStatGroup (Group *block)
 Merge the contents (stats & children) of a block to this block. More...
 
 Group ()=delete
 
 Group (const Group &)=delete
 
Groupoperator= (const Group &)=delete
 
- Public Member Functions inherited from gem5::Named
 Named (const std::string &name_)
 
virtual ~Named ()=default
 
virtual std::string name () const
 
- Public Member Functions inherited from gem5::Clocked
void updateClockPeriod ()
 Update the tick to the current tick. More...
 
Tick clockEdge (Cycles cycles=Cycles(0)) const
 Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle. More...
 
Cycles curCycle () const
 Determine the current cycle, corresponding to a tick aligned to a clock edge. More...
 
Tick nextCycle () const
 Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future. More...
 
uint64_t frequency () const
 
Tick clockPeriod () const
 
double voltage () const
 
Cycles ticksToCycles (Tick t) const
 
Tick cyclesToTicks (Cycles c) const
 

Protected Member Functions

void updateKvmState () override
 Update the KVM state from the current thread context. More...
 
void updateThreadContext () override
 Update the current thread context with the KVM state. More...
 
const std::vector< ArmV8KvmCPU::MiscRegInfo > & getSysRegMap () const
 Get a map between system registers in kvm and gem5 registers. More...
 
- Protected Member Functions inherited from gem5::BaseArmKvmCPU
Tick kvmRun (Tick ticks) override
 Request KVM to run the guest for a given number of ticks. More...
 
void ioctlRun () override
 Override for synchronizing state in kvm_run. More...
 
const RegIndexVectorgetRegList () const
 Get a list of registers supported by getOneReg() and setOneReg(). More...
 
void kvmArmVCpuInit (const kvm_vcpu_init &init)
 Tell the kernel to initialize this CPU. More...
 
- Protected Member Functions inherited from gem5::BaseKvmCPU
void tick ()
 Execute the CPU until the next event in the main event queue or until the guest needs service from gem5. More...
 
virtual uint64_t getHostCycles () const
 Get the value of the hardware cycle counter in the guest. More...
 
virtual Tick kvmRunDrain ()
 Request the CPU to run until draining completes. More...
 
struct kvm_run * getKvmRunState ()
 Get a pointer to the kvm_run structure containing all the input and output parameters from kvmRun(). More...
 
uint8_t * getGuestData (uint64_t offset) const
 Retrieve a pointer to guest data stored at the end of the kvm_run structure. More...
 
void kvmNonMaskableInterrupt ()
 Send a non-maskable interrupt to the guest. More...
 
void kvmInterrupt (const struct kvm_interrupt &interrupt)
 Send a normal interrupt to the guest. More...
 
std::string getAndFormatOneReg (uint64_t id) const
 Get and format one register for printout. More...
 
virtual bool archIsDrained () const
 Is the architecture specific code in a state that prevents draining? More...
 
Tick doMMIOAccess (Addr paddr, void *data, int size, bool write)
 Inject a memory mapped IO request into gem5. More...
 
int ioctl (int request, long p1) const
 vCPU ioctl interface. More...
 
int ioctl (int request, void *p1) const
 
int ioctl (int request) const
 
void getRegisters (struct kvm_regs &regs) const
 Get/Set the register state of the guest vCPU. More...
 
void setRegisters (const struct kvm_regs &regs)
 
void getSpecialRegisters (struct kvm_sregs &regs) const
 
void setSpecialRegisters (const struct kvm_sregs &regs)
 
void getFPUState (struct kvm_fpu &state) const
 Get/Set the guest FPU/vector state. More...
 
void setFPUState (const struct kvm_fpu &state)
 
void setOneReg (uint64_t id, const void *addr)
 Get/Set single register using the KVM_(SET|GET)_ONE_REG API. More...
 
void setOneReg (uint64_t id, uint64_t value)
 
void setOneReg (uint64_t id, uint32_t value)
 
void getOneReg (uint64_t id, void *addr) const
 
uint64_t getOneRegU64 (uint64_t id) const
 
uint32_t getOneRegU32 (uint64_t id) const
 
void syncThreadContext ()
 Update a thread context if the KVM state is dirty with respect to the cached thread context. More...
 
EventQueuedeviceEventQueue ()
 Get a pointer to the event queue owning devices. More...
 
void syncKvmState ()
 Update the KVM if the thread context is dirty. More...
 
virtual Tick handleKvmExit ()
 Main kvmRun exit handler, calls the relevant handleKvmExit* depending on exit type. More...
 
virtual Tick handleKvmExitIO ()
 The guest performed a legacy IO request (out/inp on x86) More...
 
virtual Tick handleKvmExitHypercall ()
 The guest requested a monitor service using a hypercall. More...
 
virtual Tick handleKvmExitIRQWindowOpen ()
 The guest exited because an interrupt window was requested. More...
 
virtual Tick handleKvmExitUnknown ()
 An unknown architecture dependent error occurred when starting the vCPU. More...
 
virtual Tick handleKvmExitException ()
 An unhandled virtualization exception occured. More...
 
virtual Tick handleKvmExitFailEntry ()
 KVM failed to start the virtualized CPU. More...
 
void setSignalMask (const sigset_t *mask)
 Set the signal mask used in kvmRun() More...
 
- Protected Member Functions inherited from gem5::BaseCPU
void updateCycleCounters (CPUState state)
 base method keeping track of cycle progression More...
 
void enterPwrGating ()
 
probing::PMUUPtr pmuProbePoint (const char *name)
 Helper method to instantiate probe points belonging to this object. More...
 
- Protected Member Functions inherited from gem5::Drainable
 Drainable ()
 
virtual ~Drainable ()
 
void signalDrainDone () const
 Signal that an object is drained. More...
 
- Protected Member Functions inherited from gem5::Clocked
 Clocked (ClockDomain &clk_domain)
 Create a clocked object and set the clock domain based on the parameters. More...
 
 Clocked (Clocked &)=delete
 
Clockedoperator= (Clocked &)=delete
 
virtual ~Clocked ()
 Virtual destructor due to inheritance. More...
 
void resetClock () const
 Reset the object's clock using the current global tick value. More...
 
virtual void clockPeriodUpdated ()
 A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed. More...
 

Protected Attributes

std::vector< ArmV8KvmCPU::MiscRegInfosysRegMap
 Cached mapping between system registers in kvm and misc regs in gem5. More...
 
- Protected Attributes inherited from gem5::BaseArmKvmCPU
bool irqAsserted
 Cached state of the IRQ line. More...
 
bool fiqAsserted
 Cached state of the FIQ line. More...
 
ArmInterruptPinvirtTimerPin
 If the user-space GIC and the kernel-space timer are used simultaneously, set up this interrupt pin to forward interrupt from the timer to the GIC when timer IRQ level change is intercepted. More...
 
uint64_t prevDeviceIRQLevel
 KVM records whether each in-kernel device IRQ is asserted or disasserted in the kvmRunState->s.regs.device_irq_level bit map, and guarantees at least one KVM exit when the level changes. More...
 
- Protected Attributes inherited from gem5::BaseKvmCPU
Status _status
 CPU run state. More...
 
KVMCpuPort dataPort
 Port for data requests. More...
 
KVMCpuPort instPort
 Unused dummy port for the instruction interface. More...
 
const bool alwaysSyncTC
 Be conservative and always synchronize the thread context on KVM entry/exit. More...
 
bool threadContextDirty
 Is the gem5 context dirty? Set to true to force an update of the KVM vCPU state upon the next call to kvmRun(). More...
 
bool kvmStateDirty
 Is the KVM state dirty? Set to true to force an update of the KVM vCPU state upon the next call to kvmRun(). More...
 
const long vcpuID
 KVM internal ID of the vCPU. More...
 
pthread_t vcpuThread
 ID of the vCPU thread. More...
 
- Protected Attributes inherited from gem5::BaseCPU
Tick instCnt
 Instruction count used for SPARC misc register. More...
 
int _cpuId
 
const uint32_t _socketId
 Each cpu will have a socket ID that corresponds to its physical location in the system. More...
 
RequestorID _instRequestorId
 instruction side request id that must be placed in all requests More...
 
RequestorID _dataRequestorId
 data side request id that must be placed in all requests More...
 
uint32_t _taskId
 An intrenal representation of a task identifier within gem5. More...
 
uint32_t _pid
 The current OS process ID that is executing on this processor. More...
 
bool _switchedOut
 Is the CPU switched out or active? More...
 
const unsigned int _cacheLineSize
 Cache the cache line size that we get from the system. More...
 
std::vector< BaseInterrupts * > interrupts
 
std::vector< ThreadContext * > threadContexts
 
Trace::InstTracertracer
 
Cycles previousCycle
 
CPUState previousState
 
const Cycles pwrGatingLatency
 
const bool powerGatingOnIdle
 
EventFunctionWrapper enterPwrGatingEvent
 
probing::PMUUPtr ppRetiredInsts
 Instruction commit probe point. More...
 
probing::PMUUPtr ppRetiredInstsPC
 
probing::PMUUPtr ppRetiredLoads
 Retired load instructions. More...
 
probing::PMUUPtr ppRetiredStores
 Retired store instructions. More...
 
probing::PMUUPtr ppRetiredBranches
 Retired branches (any type) More...
 
probing::PMUUPtr ppAllCycles
 CPU cycle counter even if any thread Context is suspended. More...
 
probing::PMUUPtr ppActiveCycles
 CPU cycle counter, only counts if any thread contexts is active. More...
 
ProbePointArg< bool > * ppSleeping
 ProbePoint that signals transitions of threadContexts sets. More...
 
- Protected Attributes inherited from gem5::SimObject
const SimObjectParams & _params
 Cached copy of the object parameters. More...
 
- Protected Attributes inherited from gem5::EventManager
EventQueueeventq
 A pointer to this object's event queue. More...
 

Static Protected Attributes

static const std::vector< ArmV8KvmCPU::IntRegInfointRegMap
 Mapping between gem5 integer registers and integer registers in kvm. More...
 
static const std::vector< ArmV8KvmCPU::MiscRegInfomiscRegMap
 Mapping between gem5 misc registers and registers in kvm. More...
 
static const std::set< ArmISA::MiscRegIndexdeviceRegSet
 Device registers (needing "effectful" MiscReg writes) More...
 
static const std::vector< ArmV8KvmCPU::MiscRegInfomiscRegIdMap
 Mapping between gem5 ID misc registers and registers in kvm. More...
 
- Static Protected Attributes inherited from gem5::BaseCPU
static std::unique_ptr< GlobalStatsglobalStats
 Pointer to the global stat structure. More...
 

Additional Inherited Members

- Public Types inherited from gem5::ClockedObject
using Params = ClockedObjectParams
 Parameters of ClockedObject. More...
 
- Public Types inherited from gem5::SimObject
typedef SimObjectParams Params
 
- Static Public Member Functions inherited from gem5::BaseCPU
static int numSimulatedCPUs ()
 
static Counter numSimulatedInsts ()
 
static Counter numSimulatedOps ()
 
- Static Public Member Functions inherited from gem5::SimObject
static void serializeAll (const std::string &cpt_dir)
 Create a checkpoint by serializing all SimObjects in the system. More...
 
static SimObjectfind (const char *name)
 Find the SimObject with the given name and return a pointer to it. More...
 
static void setSimObjectResolver (SimObjectResolver *resolver)
 There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...
 
static SimObjectResolvergetSimObjectResolver ()
 There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...
 
- Static Public Member Functions inherited from gem5::Serializable
static const std::string & currentSection ()
 Gets the fully-qualified name of the active section. More...
 
static void generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
 Generate a checkpoint file so that the serialization can be routed to it. More...
 
- Public Attributes inherited from gem5::BaseKvmCPU
SimpleThreadthread
 A cached copy of a thread's state in the form of a SimpleThread object. More...
 
ThreadContexttc
 ThreadContext object, provides an interface for external objects to modify this thread's state. More...
 
KvmVMvm
 
gem5::BaseKvmCPU::StatGroup stats
 
Counter ctrInsts
 Number of instructions executed by the CPU. More...
 
- Public Attributes inherited from gem5::BaseCPU
ThreadID numThreads
 Number of threads we're actually simulating (<= SMT_MAX_THREADS). More...
 
Systemsystem
 
gem5::BaseCPU::BaseCPUStats baseStats
 
Cycles syscallRetryLatency
 
- Public Attributes inherited from gem5::ClockedObject
PowerStatepowerState
 
- Static Public Attributes inherited from gem5::BaseCPU
static const uint32_t invldPid = std::numeric_limits<uint32_t>::max()
 Invalid or unknown Pid. More...
 
- Protected Types inherited from gem5::BaseArmKvmCPU
typedef std::vector< uint64_t > RegIndexVector
 
- Protected Types inherited from gem5::BaseKvmCPU
enum  Status {
  Idle, Running, RunningService, RunningMMIOPending,
  RunningServiceCompletion
}
 
- Protected Types inherited from gem5::BaseCPU
enum  CPUState { CPU_STATE_ON, CPU_STATE_SLEEP, CPU_STATE_WAKEUP }
 

Detailed Description

This is an implementation of a KVM-based ARMv8-compatible CPU.

Known limitations:

Definition at line 82 of file armv8_cpu.hh.

Constructor & Destructor Documentation

◆ ArmV8KvmCPU()

gem5::ArmV8KvmCPU::ArmV8KvmCPU ( const ArmV8KvmCPUParams &  params)

Definition at line 132 of file armv8_cpu.cc.

◆ ~ArmV8KvmCPU()

gem5::ArmV8KvmCPU::~ArmV8KvmCPU ( )
virtual

Definition at line 137 of file armv8_cpu.cc.

Member Function Documentation

◆ dump()

void gem5::ArmV8KvmCPU::dump ( ) const
overridevirtual

◆ getSysRegMap()

const std::vector< ArmV8KvmCPU::MiscRegInfo > & gem5::ArmV8KvmCPU::getSysRegMap ( ) const
protected

Get a map between system registers in kvm and gem5 registers.

This method returns a mapping between system registers in kvm and misc regs in gem5. The actual mapping is only created the first time the method is called and stored in a cache (ArmV8KvmCPU::sysRegMap).

Returns
Vector of kvm<->misc reg mappings.

Definition at line 365 of file armv8_cpu.cc.

References gem5::ArmISA::decodeAArch64SysReg(), deviceRegSet, EXTRACT_FIELD, gem5::BaseArmKvmCPU::getRegList(), gem5::ArmISA::MISCREG_HYP_NS_WR, gem5::ArmISA::MISCREG_IMPLEMENTED, gem5::ArmISA::MISCREG_MON_NS0_WR, gem5::ArmISA::MISCREG_MON_NS1_WR, gem5::ArmISA::MISCREG_PRI_NS_WR, gem5::ArmISA::MISCREG_PRI_S_WR, gem5::ArmISA::MISCREG_USR_NS_WR, gem5::ArmISA::MISCREG_USR_S_WR, gem5::ArmISA::MISCREG_WARN_NOT_FAIL, gem5::ArmISA::miscRegInfo, gem5::ArmISA::miscRegName, gem5::X86ISA::reg, sysRegMap, and gem5::X86ISA::type.

Referenced by updateKvmState(), and updateThreadContext().

◆ startup()

void gem5::ArmV8KvmCPU::startup ( )
overridevirtual

startup() is the final initialization call before simulation.

All state is initialized (including unserialized state, if any, such as the curTick() value), so this is the appropriate place to schedule initial event(s) for objects that need them.

Reimplemented from gem5::SimObject.

Definition at line 142 of file armv8_cpu.cc.

References DPRINTF, miscRegIdMap, gem5::ThreadContext::readMiscReg(), gem5::PowerISA::ri, gem5::BaseKvmCPU::setOneReg(), gem5::BaseArmKvmCPU::startup(), and gem5::BaseKvmCPU::tc.

◆ updateKvmState()

void gem5::ArmV8KvmCPU::updateKvmState ( )
overrideprotectedvirtual

◆ updateThreadContext()

void gem5::ArmV8KvmCPU::updateThreadContext ( )
overrideprotectedvirtual

Member Data Documentation

◆ deviceRegSet

const std::set< MiscRegIndex > gem5::ArmV8KvmCPU::deviceRegSet
staticprotected
Initial value:

Device registers (needing "effectful" MiscReg writes)

Definition at line 145 of file armv8_cpu.hh.

Referenced by getSysRegMap().

◆ intRegMap

const std::vector< ArmV8KvmCPU::IntRegInfo > gem5::ArmV8KvmCPU::intRegMap
staticprotected
Initial value:
= {
{ INT_REG(regs.sp), INTREG_SP0, "SP(EL0)" },
{ INT_REG(sp_el1), INTREG_SP1, "SP(EL1)" },
}

Mapping between gem5 integer registers and integer registers in kvm.

Definition at line 141 of file armv8_cpu.hh.

Referenced by dump(), updateKvmState(), and updateThreadContext().

◆ miscRegIdMap

const std::vector< ArmV8KvmCPU::MiscRegInfo > gem5::ArmV8KvmCPU::miscRegIdMap
staticprotected
Initial value:

Mapping between gem5 ID misc registers and registers in kvm.

Definition at line 147 of file armv8_cpu.hh.

Referenced by dump(), and startup().

◆ miscRegMap

const std::vector< ArmV8KvmCPU::MiscRegInfo > gem5::ArmV8KvmCPU::miscRegMap
staticprotected
Initial value:
= {
MiscRegInfo(INT_REG(elr_el1), MISCREG_ELR_EL1, "ELR(EL1)"),
MiscRegInfo(INT_REG(spsr[KVM_SPSR_EL1]), MISCREG_SPSR_EL1, "SPSR(EL1)"),
MiscRegInfo(INT_REG(spsr[KVM_SPSR_ABT]), MISCREG_SPSR_ABT, "SPSR(ABT)"),
MiscRegInfo(INT_REG(spsr[KVM_SPSR_UND]), MISCREG_SPSR_UND, "SPSR(UND)"),
MiscRegInfo(INT_REG(spsr[KVM_SPSR_IRQ]), MISCREG_SPSR_IRQ, "SPSR(IRQ)"),
MiscRegInfo(INT_REG(spsr[KVM_SPSR_FIQ]), MISCREG_SPSR_FIQ, "SPSR(FIQ)"),
MiscRegInfo(CORE_REG(fp_regs.fpsr, U32), MISCREG_FPSR, "FPSR"),
MiscRegInfo(CORE_REG(fp_regs.fpcr, U32), MISCREG_FPCR, "FPCR"),
}

Mapping between gem5 misc registers and registers in kvm.

Definition at line 143 of file armv8_cpu.hh.

Referenced by dump(), updateKvmState(), and updateThreadContext().

◆ sysRegMap

std::vector<ArmV8KvmCPU::MiscRegInfo> gem5::ArmV8KvmCPU::sysRegMap
mutableprotected

Cached mapping between system registers in kvm and misc regs in gem5.

Definition at line 150 of file armv8_cpu.hh.

Referenced by getSysRegMap().


The documentation for this class was generated from the following files:
INT_REG
#define INT_REG(name)
Definition: armv8_cpu.cc:68
gem5::ArmISA::MISCREG_CNTV_CTL_EL0
@ MISCREG_CNTV_CTL_EL0
Definition: misc.hh:759
gem5::ArmISA::MISCREG_SPSR_FIQ
@ MISCREG_SPSR_FIQ
Definition: misc.hh:63
SYS_MPIDR_EL1
#define SYS_MPIDR_EL1
Definition: armv8_cpu.cc:71
gem5::ArmISA::MISCREG_CNTKCTL_EL1
@ MISCREG_CNTKCTL_EL1
Definition: misc.hh:768
gem5::ArmISA::MiscRegInfo
MiscRegInfo
Definition: misc.hh:1099
gem5::ArmISA::MISCREG_ELR_EL1
@ MISCREG_ELR_EL1
Definition: misc.hh:614
gem5::ArmISA::MISCREG_SPSR_IRQ
@ MISCREG_SPSR_IRQ
Definition: misc.hh:64
gem5::ArmISA::MISCREG_MPIDR_EL1
@ MISCREG_MPIDR_EL1
Definition: misc.hh:540
gem5::ArmISA::MISCREG_CNTV_CVAL_EL0
@ MISCREG_CNTV_CVAL_EL0
Definition: misc.hh:760
gem5::ArmISA::MISCREG_SPSR_EL1
@ MISCREG_SPSR_EL1
Definition: misc.hh:612
gem5::ArmISA::MISCREG_SPSR_ABT
@ MISCREG_SPSR_ABT
Definition: misc.hh:67
gem5::ArmISA::MISCREG_FPSR
@ MISCREG_FPSR
Definition: misc.hh:622
gem5::ArmISA::MISCREG_FPCR
@ MISCREG_FPCR
Definition: misc.hh:621
CORE_REG
#define CORE_REG(name, size)
Definition: armv8_cpu.cc:63
gem5::ArmISA::MISCREG_SPSR_UND
@ MISCREG_SPSR_UND
Definition: misc.hh:69

Generated on Tue Sep 21 2021 12:27:14 for gem5 by doxygen 1.8.17